CHAPTER 6
INTERRUPTS AND
THE 8259 CHIP
What happens on interrupt?
Micro automatically saves (on stack) the FR (flag register),
IP (instruction pointer), CS (code segement register).
There are 255 interrupts.
The address of the appropriate ISR can be computed by
multiplying the interrupt number by 4!
The 4 bytes in the interrupt vector table contain CS:IP
The address where the ISR is located is
IP <= IP value in table + CS value in table (shifted left one nybble!)
Example: CS value in table is $0001 and IP is $1820 then
ISR routine starts at $11820
Interrupt Vector Table
8088 Interrupt List
Hardware Versus Software Interrupts
INTR (pos level sensitive) and NMI (posedge sensitive)
INT is command that causes software interrupt.
Also, have EXCEPTIONS (SWI that happens automatically w/o INT cmd)
If we only have one INTR pin, does that mean we can only
have one kind of interrupt? NO. 8259 chip will allow us
to have up to 8 AND if we use nine 8259 chips we can have
up to 64!
Condition Codes (Status) Register
ISR Addresses
8259 Programmable Interrupt Controller
8259 Programmable Interrupt Controller Block Diagram
Addresses for 8259 ICWs
ICW1 and ICW2 Formats
INT Numbers
ICW3 and ICW4 Formats
Finding ICWs for a 8259
Addresses for 8259 OCWs
OCW Format for the 8259
Enabling IR0 thru IR7
Issuing the EOI to 8259 Chip
8259 Port Addresses in IBM PC/XT Computer
PC/XT I/O Address Map
IBM PC/XT hardware Interrupts
IBM PC/XT Initialization of 8259
What happens on interrupt?
PC/XT Sources of Hardware Interrupt
PC/XT Sources of NMI Interrupt
PC/XT Port Uses
What caused the NMI?
Ch 6 Problems (part1)
Ch 6 Problems (part 2)
Ch 6 Problems (part 3)