Three Verification
Challenges
Hans Lundén
Digital ASIC
Manager Functional Verification
CHallenges?
› Verification challenge areas
– Quantity of verification work (Integration, complexity)
– Difficulty of verification work (Complexity)
– Efficiency (Quality vs TTM and cost)
– VIP
– Power management
– Exit criteria (Efficiency)
– Languages/Methodologies/Tools
– Design/Systemization for Verification
– TLM in Verification
– ….
Three Challenges | Public | © Ericsson AB 2011 | 2011-10-31 | Page 2
TLM in verification
› Started to use TLM to model ASIC functionality and its
environment.
– Both LT and AT models are used for several purposes.
› System development.
› Early SW development.
› Early system performance investigations
› Planned to be introduced also in verification.
– Early verification test bench and test case development.
› Why?
– TTM (Time To Market)
Three Challenges | Public | © Ericsson AB 2011 | 2011-10-31 | Page 3
Verification IP
› Internal VIPs
– Develop in house or outsource?
– Takes time. New VIPs is always a risk.
› Standard VIP
– Purchase or develop?
› Decision from case to case.
› VIP business not as mature as Design IP business.
› Quality problems in VIPs often revealed very late in projects.
› Why?
– Quality.
Three Challenges | Public | © Ericsson AB 2011 | 2011-10-31 | Page 4
Design for Verification
› “Design” is here including System down to RTL:
– RTL level
› Code to support verification.
– Block architecture
› Partitioning of functions and choice of interfaces between sub blocks
that simplifies verification
– ASIC level
› Re-use
› Minimize number of unique interfaces
› Minimize number updated blocks
– System and product mgmt level
› Minimize number of unique interfaces
› Minimize number of updated functions
› Why?
– Quality and TTM
Three Challenges | Public | © Ericsson AB 2011 | 2011-10-31 | Page 5