Processor Power Management Overview
Agenda
• Introduction
• Overview of all power states
 Global States
 Device States
 CPU States
 PCIe Link PM States
 Sleep States
 AMT States
Page 2
Agenda
• Introduction
• Overview of all power states
 Global States
 Device States
 CPU States
 PCIe Link PM State
 Sleep States
• Reset
• Backup
Page 3
Power Management under ACPI
• Advanced Configuration and Power Management Interface
• New concepts beyond APM
− Fine granularity on CPU clock control
− Multiple system sleeping states
− Individual device management without H/W traps and timers
− Thermal Management
• Primary methodology for current power management.
• Define Power States within the platform.
– Lx States : Link States (for DMI and PEG)
– Dx States : Device States
– Cx States : CPU States.
– Sx States : Sleep (System) States.
– Mx States : ME (AMT)States.
– Gx States : Global States.
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Agenda
• Introduction
• Overview of all power states
 Global States
 Device States
 CPU States
 PCIe Link PM States
 Sleep States
• Reset
• Backup
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-Individual devices can be in Dx and processor
can be in Cx
G3 : no power at all ( no battery or the system
G1/S1: Stop Grant
G2/S5: Soft
Off
is insufficient
supply level to wake)
G1/S3: Suspend
to ram (STR)
G0/S0/C0: Full On
G1/S4: Suspend to Disk (STD)
G0/S0/C1: Auto Halt
G0/S0/C2: Stop Grant
G0/S0/C3: Stop Clock
G0/S0/C4: Stop Clock with lower CPU voltage
G0(Working State)
G0/S0/C5 : Stop Clock with partial power off
- System is running
- Power is on
Sleep /
Hibernate
Wake event
OS initiate
Power off
G1(Sleeping State)
No System Traffic
MCH, ICH and CPU off
G2(Soft Off)
- No System Traffic
- System is off
- Small part of ICH
remains on to accept
wake up event.
Global system state
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PWR plug in &
AFTERG3_EN=0
G3(Mech. Off)
System is unplugged
RTC battery continues
to supply power to RTC
PWR plug in &
AFTERG3_EN=1
Agenda
• Introduction
• Overview of all power states
 Global States
 Device States
 CPU States
 PCIe Link PM States
 Sleep States
• Reset
• Backup
Page 7
Device States : General
D0 Fully-On
•This state is assumed to be the highest level of power consumption.
The device is completely active.
D1 - D2
Optional. Expected to save more power and preserve less device
context than D0. D2 save more power than D1 but the latency is high.
D3 Off
- Power has been fully removed from the device. The device context is
lost when this state is entered, so the OS software will reinitialize.
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Agenda
• Introduction
• Overview of all power states
 Global States
 Device States
 CPU States
 PCIe Link PM States
 Sleep States
• Reset
• Backup
Page 9
CPU States : General
C0 Processor Power State
– Normal state. While the processor is in this state, it executes
instructions.
C1-C5 Processor Power State
– Non executing power state.
– The deeper the C state, the lower the power consumed by the
processor in that state.
• Processor power in C1 is higher than the processor power in C4.
– The deeper the C state, the higher the entry and exit latency
of that state
• Entry/exit latency of C4 is higher than that of C1
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Intel CPU States
State
Entry Method
Bus Masters
Allowed
Notes
C0
--
All
o CPU is executing instructions
C1
AutoHalt inst.
All
o Entered by CPU when it has nothing to do
o Transparent to chipset
C2
Level 2 I/O
read (LvL2)
All
o ICH asserts STPCLK#
o MCH may dynamically assert SLP#
o Most CPU I/F signals are latched
C3
Level 3 I/O
read (LvL3)
only isoc*
o ICH asserts STPCLK#, DPSLP#, STP_CPU#
o MCH or ICH asserts SLP#
o Most CPU I/F signals are latched
Break Event
Interrupt
events (SMI,
SCI..)
Interrupt (Key
stroke, Mouse
Movement,
RTC)
o Bus master
snoop request
o Unmasked
interrupt:
SMI#, NMI#
o CPU break
(FERR#)
C4
Level 4 I/O
read (LvL4)
or C4onC3
only isoc*
o ICH asserts STPCLK#, DPSLP#, STP_CPU#,
DPRSTP#, DPRSLPVR
o Bus master
snoop request
o MCH or ICH asserts SLP#
o Unmasked
interrupt:
SMI#, NMI#
o Most CPU I/F signals are latched
o CPU break
(FERR#)
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Intel CPU States
State
Entry
Method
Bus
Masters
Allowed
Notes
Break
C5/C6
Level 5/6 I/O
read
(LvL5/LvL6)
All
o CPU flushes cache prior to entry, so snoops
aren’t necessary. CPU will be [almost] fully
powered down.
Interrupt
events
o ICH asserts STPCLK#, DPSLP#, STP_CPU#,
DPRSTP#, DPRSLPVR, #PMSYNC
o MCH or ICH asserts SLP#
o Most CPU I/F signals are latched
o Same pins as C4, but different timings and
abbreviated messaging
Page 12
Intel® Deep Power Down Technology (C6)
Flexible C-States to Select Idle Power Level vs. Responsiveness
Page 13
C2 Entry/Exit Sequences
S0/C2 State
S0/C0 State
CPU I/F
Signals
Unlatched
S0/C0 State
Latched
Unlatched
t1
t6
STPCLK#
t2a
t4b
SG
CPU FSB
SG
M-I Link
t2b
GoC2
AckC2
GoC0
t4a
t3a
t3b
t5
Break
Event
Note:
“M-I link” is DMI.
“SG” message on “M-I link” should be “Req-C2”
Page 14
AckC0
C3 Entry Sequences
C0 State
C2 State
C3 State
t10b
STPCLK#
t10a
CPU FSB
M-I Link
t12a
SG
SG
Go- Ack- Wait- ReqC2 C2 C3 C3
Go- AckC3 C3
t12b
CPU_SLP#
t12c
DPSLP#
t13
STP_CPU#
t14
CPU CLK
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Runnin
g
t15
C3 Exit Sequences
Page 16
C4 Entry Sequences
Page 17
C4 Exit Sequences
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C5/C6 Entry Sequences
Page 19
C5/C6 Exit Sequences
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NHM CPU States
• NHM supports C0, C1, C1E, C3, C6 and C7.
• C7 is identical to C6 at core level but different Uncore power
optimization.
• C7 is an overall package state where all cores have lost their
registers, last level cache is at its minimum voltage but uncore is still
in retention voltage
• On NHM, STPCLK#, SLP# and DPSLP# signals are removed
due to platform change and CSI bus interface.
•Not all package C-state will be supported on all versions of
NHM like Uncore power reduction features on C3 and lower
power states maybe fused off in desktop or server parts.
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Agenda
• Introduction
• Overview of all power states
 Global States
 Device States
 CPU States
 PCIe Link PM State
 Sleep States Reset
• Common Questions
Page 22
Link PM States
•L0 – Active state
•TLP(Transaction Layer Packet)’s and DLLP(Data Link Layer Packet)’s
are permitted
•L0s – Low resume latency, energy saving “standby” state:
•no TLP/DLLP during L0s state
•quick entry/exit, exit in the order of 100 ns for Intel chipset
•L0s is single-directional. A transmitter can initiate L0s without the other
port initiating L0s.
•Main power and clocks remain.
•Chipset gates some internal logic.
•L1 – lower power standby state – Higher latency PM state:
•Downstream port initiates when the device power state is programmed to
non D0 state(D3)
•no TLP/DLLP during L1 state.
•Main power and clocks remain.
•Exit in order of micro seconds.
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Link PM States (Contd..)
•L2/3 ready – Staging point for L2/L3 – Required for PCIe PM before
entering L2 or L3 state, this is not a real link state, it is just a phase
requiring protocol handshake before entering L2 or L3.
•A device must be in D3 state before entering L2/3 ready
•System will place link L2/3 ready state before entering S3/S4/S5.
•L2 – Auxiliary powered Link deep energy state. L2 is optionally
supported.
•Main power and clks are removed
•the device has aux power to perform link reactivation through
beacon, WAKE#, PME context and detection logic.
•L3 – Link off state. Zero power state.
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Link PM States (Contd..)
Summary of Link PM States:
L-State
Description
Used By SW
Directed PM
Used By ASPM
L0
Fully Active
Yes(D0)
Yes (D0)
L0s
Standby
No
Yes(D0)
L1
Lower Power
Standby
Yes(D1-D3hot)
Yes(D0)
L23
Ready
Staging point
for power
removal
Yes (links to
PME_turn_off
message )
No
L2
Low Power
Sleep State
Yes
No
L3
Off (No Vaux)
N/A
No
Ldn
Transitional
State before L0
Yes
No
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Link PM States (Contd..)
ASPM Control: Allows Hardware controlled
PCIe dynamic link power reduction.
Value
Description
00 – Disabled
•Port must not bring a Link into L0s state.
•Port must not initiate a PM_active_State_Request_L1 DLLP to other end
of the link
•Port receiving a L1 request from other agent must respond with negative
acknowledgement.
01b – L0s Entry
Enabled
•Port must bring a Link into L0s state when all conditions are met.
•Port must not initiate a PM_active_State_Request_L1 DLLP to other end
of the link
•Port receiving a L1 request from other agent must respond with negative
acknowledgement.
10b – L1 Entry
Enabled
•Port’s transmitter must not bring a Link into L0s state.
•Port may issue a PM_active_State_Request_L1 DLLP to other end of the
link
•Port receiving a L1 request from other agent must respond with positive
acknowledgement.
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Link PM States (Contd..)
ASPM Control:
Value
Description
11b – L0s and L1
Entry Enabled
•Port’s transmitter must bring a Link into L0s state.
•Port may issue a PM_active_State_Request_L1 DLLP to other end of the
link
•Port receiving a L1 request from other agent must respond with positive
acknowledgement.
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Link PM States (Contd..)
Relationship between Link and Device PM
State.
Device
State
Permissible Interconnect
Link State
D0
L0, L0s, L1 (ASPM)
D1
L1
D2
L2
D3hot
L1, L2/L3 ready
D3cold
L2, L3
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System and DMI Link Power States
System
States
CPU
State
Description
Link
State
SW Controlled
S0
C0
Fully Operation. Opportunistic Link
Active State
L0/L0
s/L1
N/A
S0
C1
CPU Auto Halt
L0/L0
s/L1
Yes
S0
C2
CPU Stop Clock
L0/L0
s/L1
Yes
S0
C3
Deep Sleep: CPU’s clock halted via
STP_CPU# assertion. MCH and ICH still
being clocked
L0/L0
s/L1
Yes
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System and DMI Link Power States
System
States
CPU
State
Description
Link
State
SW Controlled
S0
C4
Deeper Sleep: CPU’s clock halted via
STP_CPU# assertion and CPU’s voltage
lowered.
L0/L0
s/L1
Yes
S1/S1D
C2
S1D same as C2
L0/L0
s/L1
Yes
S3/S4/
S5
N/A
STR/STD/Off
L3
Yes
Page 30
Agenda
• Introduction
• Overview of all power states
 Global States
 Device States
 CPU States
 PCIe Link PM State
 Sleep States
• Reset
• Backup
Page 31
Sleep States – User Point of View
State
Common Names
Description
S1
Stand By,
Entered by pressing sleep button, closing lid, system idle, etc.
System appears mostly off (LED’s may indicate Stand By).
Common wake events include power button, sleep button, mouse
movement, modem ring, etc. System wakes quickly and all
programs are still running.
Powered on Suspend
(refers to S1M state –
last supported on ICH5)
S2
S3
Not supported by Intel chipsets
Stand By,
Suspend to RAM
To user, appears the same as S1, but in mobile system the battery
can maintain S3 much longer. Wake will take longer than S1, but
still very fast.
S3 is “suspend” when pressing Fn + F4.
S4
Hibernate,
Suspend to Disk
Entered by user direction or system idle. System appears off.
Most common wake event would be power button, but all others
are still possible. System takes longer to wake than S3, but all
programs are still running.
S4 is “hibernate” when pressing Fn + F12.
S5
Shut Down,
Soft Off
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Entered by user direction (Start -> Shut Down). Very similar to S4,
but a full boot occurs on wake (no programs remain running from
previous S0). Desktop must stay plugged in, laptop must have
charged battery, otherwise platform is in G3.
Sleep State Entry Sequence
S0
S1
S3
t53b
STPCLK#
DMI
REQ
- C2
CPUSLP#
Go
C2
-
Ack
- C2
Go
-
S3
t56 +t58
t59
SLP_S3#
SLP_S5#
Page 33
L3
t55
PLTRST#
SLP_S4#
L2/
- S3
t53c
SUS_STAT#
PWROK#
Ack
t60 (for S3
- Cold only)
t61
t62
S4
S5
Sleep State Exit Sequence
Page 34
Agenda
• Introduction
• Overview of all power states
 Global States
 Device States
 CPU States
 PCIe Link PM State
 Sleep States Reset
 AMT Status
•
Page 35
ME impact on Sleep States
Page 36
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Page 39
Thank You
Page 40