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HT7017 User Manual (P73-13-46)
HT7017
User manual
Juquan Optoelectronics Technology (Shanghai) Co., Ltd.
Tel:
Fax:
021-51035886
021-50277833
Email: sales@hitrendtech.com
Web:http://www.hitrendtech.com
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Version update instructions
Modify content
version number
Change the time
V1.3
2014-6-15
1.Create a first draft.
V1.4
2014-9-26
1.removeAUTO_DC, Modify the DC calibration method,Modify the corresponding registerI1off,
I2off,Uoffinstruction of.
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Head
record
1.Chip Overview................................................ ................................................................. ....................................................4
1.1.
1.2.
1.3.
1.4.
Chip Introduction................................................ ................................................................. .............................4
Chip Characteristics................................................ ................................................................. .............................4
Overall block diagram................................................ ................................................................. .............................5
Pin definition................................................ ................................................................. ............................5
2.Power management................................................ ................................................................. ....................................................7
2.1.
2.2.
Operating mode................................................ ................................................................. .............................7
System reset................................................ ................................................................. .............................7
3.System functions................................................ ................................................................. ....................................................8
3.1. A/DConversion................................................ ................................................................. ............................8
3.2.VREFParameter Description................................................ ................................................................. ............8
3.3.
3.4.
3.5.
3.6.
3.7.
3.8.
3.9.
3.10.
Sampling waveform function................................................ ................................................................. .....................8
Effective value measurement................................................ ................................................................. .....................8
Active power calculation................................................ ................................................................. .....................9
Reactive power calculation................................................ ................................................................. .....................9
Apparent power calculation........................................ ................................................................. .....................9
Power/Frequency Conversion........................................ ................................................................. ............10
Starting/creep........................................ ................................................................. ............................10
Interrupt source................................................ ................................................................. .............................10
4.Communication Interface................................................ ................................................................. ....................................................11
4.1. UARTinterface................................................. ................................................................. .....................11
5.register................................................. ................................................................. .................................................................15
5.1.
5.2.
Measurement parameter register................................................ ................................................................. ............15
Calibration parameter register................................................ ................................................................. .............twenty four
6.Electrical Specifications................................................ ................................................................. ....................................................46
6.1.
6.2.
Absolute Maximum Ratings........................................ ................................................................. .............46
Electrical Characteristics........................................ ................................................................. .............................46
7.Calibration process................................................ ................................................................. ........................................48
8.Chip packaging................................................ ................................................................. ....................................................52
8.1. HT7017(SSOP16)........................................................ ................................................................. ....52
9.typical application................................................ ................................................................. ....................................................53
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1.Chip overview
1.1. Chip introduction
HT7017It's a beltUARTHigh-precision single-phase multi-function metering chip with communication
interface. The operating voltage range of the chip is4.5~5.5V. The working crystal oscillator is6MHz.
1.2. Chip characteristics
-
Three-way22 bit Sigma-Delta ADC support5000:1The dynamic range can obtain
the active power and reactive power of two metering channels at the same time.
Supports active, reactive, apparent power and active energy pulse output
Able to get three channels at the same timeADCThe effective value of the channel, and the frequency support of the voltage
channelUARTcommunication method
Interrupt support: zero-crossing interrupt, sampling interrupt, power pulse interrupt, calibration interrupt, etc. NORMAL
Power consumption when running at full speed<4.5mA
Power monitoring function:LBORFunction
SSOP 16
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1.3. Overall block diagram
I2IN+
2levelADC
DEC filter
PGA
I1IN-
2levelADC
PGA
I1IN+
PGA
VIN+
VIN-
2levelADC
DEC filter
DEC filter
PF
Pulse
output
EMU
Tx
RX
General
Register
VREFO
Voltage
Interface
Reset
Reference
Power
Clock
Monitor Unit
Generator
DVCC
picture1-1
AVCCCLKINCLKOUT
Overall chip block diagram
1.4. Pin definition
1.4.1.PINPin package diagram
ssop16,3roadADC+1roadCF
16
VDD1P8
2
15
/RST
3
14
DVDD
AVCC
1
V3P
V3N
V2P
4
V1P
5
HT7017
16PIN
13
XTALO
12
XTALI
V1N
6
11
Tx
VREF
7
10
RX
AGND
8
9
PF
picture1-4
HT7017chipPINPin package diagram
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1.4.2. HT7017chipPINFoot function description
serial number
PINname
type
PINillustrate
1
AVCC
POWER
Analog power input,4.5v~5.5v
2
V3P
INPUT
Voltage input channel positive; (VP-VN)scope±800mvPeak, common mode0V.
3
V3N
INPUT
Voltage input channel negative
4
V2P
INPUT
current channel2Enter positive;
5
V1P
INPUT
current channel1Enter positive;(VP-VN)scope±800mvPeak, common mode0V.
6
V1N
INPUT
current channel1Enter negative
7
VREF
OUTPUT
ADCReference voltage output, typical2.5V, external0.1uFcapacitance
8
AGND
GND
Analogly
9
PF
OUTPUT
5Voutput
PPulse output
10
RX
INPUT
5Venter
UARTCommunication, serial port receives data input
11
Tx
OUTPUT
5Voutput
UARTDuring communication, serial port data output,defaultThe output is in a high-impedance state, and the user needs to
pull it up externally.
12
XTALI
INPUT
crystal oscillator6MHzinput, this pin andXTALONo need to connect between10Mresistance
13
XTALO
OUTPUT
crystal oscillator6MHzoutput, this pin andXTALINo need to connect between10Mresistance
14
DVDD
POWER
Digital power input:4.5v~5.5v
15
RST\
INPUT
5Venter
Chip reset pin, active low level, this pin defaults to internal strong pull-up, when the
pin is greater than200usWhen low level, the chip resets
16
VDD1P8
POWER
number1.8VOutput, external connection0.1uf+1ufcapacitance
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2.Power management
2.1. Working mode
HT7017Can only work in normal mode, noSleepmodel.
2.2. System reset
There is a power detection module inside the chip to detect changes in the system power supply. When it is lower than the detection threshold, the chip resets.
parameter name
Min
Type
Max
Parameter unit
Detect voltag(Falling)
-
4.1
-
V
Release voltage(Rising)
-
4.2
-
V
System cold reset time: GiveHT7017Provide power, wait for the crystal oscillator to start oscillating andHT7017Internal power system establishment requires20ms time
before the internal registers can be manipulated.
System warm reset time: writeSRSTREGPerform a software reset or/RSTPINThe hot reset mode of pull-high reset requires waiting after reset under the premise that the
system power supply and external crystal oscillator are working normally.2msOnly then can the register be manipulated.
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3.System functions
3.1.A/DConvert
parameter name
Min
Type
Max
Parameter unit
Full scale (peak value)
±800
mV
ADCBit stream frequency
1
MHz
Current channel gain
1times,4times,8times,16times,twenty fourtimes
voltage channel gain
1times,2times,4times
3.2.VREFParameter Description
parameter name
Min
Type
Max
Parameter unit
central value
2.5
V
Temperature Coefficient
10
ppm
3.3. Sampling waveform function
(1) supports three channelsADCSampling data output,ADCThe waveform sampling data is updated at a speed of 0.976kHz, the
fastest can be through the registerFreCFG[2..0](41H)Configuration reaches15.62kHz
Note: When external crystal oscillator is not used6MHz, and adopt5.5296MHzcase,ADCThe waveform sampling data refresh speed is by default
0.9kHz, the fastest can be passed through the registerFreCFG[2..0](41H)Configuration reaches14.4kHz
3.4. Effective value measurement
(1) supports three channels at the same timeADCChannel effective value measurement supports two current channel effective value small signal offset correction, which is used to
correct when the current channel input signal is0When, there is zero drift in the effective value register.
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3.5. Active power calculation
3.6. Reactive power calculation
3.7. Apparent power calculation
Apparent power is calculated by multiplying the effective voltage and current values.
S=Urms×Irms
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3.8. Power/frequency conversion
Note: The energy unit accumulated by the fast pulse register is1/HFConst.
3.9. Start/Creep
via registerEMUSR(19H)BitNoPldandNoQldTo indicate whether the chip is in a creeping state, if it is creeping, the flag is set. The
chip uses power to make startup/creeping judgments.
3.10. Interrupt sources
Interrupt flag registerEMUIFAll flags in can be read, but there is no external pin level output.
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4.Communication Interface
4.1.UARTinterface
4.1.1.Overview
(1) works in slave mode, half-duplex communication,9BitUART(including even parity bit), conforms to the standardUARTprotocol. (
2)HT7017Fixed baud rate4800bps. (3) The data frame structure contains the check byte sumACKfeedback byte
4.1.2. UARTInterface Description
HT7017:
(1)RX:HT7017data receiving pin. (2)Tx:
HT7017data sending pin.
4.1.3. UARTInterface diagram
1
16
2
15
3
4
5
6
HT7017
16PIN
Host
14
13
12
11
Tx
7
10
RX
8
9
Slave data sending
Slave data reception
RX(orI/Omouth)
Tx(orI/Omouth)
HT7017 UARTInterface diagram
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4.1.4. UARTsingle byte format
T
Start
D0
Bit
D1
D2
D3
D4
D5
D6
D7
Parity
Bit
Stop
Bit
1Bytes of information required for transmission11bit
baud rate1/T
4.1.5. HT7017 UARTCommunication command frame format
HEAD
DATA
CMD[7...0]
CHKSUM/ACK
Fixed:0x6A W/R+Address
MSB
LSB
name
explain
HEAD
Transmission byte frame header, fixed to0x6A
CMD[7…0]
Command byte, sent by the host
CMD[7]For the command category: 0: read operation
1: Write operation
CMD[6:0]For those that require operationHT7017Register address
DATA
Data bytes, read operations are performed by the slave side (HT7017) is sent, and the write operation is sent by the host
side. Read register is fixed3Byte transfer; write register is fixed2Bytes are transferred, high byte first.
CHKSUM
Checksum: During read operation, it is determined by the slave side (HT7017) is sent, and is sent by the host during write operations. The
checksum algorithm is as follows:
CHKSUM[7...0] =HEAD[7...0]+CMD[7...0]+DATAn[7...0]+ ...+DATA1[7...0]
That is, each data in the command frame is added, the carry bit is discarded, and the final result is inverted bit by bit.
ACK
During write operation, the slave side (HT7017) indicates whether the checksum sent by the user is consistent with the checksum
calculated internally by the slave machine. If they are consistent,ACKfor0x54, if inconsistent thenACKfor0x63. ACKThe response time is
the slave side (HT7017) After receiving the data26usrespond later.
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4.1.6. HT7017 UARTCommunication write operation format
One frame of communication data ends
New communication frame data starts
host pairHT7017perform write operation
host pairHT7017perform write operation
HEAD
HT7017RXD
CMD
DATA1
DATA0
HEAD
CHKSUM
CMD
DATA1
Fixed:0x6A W/R+Address
LSB
MSB
HT7017TX
ACK
D
feedbackACKSignal
Write operation characteristics
illustrate
9BitUART
A single byte of information consists of11bitComposition, respectively: start bit + data bit + parity bit + stop bit
6Bytes fixed
Each write operation data frame is6A fixed length of bytes. If the master sends a checksum and the slave detects that it is
length transfer
inconsistent with the received checksum, the frame data will not be written.HT7017register, and will also giveACK Signal.
Byte transfer
For double-byte registers, when the data frame is written, the high-order bit comes first and the low-order bit comes last. For single-byte registers, when
order
the data frame is written, the high bits are filled0, the low bit is the data that the user needs to write.
write protect
The user needs to write a write enable command before writing to the register.
Error handling
Mistake 1: Data headerHEADIf there is an error, the byte is discarded and the next byte is re-judged whether the data header is received
correctly.
Mistake 2: ChecksumCHECKSUMIf the comparison is wrong, the slave will abandon the frame data and return the
correspondingACK Signal(0x63).
4.1.7. HT7017 UARTCommunication read operation format
One frame of communication data ends
New communication frame data starts
host pairHT7017perform read operation
HT7017
HEAD
RXD
host pairHT7017perform read operation
CMD
HEAD
CMD
Fixed:0x6A W/R+Address
HT7017
DATA2
TxD
DATA1
DATA0
MSB
CHECKSUM
DATA2
LSB
Read operation characteristics
illustrate
9BitUART
A single byte of information consists of11bitComposition, respectively: start bit + data bit + parity bit + stop bit
6Bytes fixed
Each read operation data frame is6fixed length of bytes, the slave returns after receiving the command4bytes indicating the
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length transfer
The read operation ends, this4bytes contain3register data bytes and1checksum bytes.
Byte transfer
For multi-byte registers, when the data frame is output, the high bit is first and the low bit is last. for deficiencies3byte register,HT7017
order
The internal registers are aligned with the low bits of the data frame.
Error handling
Mistake 1: Data headerHEADIf there is an error, the byte is discarded and the next byte is re-judged whether the data header is received
correctly.
4.1.8. HT7017 UARTCommunication timeout protection mechanism
HT7017ofUARTCommunication provides a timeout protection mechanism, stipulatingbyteandbyteThe interval between them must not exceed a certain value (20ms
),otherwiseUARTThe module automatically resets. Specific steps are as follows:
(1) everybyteofStart Bit, the counter is cleared and starts counting;
(2) when the counter overflows (exceeds20ms),butUARTThe module automatically resets, the counter is cleared and stops counting; (3) After the complete data
frame transmission/reception is completed, the counter is cleared and stops counting.
4.1.9.HT7017ofUARTCommunication checksum
(1)BCKREG: will save the last timeUARTCommunicationBUFFThe value of the data (this register is to ensureUARTaccuracy of
communications,UARTThe write operation is2bytes,BCKREGThe high byte is invalid)
.
(2)ComChecksum:rightUARTReading the checksum register of the transmission data frame will cause the checksum register to be recalculated
each timeUARTCommunication commands (includingHEADandCMD)and data are accumulated and put intoComChecksumThe lower two bytes
of the register.ComChecksumheight of8Bitbit16….bit23will saveUARTCommunication of the last command.UARTThe data in communication is
the addition of single-byte length. (This register is to ensureUARTaccuracy of communications). (3)BCKREGandComChecksumThe
communication check register can be selected by the user when using it. (4)SumChecksum: Accumulate all calibration registers, and put the
accumulated results into a3Byte parameters and registers are updated at a fixed time, so the user can determine whether there is an error by
querying whether the data in this register has changed.
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5.register
5.1. Measurement parameter register
5.1.1.Measurement parameter register list
surface5-1Metering parameter register list (Read Only)
address
name
00H
Spl_I1
3
current channel1ofADCsampled data
01H
Spl_I2
3
current channel2ofADCsampled data
02H
Spl_U
3
voltage channelADCsampled data
06H
Rms_I1
3
current channel1Valid values of
07H
Rms_I2
3
current channel2Valid values of
08H
Rms_U
3
RMS value of voltage channel
09H
Freq_U
2
Voltage frequency
0AH
PowerP1
3
Active power of the first channel
0BH
PowerQ1
3
First channel reactive power
0CH
Power_S
3
inspecting power
0DH
Energy_P
3
Active energy
0EH
Energy_Q
3
Reactive energy
0FH
Energy_S
3
apparent energy
10H
PowerP2
3
Second channel active power
11H
PowerQ2
3
Second channel reactive power
12H
MAXUWAVE
3
voltage waveform peak register,22bit,andADCThe number of digits is the same
16H
BackupData
3
Communication data backup register
17H
COMChecksum
2
Communication checksum register
18H
SUMChecksum
3
Calibration parameter checksum register
19H
EMUSR
2
EMUstatus register
1AH
SYSSTA
1
system status register
1BH
ChipID
3
ChipID, the default value is7053B0
1CH
DeviceID
3
DeviceID, the default value is705304
Byte length
Function description
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5.1.2.Measurement parameter register description
5.1.2.1. ADCWaveform Register (SPLI1,SPLI2,SPLU)
Address:00H
Current 1 wave Register (SPLI1)
Bit21
20
19
18…3
2
1
Bit0
Read:
SPLI121
SPLI120
SPLI119
SPLI118…SPLI13
SPLI12
SPLI11
SPLI10
Write:
X
X
X
X
X
X
X
Reset:
0
0
0
0
0
0
0
Address:01H
Current 2 wave Register (SPLI2)
Bit21
20
19
18…3
2
1
Bit0
Read:
SPLI221
SPLI220
SPLI219
SPLI218…SPLI23
SPLI22
SPLI21
SPLI20
Write:
X
X
X
X
X
X
X
Reset:
0
0
0
0
0
0
0
Address:02H
Voltage wave Register (SPLU)
Bit21
20
19
18…3
2
1
Bit0
Read:
SPLU21
SPLU20
SPLU19
SPLU18…SPLU3
SPLU2
SPLU1
SPLU0
Write:
X
X
X
X
X
X
X
Reset:
0
0
0
0
0
0
0
Notice:
The update speed of the waveform register is determined by the clock configuration registerFreqCFG. [2:0]of3indivualbitcontrol. this3
The effective number of registers istwenty twoBit,bit21is the sign bit, and the sign bit extends totwenty fourbits, that is to say, among the
data bits read outbit23—bit21They are all sign bits. ShouldADCThe waveform register is data that has not passed through Qualcomm and is
ADC Uncorrected raw data output. Data is in two's complement format.
5.1.2.2.Valid value output (I1Rms, I2Rms, URms)
Address:06H
Current 1 Rms Register (I1Rms)
Bit23
twenty two
twenty one
20…3
2
1
Bit0
Read:
I1S23
I1S22
I1S21
I1S20…I1S3
I1S2
I1S1
I1S0
Write:
X
X
X
X
X
X
X
Reset:
0
0
0
0
0
0
0
20…3
2
1
Bit0
Address:07H
Current 2 Rms Register (I2Rms)
Bit23
twenty two
twenty one
Read:
I2S23
I2S22
I2S21
I2S20…I2S3
I2S2
I2S1
I2S0
Write:
X
X
X
X
X
X
X
Reset:
0
0
0
0
0
0
0
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Address:08H
Voltage Rms Register (Urms)
Bit23
twenty two
twenty one
20…3
2
1
Bit0
Read:
US23
US22
US21
US20…US3
US2
US1
US0
Write:
X
X
X
X
X
X
X
Reset:
0
0
0
0
0
0
0
Notice:
Valid valuesRmsyestwenty fourAn unsigned number of bits, the highest bit is always0. whenEMUThe clock frequency is1MHzWhen , the parameter
.
update frequency defaults to3.8Hz,ConfigurableFreqCFG[6:5]to the highest15.2Hz(ConfigurationEMUThe clock is2Mfor7.6Hz)
If the user needs to get a more accurate effective value register value when the signal is small, he needs to passI1RMSOFFSETand
I2RMSOFFSETThese two registers perform zero drift correction on the effective value.
5.1.2.3.Voltage frequency measurement (UFREQ)
Voltage Frequency Register (UFREQ)
Address:09H
Bit15
14
13
12…3
2
1
Bit0
Read:
Ufreq15
Ufreq14
Ufreq13
Ufreq12…Ufreq3
Ufreq2
Ufreq1
Ufreq0
Write:
X
X
X
X
X
X
X
Reset:
0
0
0
0
0
0
0
Notice:
The frequency value is a16An unsigned number of bits, the parameter formatting formula is:
Frequency=
femu
(UFREQ×2)
in:
f——External crystal frequencyCLKIN femu
——Metering module working frequency
For example, if the system clockCLKIN =6MHz,EMUclock(femu) selected as1MHz,register
UFREQ=10000, then the actual measured frequency is:Frequency=1M/2/10000=50Hz.
system clockCLKIN =5.5296MHz,EMUclock(femu) selected as0.92KHzWhen , the calculation result of the
above example is:Freq=5.5296M/6/2/1000=46.08Hz.
5.1.2.4.Power parameter output (PowerP1, PowerQ1, PowerS)
Address:0AH
Active Power Register (PowerP1)
Bit23
twenty two
twenty one
20…3
2
1
Bit0
Read:
AP23
AP22
AP21
AP20…AP3
AP2
AP1
AP0
Write:
X
X
X
X
X
X
X
Reset:
0
0
0
0
0
0
0
20…3
2
1
Bit0
Reactive Power Register (PowerQ1)
Bit23
twenty two
Address:0BH
twenty one
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Read:
RP23
RP22
RP21
RP20…RP3
RP2
RP1
RP0
Write:
X
X
X
X
X
X
X
Reset:
0
0
0
0
0
0
0
20…3
2
1
Bit0
Address:0CH
Apparent Power Register (PowerS)
Bit23
twenty two
twenty one
Read:
SP23
SP22
SP21
SP20…SP3
SP2
SP1
SP0
Write:
X
X
X
X
X
X
X
Reset:
0
0
0
0
0
0
0
Notice:
The power istwenty fourBit two's complement format, the highest bit is the sign bit, and the parameter update frequency is3.8Hz(EMUThe clock
frequency is1MHz, configurationEMUThe clock is2MHztime is7.6Hz)
First channel power parametersPowerP1,PowerQ1is two's complement format,twenty fourbit data, the highest bit of which is the sign bit. PowerSAccording to the
channel selected by the user, the apparent power of the first or second channel is output.
Let the data in the register bePowerP1, it is used for calculationPregfor:
Preg=PowerP1
Preg=PowerP1-2 2̂4
;ifPowerP1<2 2̂3
;ifPowerP1>=2 2̂3
Let the displayed active power beP, the conversion coefficient isikB
,but: P=Preg×Kpqs
ikBWhen the power input is rated active power, the rated power andPowerP1ratio of readings.
Coefficients for displaying reactive power and apparent power and coefficients for active powerikBsame.
example:
enter1000wActive power,PowerP1The average reading is0x00C9D9(51673)
,but ikB=1000/51673=0.01935
whenPowerP1The reading is0xFF4534When , the power value it
represents is: P=Kpqs*Preg=0.01935*(-47820)=-925.3w inPreg=
PowerP1-2 2̂4=-47820
5.1.2.5.Electric energy parameter output (EnergyP, EnergyQ, EnergyS)
Address:0DH
Active Energy Register (EnergyP)
Bit23
twenty two
twenty one
20…3
2
1
Bit0
Read:
EP23
EP22
EP21
EP20…EP3
EP2
EP1
EP0
Write:
X
X
X
X
X
X
X
Reset:
0
0
0
0
0
0
0
Notice:
The energy accumulation register is configured to be unclear after reading by default.0, can be passed through the register
EMUCFG.13(EnergyClr) Configure this register to clear after reading0type, the energy represented by the smallest unit of this register is1/EC
kWh. Example: The pulse constant is3200imp/kWh, the register reading is0x001000(4096), the energy it represents is
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E=4096/3200=1.28kWh
Address:0EH
Reactive Energy (EnergyQ)
Bit23
twenty two
twenty one
20…3
2
1
Bit0
Read:
EQ23
EQ22
EQ21
EQ20…EQ3
EQ2
EQ1
EQ0
Write:
X
X
X
X
X
X
X
Reset:
0
0
0
0
0
0
0
Notice:
The energy accumulation register is configured to be unclear after reading by default.0, can be passed through the registerEMUCFG.13(EnergyClr)
Configure this register to clear after reading0type, the energy represented by the smallest unit of this register is1/EC kWh.
Address:0FH
Apparent Energy (EnergyS)
Bit23
twenty two
twenty one
20…3
2
1
Bit0
Read:
ES23
ES22
ES21
ES20…ES3
ES2
ES1
ES0
Write:
X
X
X
X
X
X
X
Reset:
0
0
0
0
0
0
0
Notice:
The energy accumulation register is configured to be unclear after reading by default.0, the energy represented by the smallest unit of this register is1/EC kWh. The energy
register is not cleared by default after being read, and can also be modified.EnergyClr=1, so that the energy register is cleared after reading.
5.1.2.6.Power parameter output (PowerP2, PowerQ2)
Address:10H
Active Power Register (PowerP2)
Bit23
twenty two
twenty one
20…3
2
1
Bit0
Read:
AP23
AP22
AP21
AP20…AP3
AP2
AP1
AP0
Write:
X
X
X
X
X
X
X
Reset:
0
0
0
0
0
0
0
twenty two
twenty one
20…3
2
1
Bit0
Address:11H
Reactive Power Register (PowerQ2)
Bit23
Read:
RP23
RP22
RP21
RP20…RP3
RP2
RP1
RP0
Write:
X
X
X
X
X
X
X
Reset:
0
0
0
0
0
0
0
Notice:
The power istwenty fourBit two's complement format, the highest bit is the sign bit, and the parameter update frequency is
3.8Hz(EMU The clock frequency is1MHzWhen, configureEMUThe clock is2MHztime is7.6Hz)
5.1.2.7.Voltage Peak Register (MAXUWAVE)
MAX Votage(MAXUWAVE)
Address:12H
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Bit21
20
19
18…3
2
1
Bit0
Read:
SU_21
SU_20
SU_19
SU_18…SU_3
SU_2
SU_1
SU_0
Write:
X
X
X
X
X
X
X
Reset:
0
0
0
0
0
0
0
voltage peak register, andSAG,PEAKFunction-related, after user-specifiedADCAfter the cycle, the register is updated to obtain theADCThe
maximum value (absolute value) of the waveform, this register is taken from the data after high pass, in order to sumADCThe number of bits is
aligned, this register is22bit.bit21is the sign bit, and the sign bit extends totwenty fourbits, that is to say, among the data bits read outbit23—
bit21They are all sign bits. Data is in two's complement format.
5.1.2.8.Data backup register (BCKREG)
Address:16H
BackupData Register (BCKREG)
20…3
2
1
Bit0
Read:
BCKData23
BCKData22
BCKData21
BCKData20…..BCKData3
BCKData2
BCKData1
BCKData0
Write:
X
X
X
X
X
X
X
Reset:
0
0
0
0
0
0
0
Bit23
twenty two
twenty one
Backup DataThe register is saved lastUARTThe data transmitted by communication, a total of3bytes,
RepresentingUART
Communication reads data or the high, middle and low bytes of the last written data (UARTwritten as2Bytes, at this time, the
high byte of this register is an invalid byte)
.
5.1.2.9.Communication checksum register (Check)
ComChecksum Register (Ccheck)
Address:17H
Bit23
twenty two
twenty one
20…3
Ccheck20…..Ccheck 3
2
1
Bit0
Check 2
Check 1
Check 0
Read:
Ccheck23
Check 22
Check 21
Write:
X
X
X
X
X
X
X
Reset:
0
0
0
0
0
0
0
Communication checksum register:
every timeUARTCommunication commands and data are accumulated and put intoComChecksumThe lower two bytes of the
register. ComChecksumheight of8Bitbit16….bit23will saveUARTCommunication of the last command.UARTThe data in
communication is the addition of single-byte length.
5.1.2.10.Parameter checksum register (Check)
Address:18H
SumChecksum Register (Scheck)
Bit23
Read:
Scheck23
twenty two
twenty one
Scheck22
Scheck21
20…3
Scheck20….. Scheck3
2
1
Bit0
Scheck2
Scheck1
Scheck0
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Write:
X
X
X
X
X
X
X
Reset:
0
0
0
0
0
0
0
The parameter sum check register is the sum of all calibration parameter registers,40H---7CH, where the portion of the continuous address that does not
have a register allocated is not included in the calculation.DefaultThe value is0x0100BD.
(The calculation does not include72H-74Hregister)
CheckThe register is calculated as:
Use three-byte unsigned addition for all check registers, and high-order complement of two/single-byte registers.0. If the calibration table register has
been configured, the checksum register will be updated immediately, and the waiting time is2usleft and right, can be ignored.
5.1.2.11.EMUstatus register(EMUSR)
Address:19H
EMU Register Status (EMUSR)
Bit7
6
5
Read:
Chanelstatus
TAMP
I2PPXGTI1P
Write:
X
X
X
Reset:
0
0
Bit15
14
3
2
1
Bit0
NoQD
NoPLd
REVQ
REVP
X
X
X
X
X
0
0
0
0
0
0
13
12
11
10
9
Bit8
Checksum
NoQLd2
NoPLd2
NoQLd1
NoPLd1
Read:
4
Err
Write:
X
X
X
X
X
X
X
X
Reset:
0
0
0
0
0
0
0
0
Bit name
describe
Checksum Err
After enabling the internal checksum comparison function, calculate the checksum and write toSUMCHECKThe value is different. 1:
Checksum error
NOQLD2
No.2Channel reactive power creeping flag (needs to be turned on75H.bit5:En_NewStatus)
NOPLD2
No.2Channel active power creeping flag (needs to be turned on75H.bit5:En_NewStatus)
NOQLD1
No.1Channel reactive power creeping flag (needs to be turned on75H.bit5:En_NewStatus)
NOPLD1
No.1Channel active power creeping flag (needs to be turned on75H.bit5:En_NewStatus)
Chanelstatus
Metering channel status flag.
(0: Indicates the use of current channels1Measurement1: Indicates the use of current channels2
Note1
Note1
measurement)
TAMP
Sign of power theft. (1: Electricity theft occurs)Note1
I2PPXGTI1P
The effective value (power) of the second channel is greater than the effective value (power) mark of the first channel. 1:
The second channel is larger than the first channel
NOQLD
Note1
Current metering channel reactive power creeping flag,This flag is updated at the same rate as the power register and defaults to
3.8Hz.NOQLD=1: Reactive power is in a latent state
NOPLD
Current metering channel active power creeping flag, this flag is updated at the same speed as the power register, and the default is
3.8Hz.NOPLD=1: Active power is in a latent state
REVP
Active power reverse sign,PFUpdate when pulsing, and the flag is updated at the beginning of the
pulse. REVP=1: Active power reverse
REVQ
Reactive power reverse flag,QFUpdate when pulsing, and the flag is updated at the beginning of the
pulse. REVQ=1: Reactive power reverse
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TAMPDescription of power theft indicator signs:
If you choose a valid value as the basis for judging against electricity theft (tampsel=0):
whenI1Rms>I2Rms*(1+IChk)orI2Rms>I1Rms*(1+IChk), this flag takes effect.
If active power is selected (PowerP) as a basis for judgment against electricity theft (tampsel=1):
When |PowerP1|>|PowerP2|*(1+IChk)or |PowerP2| >|PowerP1|*(1+IChk)This flag works when
use.
=0Indicates that no electricity theft has occurred.i1RmsandI2Rmsare less thanIPTAMPThe set threshold, or less than the set
thresholdikB range or |PowerP|and |PowerPPX|no more thanikkscope.
I2PPXGTI1Pillustrate:
If you choose a valid value as the basis for judging against electricity theft (tampsel=0):
=1expressI2Rms>I1Rms;=0expressI2Rms≤I1Rms.
If you select active power (|PowerP|) is used as the basis for judgment against electricity theft (tampsel=1) :
=1Representation |PowerP2|>|PowerP1|;=0Representation |PowerP2|<=|PowerP1|.
Note1:ATT705BU/7059SShouldbitThe readout is invalid.
5.1.2.12.System Status Register (SYSSTA)
Address:1AH
System status Register (SYSSTA)
Bit7
6
5
4
Read:
3
2
1
Bit0
TEST_RST
E_RST
LBOR
WREN
Write:
X
X
X
X
X
X
X
X
Reset:
0
0
0
0
0
0
1
0
Bit name
describe
TEST_RST
TESTIf the pin change causes the chip to reset, this flag is set and cleared after reading.0
E_RST
RESETIf the pin change causes the chip to reset, this flag is set and cleared after reading.0
LBOR
If the system power supply drops and causes the chip to reset, this flag will be set and cleared after reading.0
WREN
Write enable flag (0: Indicates write enable is turned off1: Indicates that write enable is turned on)
Notice:
BORReset to highest priority, occursLBORReset willTEST_RSTandE_RSTclear logo0, but occurs
TEST_RSTandE_RSTwill notLBORclear logo0, this flag can only be cleared after reading0.
5.1.2.13. ChipID
Address:1BH
ChipID
Bit23
Read:
Write:
Reset:
twenty two
twenty one
20
19
18
17
Bit16
Code23
Code22
Code21
Code20
Code19
Code18
Code17
Code16
0
1
1
1
0
0
0
0
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Read:
Write:
Reset:
Read:
Write:
Reset:
Bit15
14
13
12
11
10
9
Bit8
Code15
Code14
Code13
Code12
Code11
Code10
Code9
Code8
0
1
0
1
0
0
1
1
Bit7
6
5
4
3
2
1
Bit0
Code7
Code6
Code5
Code4
Code3
Code2
Code1
Code0
1
0
1
1
0
0
0
0
20
19
18
17
Bit16
Notice:
The default value of the register isHEXdata:7053B0
5.1.2.14. DeviceID
Address:1CH
DeviceID
Bit23
Read:
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
twenty two
twenty one
Code23
Code22
Code21
Code20
Code19
Code18
Code17
Code16
0
1
1
1
0
0
0
0
Bit15
14
13
12
11
10
9
Bit8
Code15
Code14
Code13
Code12
Code11
Code10
Code9
Code8
0
1
0
1
0
0
1
1
Bit7
6
5
4
3
2
1
Bit0
Code7
Code6
Code5
Code4
Code3
Code2
Code1
Code0
0
0
0
0
0
1
0
0
Notice:
The default value of the register is705304
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5.2. Calibration parameter register
5.2.1.Calibration parameter register list
surface5-2
address
Calibration parameter register list: (Read/Write)
byte
name
reset value
30H
EMUIE
0000
2(15bit)
EMUInterrupt enable register
31H
EMUIF
8000
2(16bit)
EMUInterrupt flag register
32H
WPREG
00
1(8bit)
write protect register
33H
SRSTREG
00
1(8bit)
Software reset register
40H
EMUCFG
0000
2(15bit)
EMUconfiguration register
41H
FreqCFG
0088
2(9bit)
Clock/Update Frequency Configuration Register
42H
ModuleEn
007E
2(14bit)
EMUModule enable register
43H
ANAEN
0003
1(7bit)
ADCswitch register
45H
IOCFG
0000
2(10bit)
IOOutput configuration register
50H
GP1
0000
2(16bit)
aisle1active power correction
51H
GQ1
0000
2(16bit)
aisle1reactive power correction
52H
GS1
0000
2(16bit)
aisle1Apparent power correction of
54H
GP2
0000
2(16bit)
aisle2active power correction
55H
GQ2
0000
2(16bit)
aisle2reactive power correction
56H
GS2
0000
2(16bit)
aisle2Apparent power correction of
58H
QPhsCal
FF00
2(16bit)
Reactive power phase compensation
59H
ADCCON
0000
2(12bit)
ADCChannel gain selection
5BH
I2Gain
0000
2(16bit)
current channel2gain compensation
5CH
I1Off
0000
2(16bit)
current channel1offset correction
5DH
I2Off
0000
2(16bit)
current channel2offset correction
5EH
UOff
0000
2(16bit)
Offset Correction for Voltage Channels
5FH
PQStart
0040
2(16bit)
Starting power setting
61H
HFConst
0040
2(15bit)
Output pulse frequency setting
62H
CHK
0010
1(8bit)
Power theft threshold setting
63H
IPTAMP
0020
2(16bit)
Electricity theft detection current threshold
(ECADR)
Function description
length
44H
53H
57H
5AH
60H
64H
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65H
P1OFFSETH
00
1(8bit)
aisle1Active power offset correction parameter high8bit, and
P1OFFSETLcomposed of16bitcomplement
66H
P2OFFSETH
00
1(8bit)
aisle2Active power offset correction parameter high8bit, and
P2OFFSETLcomposed of16bitcomplement
67H
Q1OFFSETH
00
1(8bit)
aisle1Reactive power offset correction parameter is high8bit, and
Q1OFFSETLcomposed of16bitcomplement
68H
Q2OFFSETH
00
1(8bit)
aisle2Reactive power offset correction parameter is high8bit, and
Q2OFFSETLcomposed of16bitcomplement
69H
I1RMSOFFSET
0000
2(16bit)
aisle1RMS compensation register, for16bitunsigned number
6AH
I2RMSOFFSET
0000
2(16bit)
aisle2RMS compensation register, for16bitunsigned number
6CH
ZCrossCurrent
0004
2(16bit)
Current zero-crossing threshold setting register
6DH
GPhs1
0000
2(16bit)
aisle1phase correction (PQWay)
6EH
GPhs2
0000
2(16bit)
aisle2phase correction (PQWay)
6FH
PFCnt
0000
2(16bit)
Fast active pulse counting
70H
QFCnt
0000
2(16bit)
Fast reactive pulse counting
71H
SFCnt
0000
2(16bit)
Fast apparent pulse counting
72H
ANACON
0000
2(16bit)
Analog control register
73H
SUMCHECKL
0000
2(16bit)
Checksum low16Bit, written by user, enables comparison function
6BH
Afterwards, the chip comparison gives the flag
74H
SUMCHECKH
00
1(8bit)
check sum high8Bit, written by user, enables comparison function
Afterwards, the chip comparison gives the flag
75H
MODECFG
00
1(8bit)
Mode configuration register
76H
P1OFFSETL
00
1(8bit)
aisle1Active power offset correction parameter is low8bit, and
P1OFFSETHcomposition16bitcomplement
77H
P2OFFSETL
00
1(8bit)
aisle2Active power offset correction parameter is low8bit, and
P2OFFSETHcomposition16bitcomplement
78H
Q1OFFSETL
00
1(8bit)
aisle1Reactive power offset correction parameter is low8bit, and
Q1OFFSETHcomposition16bitcomplement
79H
Q2OFFSETL
00
1(8bit)
aisle2Reactive power offset correction parameter is low8bit, and
Q2OFFSETHcomposition16bitcomplement
7AH
UPeakLvl
0000
2(16bit)
UPEAKthreshold register,16bit unsigned number, andADC high-order
alignment of absolute values
7BH
USagLvl
0000
2(16bit)
USAGthreshold register,16bit unsigned number, andADC high-order
alignment of absolute values
7CH
UCycLen
0000
2(16bit)
PEAK SAGDetection cycle setting register,16bit
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5.2.2.Calibration parameter register description
5.2.2.1.Interrupt enable register (EMUIE)
Address:30H
EMU Interrupt Enable Register (EMUIE)
Bit15
Read:
Write:
0
Reset:
Read:
Write:
14
13
12
11
CZCROS1_IE
CZCROS2_IE
USAGIE
0
0
0
0
PRms
UpdatesIE
10
9
Bit8
PEOFIE
QEOFIE
SEOFIE
0
0
0
Bit7
6
5
4
3
2
1
Bit0
UPEAKIE
TmpIE
PFIE
QFIE
SFIE
SPLIE
ZXIE
SPIWrongIE
0
0
0
0
0
0
0
0
Reset:
Bit name
describe
CZCROS2_IE
current channel2Positive zero-crossing interrupt enable (0:prohibit
1:Enable)
CZCROS1_IE
current channel1Positive zero-crossing interrupt enable (0:prohibit
1:Enable)
USAGIE
voltage channel signalSAGinterrupt enable (0:prohibit
PRms_UpdatesIE
Power register, rms register update interrupt enable (0:prohibit
PEOFIE
Interrupt enable when active energy register overflows (0:prohibit
1:Enable)
QEOFIE
Interrupt enable when reactive energy register overflows (0:prohibit
1:Enable)
SEOFIE
Interrupt enable on apparent energy register overflow (0:prohibit
1:Enable)
UPEAKIE
voltage channel signalPEAKinterrupt enable (0:prohibit
TmpIE
Power theft interrupt enable (0:prohibit1:Enable)
PFIE
PFInterrupt enable when pulsing (0:prohibit
1:Enable)
QFIE
QFInterrupt enable when pulsing (0:prohibit
1:Enable)
SFIE
SFInterrupt enable when pulsing (0:prohibit
1:Enable)
SPLIE
Interrupt enable when waveform register is updated (0:prohibit
ZXIE
Interrupt enable when voltage occurs in user-specified zero-crossing mode (0:prohibit
SPIWrongIE
SPICommunication error interrupt enable
1:Enable)
1:Enable)
1:Enable)
1:Enable)
1:Enable)
5.2.2.2.Interrupt Flag Register (EMUIF)
Address:31H
EMU Interrupt Flag Register (EMUIF)
Read:
Write:
Reset:
Bit15
14
13
12
RSTIF
CZCROS1_IF
CZCROS2_IF
USAGIF
0
0
0
0
11
PRms
UpdatesIF
0
10
9
Bit8
PEOFIF
QEOFIF
SEOFIF
0
0
0
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Bit7
6
5
4
3
2
1
Bit0
Read:
UPEAKIF
TmpIF
PFIF
QFIF
SFIF
SPLIF
ZXIF
SPIWrongIF
Write:
X
X
X
X
X
X
X
X
Reset:
0
0
0
0
0
0
0
0
Bit name
describe
RSTIF
When the chip is reset, this flag is set and cleared after reading.0
CZCROS2_IF
current channel2Positive zero-crossing interrupt flag, cleared after reading0
CZCROS1_IF
current channel1Positive zero-crossing interrupt flag, cleared after reading0
USAGIF
The voltage channel signal is lower than the set threshold interrupt flag. It is cleared after reading.0
PRms_UpdatesIE
Power register, effective value register update interrupt flag, cleared after reading0
PEOFIF
When the active energy register overflows, this flag is set and cleared after reading.0
QEOFIF
When the reactive energy register overflows, this flag is set and cleared after reading.0
SEOFIF
When the apparent energy register overflows, this flag is set and cleared after reading.0
UPEAKIF
The voltage channel signal is higher than the set threshold interrupt flag. It is cleared after reading.0
TmpIF
When power theft occurs, this flag is set and cleared after reading.0
PFIF
PFWhen a pulse is sent, this flag is set and cleared after reading.0
QFIF
QFWhen a pulse is sent, this flag is set and cleared after reading.0
SFIF
SFWhen a pulse is sent, this flag is set and cleared after reading.0
SPLIF
When the waveform register is updated, this flag is set and cleared after reading.0
ZXIF
When the voltage occurs in the user-specified zero-crossing mode, this flag is set and cleared after reading.0
SPIWrongIF
SPICommunication error interrupt flag signal, cleared after reading0
5.2.2.3.Write Protect Register (WPCFG)
Written protect Register (WPCFG)
Read:
Write:
Reset:
Address:32H
Bit7
6
5
4
3
2
1
Bit0
WPCFG7*
WPCFG6
WPCFG5
WPCFG4
WPCFG3
WPCFG2
WPCFG1
WPCFG0
0
0
0
0
0
0
0
0
Notice:
WPCFG = 0xA6: Indicates that write protection is on and can only be operated50Harrive7CHThe calibration parameter register is inoperable40H
arrive45HCalibration parameter register.
WPCFG = 0xBC: Indicates that write protection is on and can only be operated40Harrive45HThe calibration parameter register is inoperable50H
arrive7CHCalibration parameter register.
WPCFG =Other values: indicates that the write protection is turned off, and the operation of the calibration parameter register is invalid. After the
write protection is turned on, as long as it does not changeWPCFGregister value, then the write protection is always valid.
5.2.2.4.Software Reset Register (SRSTREG)
Soft reset Register (SRSTREG)
Address:33H
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Read:
Write:
Bit7
6
5
4
3
2
1
Bit0
SRST7
SRST 6
SRST 5
SRST 4
SRST 3
SRST 2
SRST 1
SRST 0
0
0
0
0
0
0
0
0
Reset:
Notice:
SRSTREGRegister if written0x55will cause the chip to reset. After reset, this register is cleared.0.
5.2.2.5.EMUconfiguration register (EMUCFG)
Address:40H
EMUCFG
Bit15
14
Read:
Write:
Write:
12
11
10
9
Bit8
EnergyClr
QMOD1
QMOD0
PMOD1
PMOD0
QSSelect
0
0
0
0
0
0
0
0
Bit7
6
5
4
3
2
1
Bit0
Zxd1
Zxd0
FLTON
CHNSEL*
CIADD*
TmpSel
0
0
0
0
0
0
Reset:
Read:
13
Reset:
0
0
Bit name
describe
EnergyClr
Set whether the energy register is cleared after reading0(0: Unclear after reading0;1: Clear after reading0)
QMOD[1…0]
Reactive energy registerEnergyQAccumulation mode selection, detailed configuration is shown in the following table
PMOD[1…0]
Active energy registerEnergyQAccumulation mode selection, detailed configuration is shown in the following table
QSSelect
Reactive energy/apparent energy output selection (0：Reactive energy output1: Apparent electric energy output)
Zxd1
Voltage interrupt zero-crossing selection, detailed configuration is shown in the table below
Zxd0
Voltage interrupt zero-crossing selection, detailed configuration is shown in the table below
FLTON
Automatic anti-theft module switch (0: Automatic anti-electricity tampering shutdown1: Automatic anti-theft of electricity is on)
CHNSEL
Select channel metering (0:Select channel1Measurement1:Select channel2measurement) , see the table below for details
CIADD
Single-phase three-wire accumulation mode selection (0:Single channel mode1: Current summation mode)
TmpSel
Anti-theft power head selection (0: Select the effective current value to prevent electricity theft.1: Select active power to prevent electricity theft)
, see the table below for details
Notice:
In the current addition mode, each channel uses its own calibration parameter data. The power accumulation mode is fixed to the
absolute value accumulation mode in the current addition mode. existFLTON=1when, that is, when the automatic anti-theft module is turned
on,CIADDand CHNSELwill lose its meaning. Although it can be read and written, it is invalid; onlyFLTON=0hourCIADDandCHNSEL Can read
and write effectively.
QMOD1
QMOD0
Reactive power accumulation mode, that isQFCntThe accumulation mode of
0
0
When calculating energy, the power is accumulated according to the algebraic sum method (default)
0
1
When calculating energy, only positive power is accumulated, and negative power is not accumulated.
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1
0
When calculating energy, the power is accumulated according to the absolute value method.
1
1
When calculating energy, the power is accumulated as an algebraic sum
PMOD1
PMOD0
Active power accumulation mode, that isPFCntThe accumulation mode of
0
0
When calculating energy, the power is accumulated according to the algebraic sum method (default)
0
1
When calculating energy, only positive power is accumulated, and negative power is not accumulated.
1
0
When calculating energy, the power is accumulated according to the absolute value method.
1
1
When calculating energy, the power is accumulated as an algebraic sum
ZXD1
ZXD0
0
0
A positive zero-crossing interrupt is generated whenZXCFG=1When , the pin outputs a positive zero-crossing waveform (default)
0
1
Negative zero-crossing interrupt is generated whenZXCFG=1When, the pin outputs a negative zero-crossing waveform
1
X
A bidirectional zero-crossing interrupt is generated whenZXCFG=1When, the pin outputs a bidirectional zero-crossing waveform
Voltage zero-crossing output selection, voltage zero-crossing interrupt selection
input signal
output signal
FLTON
CIADD
CHNSEL
Chanelstatus
Energy accumulation
1
X
X
Indicates automatic power theft prevention
according toChanelstatusto decide to adopt
Channel selection result
Which power channel participates in measurement?
0
Select channel1Participation
0
0
0
Measurement (default)
0
0
1
1
Select channel2Participation measurement
0
1
x
0
Single-phase three-wire mode (absolute value accumulation)
5.2.2.6.Clock configuration register (FreqCFG)
Address:41H
FreqCFG
14
Bit15
13
12
11
10
9
Read:
CFP1
Write:
Reset:
Read:
Write:
Reset:
Bit8
0
0
0
0
0
Bit7
6
5
4
3
CFP0
PRFCFG1
PRFCFG0
Emuclk_ctrl1
1
0
0
0
0
0
2
1
Bit0
Emuclk_ctrl0
SPL2
SPL1
SPL0
1
0
0
0
Bit name
describe
SPL[2…0]
ADCWaveform register sampling rate selection, see the table below for details
Emuclk_Ctrl[1..0]
EMUClock frequency selection bit, see the table below for details
CFP[1:.0]
Pulse width adjustment bit, see the table below for details
0
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PRFCFG[1…0]
Valid value update speed selection, detailed configuration is shown in the table below
SPL2
SPL1
SPL0
Waveform sampling frequency (EMUClock frequency1MHz)
0
0
0
0.976k Hz (femu/1024)(default)
0
0
1
1.953k Hz (femu/512)
0
1
0
3.906k Hz (femu/256)
0
1
1
7.812k Hz (femu/128)
1
x
x
15.62kHz (femu/64)
Emuclk_Ctrl1
Emuclk_Ctrl0
EMUClock frequency
EMUClock frequency
(The system clock is6MHz)
(The system clock is5.5296MHz)
0
0
2MHz
1.8MHz
0
1
1MHz(default)
921KHz
1
X
1MHz
921KHz
PRFCFG1
PRFCFG0
Valid value update speed (EMUClock frequency1MHz)
0
0
3.8Hz(default)
0
1
7.6Hz
1
0
15.2Hz
1
1
3.8Hz
CFPPulse width selection:EMUThe clock frequency is selected as2MHzwhen
CFP[1:0]
00
01
10
11
pulse width
90ms
90/2=45ms
90/4=22.5ms
90/8=11.25ms
CFPPulse width selection:EMUThe clock frequency is selected as1MHzwhen
CFP[1:0]
00
01 (default)
10
11
pulse width
180ms
180/2=90ms
180/4=45ms
180/8=22.5ms
5.2.2.7.Mode Control Register (ModuleEn)
Address:42H
ModuleEn
Bit15
14
13
Read:
11
X
Write:
Reset:
12
0
Bit7
Read:
Write:
0
0
0
10
9
Bit8
Rosi_i2_en
Rosi_i1_en
WDTEN
0
0
0
0
6
5
4
3
2
1
SRun
QRun
PRun
HPFONU
HPFONI2
HPFONI1
Bit0
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Reset:
0
1
1
1
1
1
1
0
Bit name
describe
Rosi_i2_en
Enable current channel2Support Rogowski coil (0:closureRosi
1:EnableRosi)
Rosi_i1_en
Enable current channel1Support Rogowski coil (0:closureRosi
1:EnableRosi)
WDTEN
whenSPITurning on this function when it is always pulled low can achieveSPI_CLKThe signal self-synchronizes when the user300ms No operation
SPIinterface,SPIThe module automatically returns to the reset state (0: This function is disabled and enabled)
SRun
Apparent energy accumulation enabled (0:Stop metering
1: Allow metering)
QRun
Reactive energy accumulation enable (0:Stop metering
1: Allow metering)
PRun
Active energy accumulation enable (0:Stop metering
1: Allow metering)
HPFONU
Voltage Channel High Pass Filter Switch (0:closure
HPFONI2
current channel2High pass filter switch (0:closure
1:open)
HPFONI1
voltage channel1High pass filter switch (0:closure
1:open)
1: This function
1:open)
5.2.2.8. ADCswitch register (ANAEN)
Analog Enable Register (ANAEN)
Bit7
Address:43H
6
5
4
3
Read:
Write:
Reset:
0
0
0
0
0
2
1
Bit0
Adc_i2on
Adc_i1on
Adc_uon
0
1
1
Bit name
describe
Adc_i2on
current channelI2ofADCswitch signal (0:closure
1:Open)
Adc_i1on
current channelI1ofADCswitch signal (0:closure
1:Open)
Adc_uon
voltage channelUofADCswitch signal (0:closure
1:Open)
5.2.2.9.Output pin configuration register (IOCFG)
Address:45H
IOCFG
Bit15
14
13
12
11
10
9
Bit8
0
0
0
0
0
0
0
0
Read:
Write:
Reset:
Read:
Write:
Reset:
Bit7
6
POS
IRQCFG1
0
0
5
4
3
2
1
Bit0
IRQCFG0
0
0
0
0
0
0
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Bit name
describe
POS
0:PF/QF/SFActive for high level1:PF/QF/SFis active low
IRQCFG[1:0]
Keep the default value,HT7017noneIRQOutput function
5.2.2.10.aisle1Active power correction (GP1)
Active Power Gain 1 Register (GP1)
Read:
Write:
Reset:
Address:50H
Bit15
14
13
12…3
2
1
Bit0
GP1_15
GP1_14
GP1_13
GP1_12…GP1_3
GP1_2
GP1_1
GP1_0
0
0
0
0
0
0
0
Notice:
This register is16There are signed numbers, and the highest bit is the sign bit. The power factor is1In the
case of , the error measured by the user during the calibration process is:Err% Pgain = -Err% /(1+Err%)
ifPgainis a positive number, thenGP1The written value is:Pgain *32768 ifPgainis a
negative number, thenGP1The written value is:65536+Pgain *32768
5.2.2.11.aisle1Reactive power correction (GQ1)
Reactive Power Gain Register (GQ1)
Read:
Write:
Reset:
Address:51H
Bit15
14
13
12…3
2
1
Bit0
GQ1_15
GQ1_14
GQ1_13
GQ1_12…GQ1_3
GQ1_2
GQ1_1
GQ1_0
0
0
0
0
0
0
0
Notice:
16There are signed numbers, and the highest bit is the sign bit.
During the user calibration process, generallyGQ1Write value withGP1The calculated written value is the same.
5.2.2.12.aisle1Apparent power correction (GS1)
Apparent Power Gain 1 Register (GS1)
Read:
Write:
Reset:
Address:52H
Bit15
14
13
12…3
2
1
Bit0
GS1_15
GS1_14
GS1_13
GS1_12…GS1_3
GS1_2
GS1_1
GS1_0
0
0
0
0
0
0
0
Notice:
16There are signed numbers, and the highest bit is the sign bit.
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During the user calibration process,GS1Write value withGP1The calculated written value is the same.
5.2.2.13.aisle2Active power correction (GP2)
Active Power Gain 2 Register (GP2)
Read:
Write:
Reset:
Address:54H
Bit15
14
13
12…3
2
1
Bit0
GP2_15
GP2_14
GP2_13
GP2_12…GP2_3
GP2_2
GP2_1
GP2_0
0
0
0
0
0
0
0
Notice:
andGP1The calculation formula is the same.
5.2.2.14.aisle2Reactive power correction (GQ2)
Reactive Power Gain 2 Register (GQ2)
Read:
Write:
Reset:
Address:55H
Bit15
14
13
12…3
2
1
Bit0
GQ2_15
GQ2_14
GQ2_13
GQ2_12…GQ2_3
GQ2_2
GQ2_1
GQ2_0
0
0
0
0
0
0
0
Notice:
During the calibration process, users generallyGP2The written values are the same.
5.2.2.15.aisle2Apparent power correction (GS2)
Apparent Power Gain 2 Register (GS2)
Read:
Write:
Reset:
Address:56H
Bit15
14
13
12…3
2
1
Bit0
GS2_15
GS2_14
GS2_13
GS2_12…GS2_3
GS2_2
GS2_1
GS2_0
0
0
0
0
0
0
0
Notice:
During the calibration process, users generallyGP2The written values are the same.
5.2.2.16.Reactive phase correction (QPhsCal)
Address:58H
QPhsCal
Read:
Write:
Bit15
14
13
12…3
2
1
Bit0
QPC15
QPC14
QPC13
QPC12….QPC3
QPC2
QPC1
QPC0
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Reset:
1
1
1
0
0
0
0
Notice:
The reactive power phase compensation register also adopts two's complement form, and the highest bit is the sign bit. The
default value of this registerFF00H.
The default value corresponds tofemu=1MHzsituation at the time,50HzNo correction is required at the signal frequency; when the signal is at other frequencies, it needs to be
corrected according to the following formula:
No use0.5L,existU,IThe included angle is30Calibration is performed when the powerQThe error value is:Err%
QPhasCalThe calculation formula is:
Result = Err%*32768/1.732-256 if
Resultis a positive number
ifResultis a negative number
QphsCal = Result;
QphsCal = 65536+Result;
Note:
1, when the system clock is changed to5.5296MHzIn order to obtain accurate reactive power accuracy, this register needs to be calibrated. 2, this
register corrects the internal phase shift filter, and the calibration results are common to both measurement channels.
5.2.2.17. ADCchannel gain (ADCCON)
Address:59H
ADC Channel Gain Register (ADCCON)
14
Bit15
Read:
Write:
13
12
11
10
9
Bit8
PGA242
PGA241
DGI3
DGI2
DGI1
DGI0
0
0
0
0
0
0
0
0
Bit7
6
5
4
3
2
1
Bit0
DGU1
DGU0
PGA3
PGA2
PGA1
PGA0
UPGA1
UPGA0
Reset:
0
0
0
0
0
0
0
0
PGA242
PGA3
PGA2
I2Gain
PGA241
PGA1
PGA0
I1Gain
UPGA1
UPGA0
UGAIN
0
0
0
PGA=1
0
0
0
PGA=1
0
0
PGA=1
0
0
1
PGA=4
0
0
1
PGA=4
0
1
PGA=2
0
1
0
PGA=8
0
1
0
PGA=8
1
0
PGA=4
0
1
1
PGA=16
0
1
1
PGA=16
1
1
PGA=4
1
X
X
PGA=24
1
X
X
PGA=24
Reset:
Read:
Write:
Notice:
hereI1Gain,I2Gain,UGainrespectively refer toADCAnalog section current channels1gain, current channel2 gain,
Voltage channel gain.
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DGU 1
DGU 0
voltage channel
DGI1
DGI0
current channel1
DGI3
DGI2
current channel2
0
0
DG=1
0
0
DG=1
0
0
DG=1
0
1
DG=2
0
1
DG=2
0
1
DG=2
1
0
DG=4
1
0
DG=4
1
0
DG=4
1
1
DG=8
1
1
DG=8
1
1
DG=8
Notice:
Digital gain is amplified by shiftingADCIt is realized by the digital signal after1/2/4/8. Digital gain can be used to
double small signals, and the effective value is doubled as well.
5.2.2.18.current channel2gain setting (I2Gain)
Address:5BH
Current 2 Gain Register (I2Gain)
Read:
Write:
Reset:
Bit15
14
13
12…3
2
1
Bit0
I2G15
I2G14
I2G13
I2G12…I2G3
I2G2
I2G1
I2G0
0
0
0
0
0
0
0
Notice:
aisle2The current gain register adopts two's complement form, and the highest bit is the sign bit. See the calibration process for definition. When the same
external current channel is input, the current effective value output of the two channels is consistent, mainly to adjust the two currents introduced due to the different
external sensors of the two current channels.ADCThe effective value difference of the channels.
Calculated as follows(i1RmsandI2RmsThey are the current channels when the inputs are the same.1The rms register value and current channel
2
valid value register value):
Gain=(I1Rms/I2Rms)-1;
likeGain>0,I2Gain=Gain*(2 1̂5); like
Gain<0,I2Gain=2 1̂6+Gain*(2 1̂5);
5.2.2.19.current channel1DC offset correction register (I1Off)
Address:5CH
Current 1 Offset Register (I1Off)
Read:
Write:
Reset:
Bit15
14
13
12…3
2
1
Bit0
I1OS15
I1OS14
I1OS13
I1OS12…I1OS3
I1OS2
I1OS1
I1OS0
0
0
0
0
0
0
0
Notice:
When measuring DC signals, turn off the high pass first. When the input channel signal is0When, read the register several times in succession00H
The values of are averaged and then inverted to getI1OffThe value of the register, the user will store this value after getting it, and then restore the
previously stored value after powering on again.I1OffThe value is rewritten to the register.
The smallest unit of this register is the same asADCOutput16The smallest unit of bit data is consistent. The main purpose of this
register is to turn off the high pass inside the chip when the user expects to test DC signals.I1/I2/Umust
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Qualcomm must be turned off together, otherwise phase errors will be introduced. Correct the external input signal through this register to0timelyADC
Zero drift. Generally speaking, users do not need to configure this register when testing AC signals. Note:I1OffandI2OffCorrection cannot be performed
simultaneously.
5.2.2.20.current channel2DC Bias Correction Register (I2Off)
Address:5DH
Current 2 Offset Register (I2Off)
Read:
Write:
Reset:
Bit15
14
13
12…3
2
1
Bit0
I2OS15
I2OS14
I2OS13
I2OS12…I2OS3
I2OS2
I2OS1
I2OS0
0
0
0
0
0
0
0
Notice:
When measuring DC signals, turn off the high pass first. When the input channel signal is0When, read the register several times in succession01H
The values of are averaged and then inverted to getI2OffThe value of the register, the user will store this value after getting it, and later store the
previously stored value after powering on again.I2OffThe value is rewritten to the register.
The smallest unit of this register is the same asADCOutput16The smallest unit of bit data is consistent. Note:I1Off
andI2OffCorrection cannot be performed simultaneously.
5.2.2.21.Voltage Channel DC Bias Correction Register (UOff)
Address:5EH
Voltage Offset Register (UOff)
Read:
Write:
Reset:
Bit15
14
13
12…3
2
1
Bit0
UOS15
UOS14
UOS13
UOS12…UOS3
UOS2
UOS1
UOS0
0
0
0
0
0
0
0
Notice:
When measuring DC signals, turn off the high pass first. When the input channel signal is0When, read the register several times in succession02H
The values of are averaged and then inverted to getUOffThe value of the register, the user will store this value after getting it, and later store the
previously stored value after powering on again.UOffThe value is rewritten to the register.
Its smallest unit is the same asADCOutput16The smallest unit of bit data is consistent. Channel DC offset correction is only used after the highpass link is turned off.I1/I2/UQualpass must be turned off together, otherwise phase errors will be introduced.
5.2.2.22.Latent and activation (PQStart)
Address:5FH
PQStart
Read:
Write:
Reset:
Bit15
14
13
12…7
6
5…2
1
Bit0
PQS15
PQS 14
PQS 13
PQS 12…PQS 7
PQS 6
PQS 5…PQS 2
PQS 1
PQS 0
0
0
0
0
1
0
0
0
Notice:
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PQStartyes16bit unsigned number, when compared, treat it as low16Bit ANDP/Q (PowerP 0x0AH / PowerQ 0x0BH,
both24bitThe absolute value of signed number) is compared to make a starting judgment.
|P|less thanPQStarthour,PFNo pulse is output. At the same time,REVPReverse flag clear0. |Q|
less thanPQStarthour,QFNo pulse is output. At the same time,REVQReverse flag clear0.
(|P|/|Q|both are smaller thanPQStart)hour,SFNo pulse is output.
Application method:
1, after the calibration is completed, enterIb,Un.
2,read outPowerPThe value is24bircomplementx1, take its original code value asx2.
3, assuming writingPQStartThe value isY, if required0.4%IbThe meter can be started if:
Y=x2*0.2%
5.2.2.23.Pulse frequency setting register (HFConst)
Address:61H
HFConst
14
13
12…7
6
5…2
1
Bit0
HFC14
HFC13
HFC12…HFC7
HFC6
HFC5….HFC2
HFC1
HFC0
0
0
0
1
0
0
0
Bit15
Read:
0
Write:
X
Reset:
0
Notice:
HFConstyes15bit unsigned number, when compared, treat it as low15Bit and Fast Pulse Count Register 0x6FH~0x71HThe
absolute value of the register value is compared, if it is greater than or equal toHFConstvalue, then there will be a corresponding
PF/QF/SFPulse output.
HFConstThe default value is0x0040.
5.2.2.24.Inter-channel power theft threshold |P|orIRMSThe domain value setting (htK)
Address:62H
Check Register (Chk)
Read:
Write:
Bit7
6
5
4
3
2
1
Bit0
CHK7
CHK6
CHK5
CHK4
CHK3
CHK2
CHK1
CHK0
0
0
0
1
0
0
0
0
Reset:
Notice:
The power theft threshold current register adopts two's complement form and represents the range (0,+1).
ICHK=ICK7*2 (̂-1)+ICK6*2 (̂-2)+ICK5*2 (̂-3)+…+ICK1*2 (̂-7)+ICK0*2 (̂-8) when |I2Rms-I1Rms|/I1Rmsor |
PowerP2-PowerP1|/PowerP1more than theICHKWhen, set the power stealing flag. if and only ifCheck
Registerone ofBitfor1When , the corresponding thresholds are as follows:
Bit7
Bit6
Bit5
Bit4
Bit3
0.5
0.25
0.125
0.0625
0.03125
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Bit2
Bit1
Bit0
0.015625
0.007813
0.003906
For example:Check Register=0x1AWhen , the power stealing threshold is0.0625+0.03125+0.007813=10.1563% The default is:0.0625That is to say6.25%. After
turning on automatic electricity theft prevention, when the current effective value is selected as the source of electricity theft prevention, the current1and current2
The difference between the two (|I2Rms-I1Rms|/I1Rms) exceeds the electricity theft threshold current value, a larger current value is automatically selected to
participate in power measurement, and at the same time TAMP=1. If the current2greater than current1, then the flag bitI2GTI1set to1, otherwise the flag bitI2GTI1for0.
When selecting power as the source to prevent electricity theft, the powerPowerP1and powerPowerP2The difference between the two (|PowerP2PowerP1|/PowerP1) exceeds the power theft value, a larger power value is automatically selected to participate in power measurement, and at the same
time TAMP=1.
5.2.2.25.Power theft detection threshold |P|orIRMSThe domain value setting (IPTAMP)
Address:63H
IPTAMP
14
13
12…3
2
1
Bit0
IPTAMP14
IPTAMP13
IPTAMP12…IPTAMP3
IPTAMP2
IPTAMP1
IPTAMP0
0
0
0
0
0
0
Bit15
Read:
IPTAMP15
Write:
X
Reset:
0
Notice:
The default value of this register is0x0020.
The format is the same as the current effective value register or power register,IPTAMP[15:0]is high16Bit current rms register or power
register.
Notice:IPtampthe highest positionbit15User write is invalid, consistent is0, the maximum value that a user can write is0x7FFF. When the automatic anti-electricity
theft processing module is turned on:
If you choose to use the current effective value as a judgment against electricity theft, when the channel1and2The current effective values
are lower thanIPTAMP, always select the channel1As a valid input,TAMP,I2PPXGTI1PandCHNSELAll are0.
If you choose to use powerPThe absolute value of is used as a judgment to prevent electricity theft. WhenPowerP1andPowerP2are lower
thanIPTamp, always select the channel1As a valid input,TAMP,I2PPXGTI1PandCHNSELAll are0.
5.2.2.26.The first channel small signal active power correction high bit (P1OFFSETH)
Power offset 1 High (P1OFFSETH)
Address:65H
Bit7
6
5
4
3
2
1
Bit0
P1OFFH7
P1OFFH6
P1OFFH5
P1OFFH4
P1OFFH3
P1OFFH2
P1OFFH1
P1OFFH0
0
0
0
0
0
0
0
0
Read:
Write:
Reset:
Notice:
Active power channel1The correction register is in two's complement form.
P1OFFSETHandtwenty fourbit registerPowerP1of low8Bit aligned.
(with internal operations32bit registerPowerP1'of
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bit[15:8]Alignment).
Note:P-offsetFor details on the calibration method, see "Recommended Calibration Process" Chapter5step.
5.2.2.27.Second channel small signal active power correction high bit (P2OFFSETH)
Power offset 2 High (P2OFFSETH)
Address:66H
Bit7
6
5
4
3
2
1
Bit0
P2OFFH7
P2OFFH6
P2OFFH5
P2OFFH4
P2OFFH3
P2OFFH2
P2OFFH1
P2OFFH0
0
0
0
0
0
0
0
0
Read:
Write:
Reset:
Notice:
Active power channel2The correction register is in two's complement form.
P2OFFSETHandtwenty fourbit registerPowerP2of low8bit-aligned (with internal operations32bit registerPowerP2'of
bit[15:8]Alignment).
Note:P-offsetFor details on the calibration method, see "Recommended Calibration Process" Chapter5step.
5.2.2.28.The first channel small signal reactive power correction high bit (Q1OFFSETH)
Reactive
Power
High
offset1
Address:67H
(Q1OFFSETH)
Read:
Write:
Bit7
6
5
4
3
2
1
Bit0
Q1OFFH7
Q1OFFH6
Q1OFFH5
Q1OFFH4
Q1OFFH3
Q1OFFH2
Q1OFFH1
Q1OFFH0
0
0
0
0
0
0
0
0
Reset:
Notice:
1, reactive power channel1The correction register is in two's complement form
2,Q1OFFSETHandtwenty fourbit registerPowerQ1of low8bit-aligned (with internal operations32bit registerPowerQ1'of
bit[15:8]Alignment).
3,Q-offsetThe verification method is the same asP-offsetThe correction method is the same, but the user needs to calculate it by observing the accuracy of reactive power.
5.2.2.29.Second channel small signal reactive power correction high bit (Q2OFFSETH)
Reactive
Power
High
offset2
Address:68H
(Q2OFFSETH)
Read:
Write:
Reset:
Bit7
6
5
4
3
2
1
Bit0
Q2OFFH7
Q2OFFH6
Q2OFFH5
Q2OFFH4
Q2OFFH3
Q2OFFH2
Q2OFFH1
Q2OFFH0
0
0
0
0
0
0
0
0
Notice:
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1, reactive power channel2The correction register is in two's complement form
2,Q2OFFSETHandtwenty fourbit registerPowerQ2of low8bit-aligned (with internal operations32bit registerPowerQ2'of
bit[15:8]Alignment).
3,Q-offsetThe verification method is the same asP-offsetThe correction method is the same, but the user needs to calculate it by observing the accuracy of reactive power.
5.2.2.30.current channel1RMS offset correction register (I1RMSOFFSET)
Address:69H
I1RMSOFFSET
Bi15
14
13
12…3
2
1
Bit0
Read:
I1RMS
I1RMS
I1RMS
I1RMS
I1RMS
I1RMS
I1RMS
Write:
OFFSET15
OFFSET14
OFFSET13
OFFSET12---I1RMSOFFSET3
OFFSET2
OFFSET1
OFFSET0
Reset:
0
0
0
0
0
0
0
Notice:
current channel1The RMS correction register takes the form of a binary unsigned number. The
calculation formula is:
When the input signal is0when reading multiple timesI1RMS, after taking the average, then calculate according to the formula
below. I1RMSOFFSET = (I1RMS 2̂)/ (2 1̂5) If the external noise is large, it will cause theI1RMSOFFSETexceeds the limit. At this
time, the user can only write software to remove excessive board-level noise. This register cannot completely eliminate this
zero-drift noise.
5.2.2.31.current channel2RMS Bias Correction Register (I2RMSOFFSET)
Address:6AH
I2RMSOFFSET
Bi15
14
13
12…3
2
1
Bit0
Read:
i2RMS
i2RMS
i2RMS
i2RMS
i2RMS
i2RMS
i2RMS
Write:
OFFSET15
OFFSET14
OFFSET13
OFFSET12---I2RMSOFFSET3
OFFSET2
OFFSET1
OFFSET0
Reset:
0
0
0
0
0
0
0
Notice:
current channel2The calculation formula of the effective value correction register in the form of binary
unsigned number is:
When the input signal is0when reading multiple timesi2RMS, after taking the average, then calculate according to the formula
below. I2RMSOFFSET = (I2RMS 2̂)/ (2 1̂5)
5.2.2.32.Current zero-crossing threshold setting register (ZCrossCurrent)
Address:6CH
ZCrossCurrent
Read:
Bit15
14
13
12…3
2
1
Bit0
ZC15
ZC154
ZC13
ZC12…ZC3
ZC2
ZC1
ZC0
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Write:
Reset:
0
0
0
0
0
0
0
Notice:
Current effective value andZCrossCurrentCompared.ZCrossCurrentcorrespondIRMSof low16BitBit15…bit0. Zero-crossing current threshold setting register. When
the effective current value is less than the current zero-crossing threshold setting register set by the user, the current positive zero-crossing signal will not be output, and
the internal output will always be0. At the same time, the angle register output of the corresponding channel is0, no angle calculation is performed.
5.2.2.33.PQmode phase correction register (GPhs1)
Address:6DH
Phase Calibration 1 Register (GPhs1)
Read:
Write:
Reset:
Bit15
14
13
12…3
2
1
Bit0
GPS1_15
GPS1_14
GPS1_13
GPS1_12…GPS1_3
GPS1_2
GPS1_1
GPS1_0
0
0
0
0
0
0
0
Notice:
PQThe formula for calculating phase correction is as follows:
The user passes thePGainregister corrects the output error to0Nearby adjust the signal input to
0.5L, at this time the observation error isErr% ifErris a negative number:
Gphs1 = -Err%*32768/1.732 ifErr
is a positive number:
Gphs1 = 65536 – Err%*32768/1.732
5.2.2.34.PQmode phase correction register (GPhs2)
Phase Calibration 2 Register (GPhs2)
Read:
Write:
Reset:
Address:6EH
Bit15
14
13
12…3
2
1
Bit0
GPS2_15
GPS2_14
GPS2_13
GPS2_12…GPS2_3
GPS2_2
GPS2_1
GPS2_0
0
0
0
0
0
0
0
andGphs1same.
5.2.2.35.Fast Pulse Counter (PFCNT,QFCNT,SFCNT)
Active Energy Counter Register (PFCNT)
Read:
Write:
Reset:
Address:6FH
Bit15
14
13
12…3
2
1
Bit0
PFC15
PFC14
PFC13
PFC12…PFC3
PFC2
PFC1
PFC0
0
0
0
0
0
0
0
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Address:70H
Reactive Energy Counter (QFCNT)
Read:
Write:
Reset:
Bit15
14
13
12…3
2
1
Bit0
QFC15
QFC14
QFC13
QFC12…QFC3
QFC2
QFC1
QFC0
0
0
0
0
0
0
0
Address:71H
Apparent Energy Counter (SFCNT)
Read:
Write:
Reset:
Bit15
14
13
12…3
2
1
Bit0
SFC15
SFC14
SFC13
SFC12…SFC3
SFC2
SFC1
SFC0
0
0
0
0
0
0
0
Notice:
In order to prevent the loss of power when powering on and off, when powering offMCUregisterPFCnt/QFCnt/SFCntThe value is read back
and saved, and then on the next power-upMCURewrite these values toPFCnt/QFCnt/SFCntGo in.
When the fast pulse count registerPFCnt/QFCnt/SFCntThe count value is greater than or equal toHFconstwhen, the correspondingPF/QF/SF There will
be pulse overflow, the energy register0x0DH~0x0FHThe value of the register will be added accordingly1.
5.2.2.36.Analog Control Register (ANACON)
Address:72H
Analog Control(ANACON)
Bit7
6
5
4
3
2
1
Bit0
AnaPara[7]
AnaPara[6]
AnaPara[5]
AnaPara[4]
AnaPara[3]
AnaPara[2]
AnaPara[1]
AnaPara[0]
0
0
1
1
0
0
0
1
Bit15
14
13
12
11
10
9
Bit8
Read:
ADC_CHOP
ADC_CHOP
Write:
_FRE1
_FRE0
C_VREF[2]
C_VREF[1]
C_VREF[0]
Reset:
0
0
0
0
0
2
1
Bit0
Scheck2
Scheck1
Scheck0
Read:
Write:
Reset:
This register is not included in the calibration table checksum register
Bit name
describe
ADC_CHOP_FRE[1:0]
ADC_CHOP_FRESelect, default is0
C_VREF[2:0]
tTcAdjustment, default is0
AnaPara[7:0]
Internal simulation parameters, default is31H
5.2.2.37.User calibration checksum register (SUMCHECKL)
SumChecksum Register (SumcheckL)
Read:
Address:73H
Bit15
14
13
Scheck15
Scheck14
Scheck13
12…3
Scheck12….. Scheck3
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Write:
0
Reset:
0
0
0
0
0
0
4…3
2
1
Bit0
Scheck2
Scheck1
Scheck0
0
0
0
This register is not included in the calibration table checksum register
The user writes the checksum register low16bit.
5.2.2.38.User calibration checksum register (SUMCHECKH)
SumChecksum Register (SumcheckH)
Read:
Address:74H
Bit7
6
5
Scheck7
Scheck6
Scheck5
0
0
0
Scheck4….. Scheck3
Write:
Reset:
0
This register is not included in the calibration table checksum register
The user writes the checksum register high8bit, this register is the same asSUMCHECKLform together24bitValue, after the user has calibrated the meter, write
the calibration parameter checksum. After the comparison function is enabled, each internal chipEMU clkCumulative updatesSUMCHECKWhen , compare the
two registers by yourself and give the corresponding interrupt flag.
5.2.2.39. MODEconfiguration register (MODECFG)
Address:75H
Mode Configure (MODECFG)
Read:
Write:
Reset:
Bit7
6
5
Test1
Test0
En_NewStatus
0
0
0
4
ADC
chopper
3
U chopper
0
2
EN_SumChe
0
ck
0
1
CHNFix
0
Bit0
IPTamp_S
el
0
Bit name
describe
Test[1:0]
Internal test bit, keep default value00;
En_NewStatus
EnableEMUSRhigh8in the middleNoPLD 1,2andNoQLD1,2Functions and anti-theft threshold settings =0, close function,
output0, the power theft threshold is given byTAMPSELDecide; =1, enable function, the power stealing threshold is
determined byIPTamp_SelDecide;
ADC chopper
set upADC chopperWhether to turn it on?0 enable adc chopper,1 disable adc chopper
U chopper
set upU chopperWhether to turn it on?0 enable U chopper,1 disable U chopper
EN_SumCheck
=0, turn off the calibration parameter verification and automatic comparison function;
=1, enable the calibration parameter verification and automatic comparison function;
CHNFix
It was decided to reduce both circuit channels toIPTAMPIn the following times, choose to fix the first current channel measurement
or not switch channels and maintain the previous channel measurement.
=0, select the fixed first current channel;
=1, do not switch and maintain the previous channel measurement;
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IPTamp_Sel
existEn_NewStatusfor1in the case of:
=0:IPTampThe register selects a valid value as the anti-tampering threshold.
=1:IPTampThe register selects the power as the anti-tampering threshold.
5.2.2.40.The first channel small signal active power correction low position (P1OFFSETL)
Power offset 1 Low (P1OFFSETL)
Address:76H
Bit7
6
5
4
3
2
1
Bit0
P1OFFL7
P1OFFL6
P1OFFL5
P1OFFL4
P1OFFL3
P1OFFL2
P1OFFL1
P1OFFL0
0
0
0
0
0
0
0
0
Read:
Write:
Reset:
Notice:
This register is related toP1OFFSETHcomposition16bitWorking together, its sign bit isP1OFFSETH(65H) the highest bit.
P1OFFSETLand internal operations32bit registerPowerP1'of low8Bit aligned.
5.2.2.41.The second channel small signal active power correction low position (P2OFFSETL)
Power offset 2 Low (P2OFFSETL)
Address:77H
Bit7
6
5
4
3
2
1
Bit0
P2OFFL7
P2OFFL6
P2OFFL5
P2OFFL4
P2OFFL3
P2OFFL2
P2OFFL1
P2OFFL0
0
0
0
0
0
0
0
0
Read:
Write:
Reset:
Notice:
This register is related toP2OFFSETHcomposition16bitWorking together, its sign bit isP2OFFSETH(66H) the highest bit.
P2OFFSETLand internal operations32bit registerPowerP2'of low8Bit aligned.
5.2.2.42.The first channel small signal reactive power correction low bit (Q1OFFSETL)
Address:78H
Reactive Power offset 1 Low
(Q1OFFSETL)
Read:
Write:
Reset:
Bit7
6
5
4
3
2
1
Bit0
Q1OFFL7
Q1OFFL6
Q1OFFL5
Q1OFFL4
Q1OFFL3
Q1OFFL2
Q1OFFL1
Q1OFFL0
0
0
0
0
0
0
0
0
Notice:
This register is related toQ1OFFSETHcomposition16bitWorking together, its sign bit isQ1OFFSETH(67H) the highest bit.
Q1OFFSETLand internal operations32bit registerPowerQ1'of low8Bit aligned.
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5.2.2.43.Second channel small signal reactive power correction low bit (Q2OFFSETL)
Address:79H
Reactive Power offset 2 Low
(Q2OFFSETL)
Read:
Write:
Reset:
Bit7
6
5
4
3
2
1
Bit0
Q1OFFL7
Q1OFFL6
Q1OFFL5
Q1OFFL4
Q1OFFL3
Q1OFFL2
Q1OFFL1
Q1OFFL0
0
0
0
0
0
0
0
0
Notice:
This register is related toQ2OFFSETHcomposition16bitWorking together, its sign bit isQ2OFFSETH(68H) the highest bit.
Q2OFFSETLand internal operations32bit registerPowerQ2'of low8Bit aligned.
5.2.2.44.VoltagePEAKThreshold setting register (UPeakLvl)
Reactive Power offset (UPeakLvl)
Read:
Write:
Address:7AH
Bit15
14
13
12….3
2
1
Bit0
UPeakLvl15
UPeakLvl14
UPeakLvl13
UPeakLvl12…. UPeakLvl3
UPeakLvl2
UPeakLvl1
UPeakLvl0
0
0
0
0
0
0
0
Reset:
Notice:
16Bit unsigned data, voltage channelPEAKthreshold setting register, withADCThe high bit of the absolute value is aligned. When the voltage channel
sampling data is higher than the set detection threshold, the corresponding bit is set.UPEAKIFFlag bit.
When level mode output is enabled, when the voltage channel sampling data is higher than the set detection threshold,IRQOutput low level or high
level (configurable)
.
5.2.2.45.VoltageSAGThreshold setting register (USagLvl)
Reactive Power offset (USagLvl)
Read:
Write:
Reset:
Address:7BH
Bit15
14
13
12….3
2
1
Bit0
USAG15
USAG14
USAG13
USAG12….USAG3
USAG2
USAG1
USAG0
0
0
0
0
0
0
0
Notice:
16Bit unsigned data, voltage channelSAGthreshold setting register, withADCThe absolute value of the high bit is aligned. When the voltage channel
sampling data is lower than the set detection threshold, the corresponding bit is set.USAGIFFlag bit.
When level mode output is enabled, when the voltage channel sampling data is lower than the set detection threshold,IRQOutput low level or high
level (configurable)
.
5.2.2.46.VoltageSAG PEAKDetection time (UCycLen)
Reactive Power offset (UCycLen)
Bit15
14
Address:7CH
13
12….3
2
1
Bit0
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Read:
UCyclength
UCyclength
UCyclength
Write:
15
14
13
Reset:
0
0
0
UCyclength 12…. UCyclength 3
UCyclengt
UCyclengt
UCyclengt
h2
h1
h0
0
0
0
0
Notice:
16bit unsigned number, used to setSAG /PEAKDetect the data length, that isSAGThe function detects the set data length and gives the
peak value.
1indivualLSBCorresponds to half a cycle.
6.Electrical Specifications
6.1.absolute maximum ratings
maximum limit
parameter
AVDDto AGND
- 0.3V~7V
DVDD to DGND
- 0.3V~7V
Analog Input PIN (VxP VxN)
- 3V~+3V
Reference Input PIN
- 0.3V~AVDD+0.3V
Digital input PIN
- 0.3V~AVDD+0.3V
Operating Temperature Range
- 40℃~85℃
Storage Temperature Range
- 65℃~150℃
Junction Temperature
150℃
ESD Protection to All Pins
+ - 6KV
6.2. Electrical characteristics
Measurement conditions:Vcc=AVcc=5V, system frequency6M, room temperature
parameter
minimum value
classic
type
maximum value
unit
Test Conditions
value
Electric energy measurement parameters
Active energy measurement error
0.1%
normal temperature5000:1scope
0.1%
normal temperature5000:1scope
Difference
Reactive energy measurement error
Difference
Voltage rms measurement
error
Current RMS measurement
error
0.1%
0.5%
1000:1
0.1%
0.5%
1000:1
5000:1
5000:1
ADCparameter
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+-800
maximum signal level
mV
Available to customers as +-700mvpeak
value
DC input impedance
250
kΩ
signal-to-noise ratio
75
dB
14
7
KHz
2.5
V
+-10
ppm
bandwidth(-3dB)
ADCOutput reference voltage
ADCSampling frequency2MHz
ADCSampling frequency1MHz
press
ADV Vreftemperature system
number
Power consumption data
EMUfrequency1M,
4
defaultADCConfiguration
3
4.5
mA
3roadADCopen all
mA
U,I1Open
DCparameter
Digital supply voltage
4.5
5
5.5
V
Analog supply voltage
4.5
5
5.5
V
5
8
mA
CFport output drive circuit
flow
range of working temperature
- 40
85
℃
Storage temperature range
- 65
150
℃
External pin parameters
High level input voltage
0.7Vcc
Apart fromRSTAll exceptPIN
0.8Vcc
RSTpin
0.2Vcc
low level input voltage
High level output voltage
0.9Vcc
PF,QF/SF
(Isource>4mA)
0.9Vcc
Other Pins
(Isource>1mA)
Low level output voltage
0.1Vcc
PF,QF/SF
(Isink>4mA)
0.1Vcc
Other Pins
(Isink>1mA)
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7.Calibration process
1． Before accuracy correction, the current channel needs to be2Gain correction (necessary for anti-electricity theft), if the user does not need the second
channel measurement, this step can be ignored.
When preventing electricity theft, it is necessary to compare the effective current values of the two channels. Therefore, under the same current input, the current channel1with
current channel2The register values should be equal.
through current channel2Gain correction registerI2GAIN, so that under the same input current, the values of the two registers are consistent.
Assuming that the rated current is also input, the current channel1The effective value register readsI1rms, current channel2The effective value
register readsi2rms,but
Gain=I1rms/I2rms - 1 ifGain>=0,
I2Gain=Gain*2 1̂5 ifGain<0,I2Gain=
Gain*2 1̂5+2 1̂6 for example:
Add current signals to both channels and read the current channels1valid value registerRMS_I1(06H),Read current channel2 The
valid value register data ofRMS_I2(07H), the result is as follows: RMS_I1: 0x03BA55
RMS_I2: 0x025A76
According to the formula:Gain=I1rms/I2rms – 1 = 0x03BA55/0x025A76 – 1 = 244309/154230 – 1 =
0.584 becauseGain>0,I2Gain = 0.584*2 1̂5 = 0x4AC2
useMCUpassSPIorUARTWill0x4AC2writeHT7017ofI2Gain(5BH)Register: Format:
SPI_UART_Write(Register address, write data) Actual:SPI_UART_Write(0x5B,0x4AC2) Read
current after writingI1RMS and currentI2Valid values, the two should be very close.
2.High-frequency pulse constant setting (the same batch of meters only needs the sameHFCONST)
passHFConstThe register adjusts the error accuracy of the user sample table to15%Within. There are two ways to calculate it.
Option One:
HFCONSTThe default value of the register is0x0040 The user observes the initial error of the
meter asErr%, then the error is adjusted to10Within: HFCONST = 0x0040 *(1+ Err%)
for example:
Meter constant (EC)Set as3200, the power factor is1,HFCONSTRegister is default value0x0040, the error displayed on the
observation standard table is52.8%.
According to the formula:HFCONST = 0x0040 *(1+ Err%) is
calculated as:HFCONST = 0x0040 * (1+52.8%) = 0x0061
useMCUpassSPIorUARTWill0x0061writeHT7017ofHFCONST(61H) Register: Format:
SPI_UART_Write(Register address, write data)
actual:SPI_UART_Write(0x61,0x0061), the display error of the standard table after writing should be within10%within
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Option II:
femu=1MHzhour
HFConst=6.24*Vu*Vi*10^10/(EC*Un*Ib)
vu: When the rated voltage is input, the voltage of the voltage channel (voltage on the pin×gain) Vi:
When the rated current is input, the voltage of the current channel (voltage on the pin×gain) Un:
Rated input voltage
Ib: Rated input current
EC: Meter constant
femuFor other values,HFConstJust change it proportionally.
for example:
Meter constant (EC)Set as3200, the power factor is1.
Un(rated voltage) is220V,Ib(rated current) is5A,vu(voltage of the voltage channel) is0.22V Vi(voltage
of the current channel) is1.75mV, internal current channel16times gain,Vi*16 = 28mV According to
the formula:HFConst=6.24*Vu*Vi*10 1̂0/(EC*Un*Ib)Calculated HFConst =6.24*0.22 *0.028*10 1̂0 /
(3200*220*5) = 0x006D
useMCUpassSPIorUARTWill0x006DwriteHT7017ofHFCONST(61H) Register: Format:
SPI_UART_Write(Register address, write data)
actual:SPI_UART_Write(0x61,0x006D), the display error of the standard table after writing should be within10%within
3.First channel active power, reactive power and apparent gain correction
Only when the rated input and power factor are1Calculated based on active work. Usually active power, reactive power and apparent gain are written in the same
value.
A known:
The reading error on the standard table isErr%
Calculation formula:
Pgain=
− err
1+err
ifPgain>=0,butGP1=INT[Pgain*215] otherwise
Pgain<0, butGP1=INT[216+Pgain*215]
for example:
Meter constant (EC)Set as3200, the power factor is1, after passing the first stepHFCONSTAfter adjustment, the error
read on the standard table is -2.18%
According to the formula:Pgain = -(-2.18%) / (1-2.18%) =
0.022 becausePgain >=0,butGP1 = 0.022*2 1̂5 = 0x02DA
useMCUpassSPIorUARTWill0x02DAwriteHT7017ofGP1(50H), GQ1(51H), GS1(52H)register:
Format:SPI_UART_Write(Register address, write
data) Actual:SPI_UART_Write(0x50,0x02DA)
SPI_UART_Write(0x51,0x02DA)
SPI_UART_Write(0x52,0x02DA) After writing, the
;GP1
;GQ1
;GS1
display error of the standard table should be within0nearby
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4.First channel phase correction
After the gain has been corrected, phase compensation is performed. in power factor0.5LMake corrections. A known:
0.5LThe error reading of the standard table isErr%
usePQmannerGphs1(6DH) register for phase compensation, according to the compensation formula:
θ=
− err
1.732
= -0.00323
becauseθ<0,Gphs1 = 2 1̂6 + (-0.00323)*2 1̂5 = 0xFF96
useMCUpassSPIorUARTWill0xFF96writeHT7017ofGphs1(6DH)Register: Format:SPI_UART_Write(
Register address, write data) Actual:SPI_UART_Write(0x6D,0xFF96) After writing, the display
error of the standard table should be within0nearby.
5．PoffsetCorrection (small signal active power correction)
After going through the steps1,2,3Afterwards, the userIb = 100%When the meter error is corrected to0Nearby, observe small signalsx%Ib
(5%,2%) point, the meter error isErr%
x%IbClick to read the active power value output on the standard meter under resistancePreal
Apply formula to calculatePoffset =(Preal*EC*HFCONST*2^31*(-Err%))/(5.625*10^10) for
example:
Rated voltage220V, rated current (Ib)5A, the table constant is3200, fast pulse register (HFCONST) reads as0x61, the meter is atIb = 100%
time error correction in0Nearby, observe small signals5%The meter error at point is0.5%, read the small signal from the standard table5%The
output power of the point is55.2 (Preal)
According to the formulaPoffset =(Preal*EC*HFCONST*2 3̂1*(-Err%))/(5.625*10 1̂0) is calculated to get Note: iffemu=2MHz, the appeal
formula calculation result needs to be divided by2,likefemu=500KHz, the appeal formula calculation result needs to be multiplied by2.
Poffset =(Preal*EC*HFCONST*2 3̂1*(-Err%))/(5.625*10 1̂0)
= (55.2*3200*97*2 3̂1*(-0.5%)) / (5.625*10 1̂0) =
-3270.68
becausePoffset < 0, so writing to the registerP1OFFSETHandP1OFFSETLThe value is2 1̂6 + Poffset = 62266
(0xF33A)
useMCUpassSPIorUARTWill0xF3writeHT7017ofP1OFFSETH(65H)register, then pass
SPIorUARTWill0x3AwriteHT7017ofP1OFFSETL(76H)register. Format:SPI_UART_Write(
Register address, write data) Actual:
SPI_UART_Write(0x65,0xF3); SPI_UART_Write(0x76,0x3A); After
writing, the meter is in5%The point display error should be
within0nearby.
6． Second channel gain correction, phase correction
Same as the first channel correction method.
7,IRMSgain,URMSGain and power gain conversion coefficient correction for both channels
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These parameters do not have corresponding registers and need to be calculated and obtained by the user according to their
needs. for example:
with current channel1For example, effective value, current channel1Standard station output5ACurrent effective value, current channel1
valid value register RMS_I1(06H) to read the value of0x03BA55, if the user wants to display the5A, you need to calculate the conversion
coefficient between the two by yourself as follows:K = 5/0x03BA55 = 2.046*10 (̂-5)
hereKIt is the conversion coefficient, and then the user can read it according to theRMS_I1The value of times thisK, the correct current display value will be obtained. See the effective value
output chapter and the power parameter output chapter for details.
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8.Chip packaging
8.1.HT7017(SSOP16)
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9.typical application
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