Microprocessor Notes
& Model Questions
BSC. CSIT
SECOND SEMESTER
Kul Prasad Sapkota
BMC Chitwan

Unit 1: Introduction (4 Hrs.)
Definition of microprocessor and its application

Evolution of microprocessor, Von Neumann and Harvard architecture

Components of microprocessor
a)
Microprocessor: Arithmetic and Logic Unit (ALU), Control Unit (CU), Registers
b)
Memory
c)
Input / Output

System Bus: Data , Address and Control Bus

Microprocessor with Bus Organization
Process: a series of actions or steps taken to achieve an end result
Processor: a machine that completes process
IC: multifunction circuit are combined in a single chip
CPU: Central processing unit which consists of ALU and control unit.
Microprocessor: Single chip containing all units of CPU.s
Micro computer: Computer having microprocessor as CPU.
Microcontroller: Single chip consisting of MPU, Memory, I/ and interfacing circuits.
MPU: Micro processing unit- Complete processing unit with the necessary control signals.
Microprocessor: (An integrated circuit that contains all the functions of a central processing unit of a
computer.)
 It is a multipurpose, programmable, clock-driven, register-based electronic device that reads
binary instruction from a storage device (memory), accepts binary as input and processes
data according to those instructions and provides result as output. Each Microprocessor
communicates and operates in the binary number 0 and 1, called bits. Each MP has fixed sets
of instructions in the form of binary pattern called a machine language.

Features of a Microprocessor
Here is a list of some of the most prominent features of any microprocessor are:

Cost-effective: The microprocessor chips are available at low prices and results its low cost.

Size: The microprocessor is of small size chip, hence is portable.

Low Power Consumption: Microprocessors are manufactured by using metal-oxide
semiconductor technology, which has low power consumption.

Versatility: The microprocessors are versatile as we can use the same chip in a number of
applications by configuring the software program.

Reliability: The failure rate of an IC in microprocessors is very low, hence it is reliable.
Advantages of microprocessor –
 High processing speed
 Compact size
 Easy maintenance
 Can perform complex mathematics
 Flexible
 Can be improved according to requirement
Disadvantages of microprocessors –
 Overheating occurs due to overuse
 Performance depends on size of data
 Large board size than microcontrollers
 Most microprocessors do not support floating point operations

Major function of MP:
 Fetch—Microprocessor gets a software instruction from memory telling it what to do with the
data.
 Decode—Microprocessor determines what the instruction means.
 Execute—Microprocessor performs the instruction.
Applications of MP
The applications of microprocessors are not bound. They can be used virtually anywhere and in any
field.
However, the applications are sorted as follows:
Test Instruments
Microprocessors are widely used in devices such as signal generators, oscilloscopes, counters, digital
multi-meters, x-ray analyzers, blood group analyzers, baby incubator, frequency synthesizers, data
acquisition systems, spectrum analyzers etc. For example fluke 6010A synthesized signal generator uses
4004 microprocessor.
Communications
Communication today requires tens of thousands of circuits to be managed. Data should be received,
checked for errors and further analysis should also be performed. The speed at which the
microprocessor can take decisions and compute errors is truly substantial.
Computer
The microprocessor is a central processing unit (CPU) of the microcomputers. It can perform arithmetic
and logic functions as well as control function. The control unit of microprocessor sends signals to
input, output units, memory, ALU and arrange the sequence of their controlling operation.
Industries
The microprocessor is widely used in data monitoring systems, smart cameras for quality control,
automatic weighing, batching systems, assembly machine control, torque certification systems, machine
tool controller etc.
Security systems: smart cameras, CCTV, smart doors, etc.
Automatic system
Communication system: some examples are:







Calculators
Accounting system
Games machine
Complex industrial controllers
Traffic light control
Data acquisition system
Military applications
Evolution of MP (Intel Series)
4 Bits Microprocessor (Intel 4004)
Intel 4004: The Intel 4004 is a 4-bit central processing unit (CPU) released by Intel
Corporation in 1971. It was the first commercially produced microprocessor, and the first in a long
line of Intel CPUs. The chip design, implemented with the MOS silicon gate technology, started in
April 1970 and completed in 1971
First 4-bit microprocessor









Introduced November 15, 1971 by Intel
First commercially available computer processor
Clock rate 740 kHz.
Executes 60,000 instructions per second
Instruction set contained 46 instructions
Number of Transistors 2,300 at 10 μm
Addressable Memory 640 bytes
Register set contained 16 registers
Designed to be used in Busicom calculator
Successor of Intel 4004 another 4 Bits Microprocessor is Intel 4040





Introduced in 1974
Clock Speed 500 –740 kHz
Instruction set increased to 60 instructions
Number of Transistors 3,000 at 10 μm
Register set increased to 24 registers
First 8-bit processor Intel 8008








Introduced April 1, 1972
Clock Speed 500 kHz
Execute 50,000 instructions per second
Number of Transistors 3,500 at 10 μm
Addressable Memory 16 KB
Register set contained 7 registers
Designed for use in Datapoint2200 microcomputer9
Intel 8080






Introduced April, 1974
Clock Speed 2 MHz
Transistors 4,500 at 6 μm
10 times faster than Intel 8008
Execute 500,000 instructions per second10
Intel 8085





Introduced 1976
Clock Speed 3MHz
Executes 0.37 MIPS
Number of transistors 6,500 at 3 μm
100 million copies were sold
First 16-bit processor Intel 8086




Introduced in June 8, 1978
Introduction of x86 architecture
Clock speed is 4.77 –10 MHz
29,000 transistors at 3 μm
 Execute 2.5 MIPS
 Used in portable computing, IBM PS/2 computers
Intel 8088






Introduced June 1, 1979
Backward compatible 8086
Clock speed is 5 –10 MHz
Created as a cheaper version of Intel’s 8086
Used first in IBM-PC
Highly successful due to large sale of IBM-PC
Intel 80186 & 80188
 Introduced in 1982




Clock speed was 6 MHz
80188 was a cheaper version of 80186
55,000 transistors at 3 μm
Had additional components like
 Interrupt Controller
 Clock Generator
 Local Bus Controller
 Counters
Intel 80286
 Introduced in February 2, 1982






Clock speed was 8 MHz
134,000 transistors at 1.5 μm
Execute 4 MIPS
First with memory management, protection abilities
Introduces “Virtual Memory Concept”
Widely used in IBM PC
First 32-bit processor Intel 80386
 Introduced in October 17, 1985
 Clock speed 16 –33 MHz
 2,75,000 transistors at 1.5 μm
 Address 4 GB of memory
 Concept of paging was introduced Best selling microprocessor in history
First 64 bit processor Intel Core 2 Series
 Introduced on July 27, 2006
 Multi core on a single chip
 Dual, Quad Core processor
 Clock speed 1.06 –3.33 GHz
 291 million transistors at 45nm
 64 KB of L1 cache per core
 4 MB of L2 cache
 Core 2 Duo widely used in desktops, laptops
 Core 2 Quad used for business purposes
Modern Trends of Processor
 Intel was the first microprocessor producer
 Intel owns more than 83% microprocessor market share
 Intel supplies processors to Apple, Samsung, HP, Dell & others
 Intel Core i3, i5 Dual Core are most sold in India
 Gaming Geeks use i7 processors, along with a high power GPU for enhanced
performance
 Processors with suffix “K” can be Over clocked for getting ultimate performance
 Servers, Workstations are deployed on Intel Xeon chips
Conclusion
Microprocessor Growth is tremendous
Speed of microprocessor is increasing day-by-day
Architecture has been reduced to very small, 22 nm
Microprocessor are also used in various devices like mobiles, watches, ATM,
cameras
 Price reduced in recent years
 Much more in the upcoming years




Computer architecture
The Von Neumann architecture is a theoretical computer design based on the concept of storedprogram where programs and data are stored in the same memory. The concept was designed by a
mathematician John Von Neumann in 1945 and currently serves as the foundation of almost all modern
computers. Neumann machine consists of a central processor with an arithmetic/logic unit and a control
unit, a memory, mass storage and input and output.
Von Neumann Architecture
 Program can be saved like data in the memory unit and can be accessed when needed. This
approach is called ‘Stored Program Concept’ and was first adopted by John von Neumann.
 In this architecture, data and instructions are stored in a single set of main memory.
 Instruction fetch and data operation cannot occur at the same time because they share a common
bus.

 The program control unit (PCU) reads program instruction, decodes instruction for ALU and
determines
the sequence of instruction to be executed.

 The
 ALU performs arithmetic and logical operations.
 It is a basic architecture of today’s computer.
 The another architecture like this is Harvard architecture in which instruction and data have separate
memory space; and data & instruction can be accessed at the same time. This is newer approach to
von Neumann architecture.
The Harvard architecture is a computer architecture with physically separate storage and signal
pathways for instructions and data. The term originated from the Harvard Mark I relay-based computer,
which stored instructions on punched tape (24 bits wide) and data in electro-mechanical counters. Some
examples of Harvard architectures involve early computer systems where programming input could be
in one media, for example, punch cards, and stored data could be in another media, for example, on tap.
More modern computers may have modern CPU processes for both systems, but separate them in a
hardware design.
Difference between Von Neumann and Harvard Architecture
Architecture of a micro computer or a micro controller refers to the arrangement of the CPU
with respect of the RAM and ROM. Hence, the Von-Neumann and Harvard architecture are
the two ways through which the micro controller can have its arrangement of the CPU with
RAM and ROM.
Point of
Comparison
Arrangement
Hardware
requirements
Harvard Architecture
Von Neumann Architecture
In Harvard architecture, the CPU is
connected with both the data memory
(RAM) and program memory (ROM),
separately.
In Von-Neumann
architecture, there is no
separate data and program
memory. Instead, a single
memory connection is given
to the CPU.
In contrast to the Harvard
architecture, this requires less
hardware since only a
common memory needs to
It requires more hardware since it will be
requiring separate data and address
bus for each memory.
This requires more space.
Space
requirements
Speed of execution
Space usage
Controlling
Speed of execution is faster
because the processor fetches data
and instructions simultaneously
It results in wastage of space since if the
space is left in the data memory then
the instructions memory cannot use the
space of the data memory and viceversa.
Controlling becomes complex since
data and instructions are to be fetched
simultaneously.
be reached.
Von-Neumann Architecture
requires less space.
Speed of execution is slower
since it cannot fetch the
data and instructions at the
same time.
Space is not wasted because
the space of the data
memory can be utilized by
the instructions memory and
vice-versa.
Controlling becomes simpler
since either data or
instructions are to be fetched
at a time.
Basic Organization of Microcomputer
Microprocessor
It is clock driven semiconductor device consisting of electronic logic circuits
manufactured by using either a large scale integration (LSI) or very large scale
integration (VLSI) technique. It is capable of performing various computing functions
and making decisions to change the sequence of program execution.
It can be divided into three segments.
 Arithmetic/Logic unit: It performs arithmetic operations as addition and
subtraction and logic operations as AND, OR & XOR.
 Register Array : The registers are primarily used to store data temporarily
during the execution of a program and are accessible to the user through
instruction. The registers can be identified by letters such as B,C,D,E,H and
L.
 Control Unit: It provides the necessary timing and control signals to all the
operations in the microcomputer. It controls the flow of data between the
microprocessor and memory & peripherals.
 Memory: Memory stores binary information such as instructions and data
provides that information to the up whenever necessary. To execute programs,
the microprocessor reads instructions and data from memory and performs the
computing operations in its ALU. Results are either transferred to the output
section for display or stored in memory for later use. Memory has two sections.
a) Read only Memory (ROM): Used to store programs that do not need alterations
and can only read.
b) Read /Write Memory (RAM) : Also known as user memory which is used to
store user programs and data. The information stored in this memory can be easily
read and altered.
INPUT/ OUTPUT
 It communicates with the outside world using two devices input and output which
are also known as peripherals.
 The input device such as keyboard, switches, and analog to digital converter
transfer binary information from outside world to the microprocessor.
 The output devices transfer data from the microprocessor to the outside world.
They include the devices such as LED, CRT, digital to analog converter, printer
etc
System bus
The system bus is a communication path between MP and peripherals. It is used to
carry data, address and control signals .It is a group of wires that connect different
components of the computer. It is used for transmitting data, control signal and memory
address from one component to another. A bus can be 8 bit, 16 bit, 32 bit and 64 bit. A
32 bit bus can transmit 32 bit information at a time. A bus can be internal or external.
Or Bus is a group of conducting wires which carries information; all the peripherals are
connected to microprocessor through Bus.
Types of bus:
Address Bus:
It is a group of conducting wires which carries address only.Address bus is unidirectional
because data flow in one direction, from microprocessor to memory or from
microprocessor to Input/output devices (That is, Out of Microprocessor).
Length of Address Bus of 8085 microprocessor is 16 Bit (That is, Four Hexadecimal
Digits), ranging from 0000 H to FFFF H, (H denotes Hexadecimal). The microprocessor
8085 can transfer maximum 16 bit address which means it can address 65, 536 different
memory location.
Data bus
It is a group of conducting wires which carries Data only.Data bus is bidirectional
because data flow in
both directions, from microprocessor to memory or
Input/Output devices and from memory or Input/Output devices to microprocessor.
Length of Data Bus of 8085 microprocessor is 8 Bit (That is, two Hexadecimal
Digits), ranging from 00 H to FF H. (H denotes Hexadecimal).
Control bus
`It is a group of conducting wires, which is used to generate timing and control
signals to control all the associated peripherals, microprocessor uses control bus to
process data, that is what to do with selected memory location. Some control signals
are:
 Memory read
 Memory write
 I/O read
 I/O Write
 Opcode fetch
If one line of control bus may be the read/write line. If the wire is low (no
electricity flowing) then the
memory is read, if the wire is high (electricity is
flowing) then the memory is written.
Important Question for Exam:
1) What is Microprocessor? Draw the architecture of Microprocessor and
explain the each unit.
2) What is System Bus? Explain the difference types of Bus used in computer
or 8085 Microprocessor
3) Explain Von Neumann Architecture and Harvard architecture with suitable
diagram.
4) Explain the Evolution of Microprocessor.
*********
Unit-2
Basic computer Architecture
8085 Microprocessor
Explain the features of 8085 in detail.
The features of 8085 include:
1) It is an 8-bit microprocessor i.e. it can accept, process or provide 8-bit data
simultaneously.
2) It operates on a single +5V power supply connected at Vcc
3) It operates on clock cycle with 50% duly cycle.
4) It has on chip clock generator this internal clock generator requires tuned circuit
like LC, RC or crystal. The internal clock generator divides oscillation frequency
by 2 and generates clock signal, which can be used for synchronizing external
devices.
5) It can operate with 3 MHz clock frequency.
6) It has 16 address buses, hence it can access 216 64 bytes of memory.
7) It provides 8 bit I/o address to acce4ss (28) 256 I / o ports.
8) In 8085, the lower 8-bit address bus (A0-A7) and data bus (D0-D7) are
multiplexed to reduce number of external pins. But due to this, external hardware
is required to separate address lines and data lines.
9) It supports 74 instructions with following addressing modes. (a) Immediate, (b)
Register, (c) Direct (d) Indirect (e) Implied.
10)
The Arithmetic logic unit of 8085 performs a) 8 bit binary addition with or
without carry. (b) 16 bit binary addition (c) 2 digit BCD addition (d) 8-bit binary
subtraction with or without borrow (e) 8-bit logical AND, OR, EX-OR,
complement (NOT) and bit shift operations.
11)
It has 8-bit accumulator, flag register, instruction, register, six 8-bit general
purpose. Registers (B, C, D, E, H and C) and five 16-bit registers (SP and PC)
12)
It provides five hardware interrupts: TRAP, RST 7.5. RST 6.5, RST 5.5 and
INTR.
13)
It has serial I/O control which allows serial communication.
14)
It provides control signals (IO /M, RD, WR) to control bus cycles.
15)
The external hardware (another microprocessor or equivalent master) can
detect which machine cycle microprocessor is executing using status signals
(IO/M, S0, S1) This feature is useful when more than one processors are using
common system resources (memory & I/O devices).
16)
It has mechanism by which it is possible to increase its interrupt handling
capacity.
17)
The 8085 has an ability to share system bus with direct memory access
controller. This feature allows to transfer large amount of data from I/O device to
memory or from memory to I/O device with high speeds.
Draw and explain the architecture of 8085 microprocessor
There are mainly seven functional units of 8085 microprocessor
1. ALU
2. Timing and control unit
3. Instruction register and decoder
4. Register array
5. System bus
6. Interrupt Control
7. Serial I/O Control
1. ALU
 The ALU performs the actual numerical and logic operation such as ‘add’, ‘subtract’, ‘AND’, ‘OR’ etc.
 Uses data from memory and from Accumulator to perform arithmetic operation and always stores result
of operation in Accumulator.
 The ALU consists of accumulator, flag register and temporary register.
a. Accumulator
 The accumulator is an 8-bit register that is a part of arithmetic/logic unit (ALU). This register is used to
store 8-bit data and to perform arithmetic and logical operations. The result of an operation is stored in
the accumulator.
 The accumulator is also identified as register A.
b. Flag register
8085 has 8-bit flag register. There are only 5 active flags.
S
Z
AC
P
CY
Fig: 8085 flag register
Flags are flip-flops which are used to indicate the status of the accumulator and other register after the
completion of operation.
These flip-flops are set or reset according to the data condition of the result in the accumulator and other
registers.
i. Sign flag(S):
Sign flag indicates whether the result of a mathematical or logical operation is negative or positive.
If the result is negative, this flag will be set (i.e. S=1) and if the result is positive, the flag will be reset (i.e. S=0).
ii. Zero flag (Z):
Zero flag indicates whether the result of a mathematical or logical operation is zero or not.
If the result of current operation is zero, the flag will be set (i.e. Z=1) otherwise the flag will be reset (Z=0).
This flag will be modified by the result in the accumulator as well as in the other register.
iii. Auxiliary carry flag (AC):
In operation when a carry is generated by bit D3 and passes on to bit D4, the AC flag will be set otherwise AC
flag will be reset.
This flag is used only internally for BCD operation and is not available for the programmer to change the
sequence of program with the jump instruction.
iv. Parity flag (P):
This flag indicates whether the current result is of even parity (no. of 1’s is even) or odd parity (no. of 1’s is odd).
If even parity, P flag will be set otherwise reset.
v. Carry flag (CY):
This flag indicates whether during an addition or subtraction operation carry or borrow is generated or not.
If carry or borrow is generated, the flag will be set otherwise reset.
2. Timing and control unit
 This unit produces all the timing and control signal for all the operation.
 This unit synchronizes all the MP operations with the clock and generates the control signals necessary
for communication between the MP and peripherals.
3. Instruction register and decoder
 The instruction register and decoder are part of ALU. When an instruction is fetched from memory, it is
loaded in the instruction register.
 The decoder decodes the instruction and establishes the sequence of events to follow.
 The IR is not programmable and cannot be accessed through any instruction.
4. Register array
The register unit of 8085 consists of
 Six general-purpose data registers B,C,D,E,H,L
 Two internal registers W and Z
 Two 16-bit address registers PC (program counter) and SP (stack pointer)
 One increment/decrement counter register
 And, one multiplexer (MUX)
 The six general-purpose registers are used to store 8-bit data. They can be combined as register pairs BC,
DE, and HL to perform some 16-bit operations.
 The two internal registers W and Z are used to hold 8-bit data during the execution of some instructions,
CALL and XCHG instructions.
 SP is 16-bit registers used to point the address of data stored in the stack memory. It always indicates the top
of the stack.
 PC is 16-bit register used to point the address of the next instruction to be fetched and executed stored in the
memory.
5. System bus
a. Data bus:It carries ‘data’, in binary form, between MP and other external units, such as memory.
Typical size is 8 or 16 bits.
b. Address bus:It carries ‘address’ of operand in binary form.
Typical size is 16-bit.
c. Control Bus: Control Bus are various lines which have specific functions for coordinating and controlling
MP operations. E.g.: Read/Write control line
6. Interrupt Control
 Interrupt is a signal, which suspends the routine what the MP is doing, brings the control to perform the
subroutine, completes it and returns to main routine.
 May be hardware or software interrupts. Some interrupts may be ignored (maskable), some cannot (nonmaskable).
 E.g. INTR, TRAP, RST 7.5, RST 6.5, RST 5.5
7. Serial I/O Control
 The MP performs serial data input or output (one bit at a time). In serial transmission, data bits are sent
over a single line, one bit at a time.
 The 8085 has two signals to implement the serial transmission: SID (serial input data) and SOD (serial
output data).
Draw the Pin Diagram of 8085 Microprocessor
An 8085 microprocessor is an IC with 40 pins and operates with +5V power supply. The
pin configuration plays a very important role in understanding the architecture of 8085
microprocessor.
The figure below shows the pin diagram of 8085 showing 40 pin configurations:
The signals of this 40 pin IC is grouped into 7 categories, which are given below:
 Power supply and clock signals
 Data bus
 Address bus
 Serial I/O ports
 Control and status signals
 Interrupts and externally generated signals
 Direct memory access
1.Power supply and clock signals:
In 40 pin configuration, 4 pins are allotted to this particular category.
VCC – Pin number 40 denotes VCC, and an external power supply of + 5 V is provided at this pin.
VSS – Its pin number is 20. This pin shows the grounded connection of the microprocessor.
X1 and X2 – These are represented by pin number 1 and 2 respectively in the pin configuration. These 2
pins are connected with a crystal or LC network to maintain the internal frequency of the clock
generator.
CLK (OUT) – It is the 37th pin of the 8085 IC and acts as the system clock that keeps the record of time
duration required by each operation to get completed.
2.Address Bus – This category contains 8 pins.
The address bus has 16 lines i.e.; it can carry 16 bits at a time. However, out of 16, 8 are
multiplexed with the data bus and the leftover 8 are separately shown by pin number 21 to 28 in the pin
configuration.
These are used to carry the address of data and instruction from the processor to the memory
location and is unidirectional in nature. These are denoted by A8 to A15 that represents the 8 MSB of
the memory location or input-output address.
3.Data Bus with multiplexed address bus – This category also contains 8 pins.
The size of the data bus of the 8085 microprocessor is 8 bits. However, to reduce the number of bus
lines these 8-bit data bus lines are multiplexed with the 8-bit address bus.These are shown by pin
number 12 to 19. The address bus is denoted by A whereas the data bus is denoted by D. The pin
configuration denotes the lower order multiplexed address and data bus bits from AD0 to AD7.
4.Serial I/O ports :
It has basically 2 pins.
SID – SID denotes serial input data pin and its pin is numbered as 5. With this pin, data is serially fed to
the processor directly through the input devices.
SOD – SOD denotes serial output data pin and its pin number is 4, in the pin configuration of 8085.
Once the data is processed in the microprocessor then this pin represents bit by bit results at the
output devices.
5.Control and status signals :
Basically, 6 pins of the pin configuration are used by control and status signals.
ALE – ALE is an acronym for address latch enable and is pin number 30 in the configuration. We know
that 8 lower order bits of the 16-bit address bus are multiplexed with the 8-bit data bus.
This pin gets enabled at the time when the address is present at the multiplexed address and data bus.
Otherwise, it gets disabled showing the absence of an address on the bus.
RD – This pin is numbered 32 in the configuration and a low signal in this pin shows the read
operation either from I/O devices or from the memory unit. Thereby indicating that the data bus is
now in a state or position to accept the data from the memory or I/O devices.
WR – It is the 31st pin in the pin diagram and a low signal in this pin represents the write operation at
the memory or I/O devices. This indicates that the data present in the data bus is to be written into
the desired memory address or I/O device by the processor.
IO/M – It is pin number 34 and indicates the selection of a memory address or input-output device.
This shows whether the read/write operation is to be carried out at the memory location or at the I/O
device.
The low signal at this pin shows that operation is performing over memory location. As against, a high
signal at this pin represents the operation at I/O device.
S0 and S1 – The pins S0 and S1 represent the status signal at pin number 29 and 33 respectively. These
signals show the type of recent operation of the microprocessor. The table below represents the
status of the data bus under different conditions:
6.Interrupts and Externally generated signals:
Interrupts are the signals that are generated to break the sequence of an ongoing operation. When an
interrupt signal is generated then CPU immediately stops its recent task under operation and switches
to some other program known as interrupt service routine (ISR).
However, after handling ISR, the CPU gets back to its main program for execution.
In the pin configuration, 5 types of interrupts are shown by 5 different pins from pin number 6 to 10.
These pins are used to manage the interrupt.
Basically, there exist 2 types of interrupts:
Maskable Interrupt and Non- maskable interrupt
Out of the 5 major interrupts 4 are the maskable interrupts. These are INTR, RST5.5, RST6.5, RST7.5
and are easily manageable interrupts.
However, TRAP is a non-maskable interrupt and holds the topmost priority among all interrupts in the
8085 microprocessor.
RESET IN – It is pin number 36 in the pin diagram. An active low signal at this pin resets the PC of the
microprocessor to 0. Or we can say, after resetting the PC holds its initial memory address.
RESET OUT – It is the 3rd pin in the pin diagram. This pin generates a signal to provide information
about the resetting of the microprocessor. Also, we can say that once a processor is reset then all the
connected devices must also be reset.
So, enabling this signal shows the resetting of the interconnected devices.
INTA: It is the 11th pin of the 8085 pin configuration. A signal at this pin acknowledges the generated
interrupt.
7. Direct Memory Access (DMA) :
We are aware of the fact that memory and I/O devices are connected with each other by the
microprocessor. So, the intermediator i.e., CPU manages the data transfer between the input-output
device and memory.
However, when data in a large amount is to be transferred between I/O devices and memory the CPU
gets disabled by tri-stating its buses. And this transfer is manageable by external control circuits. The
DMA has 2 pins.
HOLD – This signal is generated at pin number 39. This pin generates a signal to notify the processor
that more than one request is present to access the data and address bus.
When this signal gets enabled, the CPU frees the bus after completion of the recent operation. Once
the hold signal gets disabled, the processor can access the bus again.
HLDA -This signal is generated at pin number 38. This signal is enabled at the time when the processor
gets HOLD signal and it releases HLDA i.e., hold acknowledge signal. In order to show that the multiple
requests are kept on hold and will be considered once the bus gets free after the recent operation.
After the disabling of hold request, the HLDA signal becomes low.
READY -This is the 35th numbered pin in the pin diagram that maintains synchronization between the
processor and peripherals, memory. It is clear that a microprocessor has a much faster response than
peripherals and memory.
So, this pin is enabled when the processor as well as the peripherals and memory both become ready
to begin the next operation.
In the case when the READY pin is disabled, then the microprocessor is in the WAIT state.
Explain the various addressing modes of 8085 microprocessor with example.
The term addressing modes refers to the way in which the operand of an instruction is
specified. The addressing mode specifies a rule for interpreting or modifying the address
field of the instruction before the operand is actually executed.
The 8085 has 5 addressing modes. These are:
1. Immediate addressing mode: In an immediate addressing mode, 8 or 16 bit data can
be specified as a part of instruction. In 8085, the instructions having ‘I’ letter fall under
this category. “I’ indicates immediate addressing mode.
Example: MVI A, 20H:
moves 8-bit immediate data(20H) into
accumulator.
LXI D,10FF H : moves 16-bit immediate data into DE register pair.
2. Register addressing mode: The register addressing mode specifies the source
operand, destination operand or both to be contained in an 8085 registers. This results in
faster execution, since it is not necessary to access memory locations for operands.
Example: MOV A, B :Moves the contents of register B into the accumulator.
SPHL: Moves the contents of HL register pair into stack pointer.
3. Direct addressing mode: The direct addressing mode specifies the 16- bit address of
the operand within the instruction itself. The second and third bytes of instruction
contain this 16 bit address.
Example: LDA 2000H: loads the 8bit contents of memory location 2000H into the
accumulator
SHLD 3000H : Stores the HL register pair into two consecutive memory locations.
Lower contents of L register into memory location 3000H and higher contents of H
register into memory location 3001H.
4. Indirect addressing mode: In indirect addressing mode, the memory address where the
operand located is specified by the contents of a register pair.
Example: LDAX B :
loads the accumulator with the contents of memory
location pointed by BC register pair.
MOV M, A :
Stores the contents of accumulator into the memory location
pointed by HL register pair
5. Implied addressing mode: In implied addressing mode, Opcode specifies the address
of the operands.
Example: CMA: Complements contents of accumulator.
RAL: Rotates the contents of accumulator left through the carry.
Difference between 8085 & 8086 Microprocessor
8085 Microprocessor
8086 Microprocessor
Is an 8 Bit Microprocessor
Is a 16 Bit Microprocessor
Has 8 bit data bus
Has 16 bit data bus
Has 16 bit address line
Has 20 bit address line
Only 64KB of memory can be used (216)
1 MB of memory can be used (220)
Has 5 Flags (Carry , Parity, Sign, Zero, Auxillary
Carry)
It is Accumulator based processor
Has 9 Flags (Carry, parity, Sign, Zero, Auxillary Carry,
Direction, Trap, Interrupt, Overflow)
It is general purpose Register Based processor
It has no MIN mode or MAX mode
It can operate in any one of MIN or MAX Mode
Does not support popelining
Supports pipelining
Does not support Memory segmentation
Supports Memory Segmentation
Has 6500 transistors
Has 29000 transistors
8085
8 bit microprocessor
16 Bit address bus
can access upto 2^16 = 64 KB of memory
8086
16 bit microprocessor
20 bit address bus
can access upto 2^20 = 1MB of mem
4. Instruction Queue
5.Pipelining
6. Multiprocessing
Support
7. I/O
8. Arithmetic support
doesn't have an instruction queue
does not support pipelined architechture
does not support multiprocessing support
has instruction queue
supports pipelined architechture
supports multiprocessing support
can address 2^8= 256 I/O's
only supports integer and decimal
9. Multiplication and
Division
10. Operating Mides
Doesn't support
can access 2^16= 65.536/O's
supports integer, decimal and ASCII
arithmetic
Supports
supports only single operating mode
operates in two modes
11. External Hardware
12. Cost
13. Memory
segmentation
Requires less
Low
Memory space is not segmented
Requires
High
Memory space is segmented
1. Size
2. Address Bus
3. Memory
8085 Microprocessor
8086 Microprocessor
It is 8 bit Microprocessor
It is 16 bit microprocessor
It has 16 bit address line
It has 20 bit address line
It has 8 bit data bus
It has 16 bit data bus
Clock speed of 8085 microprocessor is 3 MHZ
It has 5 flags
Clock speed of 8086 microprocessor vary between 5,8an
10 MHz for different versions.
It has 9 flags
It does not support pipelining
It supports pipelining.
It operates on clock cycle with 50% duty cycle.
It operates on clock cycle with 33% duty cycle.
8085 Microprocessor does not support memory
segmentation.
It has less number of transistors compare to 8086
microprocessor. It is about 65000 in size.
It is accumulator based processor.
8086 microprocessor supports memory segmentation.
It has more number of transistors compare to 8085
microprocessor. It is about 29000 in size.
it is general purpose register based processor.
ss
8086 Microprocessor
Write the silent features of 8086 Microprocessor
1)
2)
3)
4)
8086 microprocessor is a general purpose register based processor.
The size of the data bus in 8086 microprocessor is 16-bit.
The size the address bus in 8086 microprocessor is 20-bit.
The clock speed in 8086 microprocessor was initially limited to 5MHz but it goes up to 10 MHz
nowadays.
5) The flag register in 8086 microprocessor contains 9 flags that is, Overflow Flag, Direction Flag,
Interrupt Flag, Trap Flag, Sign Flag, Zero Flag, Auxiliary Flag, Carry Flag and Parity Flag.
6) The microprocessor supports pipe-lining as it has two independent units; the Execution unit
(EU) and Bus Interface Unit (BIU).
7) 8086 microprocessor holds a very large number of transistors in its structure. It is about 29000
in size.
8) 8086 microprocessor supports two modes of operation, that is minimum and maximum mode.
9) 8086 microprocessor supports memory segmentation.
10) 8086 microprocessor supports integer, decimal and ASCII arithmetic.
11) It requires more external hardware.
12) 8086 has multiplication and division instructions.
13) 8086 can access up to 1MB of memory.
14) 8086 is a multi-processor configuration microprocessor.
15) The instruction queue is supported in 8086 microprocessor.
Draw the 8086 architecture with the help of its EU and BIU
The 8086 is a 16-bit microprocessor. The term 16 bit implies that its arithmetic logic unit, its internal
registers, and most of its instructions are intended to work with 16 bit binary data. The 8086 has a 16 bit
data bus, so it can read data from or write data to memory and ports either 16 bits or 8 bits at a time.
The 8086 has a 20 bit address bus
The 8086 CPU is divided into two independent functional units:
1. Bus Interface Unit (BIU)
2. Execution Unit (EU)
Bus Interface Unit (BIU)
It handles all transfers of data and addresses on the buses for the execution unit. Sends out addresses
Fetches instructions from memory
Read / write data from/to ports and memory i.e. handles all transfers of data and addresses on the
busses
Execution Unit (EU)
Tells BIU where to fetch instructions or data from
Decodes instructions
Explain the 8086 Microprocessor with all functional units
1) EU (Execution Unit)
Execution unit gives instructions to BIU stating from where to fetch the data and then decode and
execute those instructions. Its function is to control operations on data using the instruction decoder &
ALU. EU has no direct connection with system buses as shown in the above figure, it performs
operations over data through BIU.
Let us now discuss the functional parts of 8086 microprocessors.
ALU
It handles all arithmetic and logical operations, like +, −, ×, /, OR, AND, NOT operations.
Flag Register
It is a 16-bit register that behaves like a flip-flop, i.e. it changes its status according to the result stored
in the accumulator. It has 9 flags and they are divided into 2 groups − Conditional Flags and Control
Flags.
Conditional Flags
It represents the result of the last arithmetic or logical instruction executed. Following is the list of
conditional flags −
Carry flag − This flag indicates an overflow condition for arithmetic operations.
Auxiliary flag − When an operation is performed at ALU, it results in a carry/barrow from lower nibble
(i.e. D0 – D3) to upper nibble (i.e. D4 – D7), then this flag is set, i.e. carry given by D3 bit to D4 is AF
flag. The processor uses this flag to perform binary to BCD conversion.
Parity flag − This flag is used to indicate the parity of the result, i.e. when the lower order 8-bits of the
result contains even number of 1’s, then the Parity Flag is set. For odd number of 1’s, the Parity Flag is
reset.
Zero flag − This flag is set to 1 when the result of arithmetic or logical operation is zero else it is set to
0.
Sign flag − This flag holds the sign of the result, i.e. when the result of the operation is negative, then
the sign flag is set to 1 else set to 0.
Overflow flag − This flag represents the result when the system capacity is exceeded.
Control Flags
Control flags controls the operations of the execution unit. Following is the list of control flags −
Trap flag − It is used for single step control and allows the user to execute one instruction at a time for
debugging. If it is set, then the program can be run in a single step mode.
Interrupt flag − It is an interrupt enable/disable flag, i.e. used to allow/prohibit the interruption of a
program. It is set to 1 for interrupt enabled condition and set to 0 for interrupt disabled condition.
Direction flag − It is used in string operation. As the name suggests when it is set then string bytes are
accessed from the higher memory address to the lower memory address and vice-a-versa.
General purpose register
There are 8 general purpose registers, i.e., AH, AL, BH, BL, CH, CL, DH, and DL. These registers can
be used individually to store 8-bit data and can be used in pairs to store 16bit data. The valid register
pairs are AH and AL, BH and BL, CH and CL, and DH and DL. It is referred to the AX, BX, CX, and
DX respectively.
AX register − It is also known as accumulator register. It is used to store operands for arithmetic
operations.
BX register − It is used as a base register. It is used to store the starting base address of the memory
area within the data segment.
CX register − It is referred to as counter. It is used in loop instruction to store the loop counter.
DX register − This register is used to hold I/O port address for I/O instruction.
Stack pointer register
It is a 16-bit register, which holds the address from the start of the segment to the memory location,
where a word was most recently stored on the stack.
2) BIU (Bus Interface Unit)
BIU takes care of all data and addresses transfers on the buses for the EU like sending addresses,
fetching instructions from the memory, reading data from the ports and the memory as well as writing
data to the ports and the memory. EU has no direction connection with System Buses so this is possible
with the BIU. EU and BIU are connected with the Internal Bus.
It has the following functional parts −
Instruction queue − BIU contains the instruction queue. BIU gets up to 6 bytes of next instructions and
stores them in the instruction queue. When EU executes instructions and is ready for its next instruction,
then it simply reads the instruction from this instruction queue resulting in increased execution speed.
Fetching the next instruction while the current instruction executes is called pipelining.
Segment register − BIU has 4 segment buses, i.e. CS, DS, SS& ES. It holds the addresses of
instructions and data in memory, which are used by the processor to access memory locations. It also
contains 1 pointer register IP, which holds the address of the next instruction to executed by the EU.
CS − It stands for Code Segment. It is used for addressing a memory location in the code segment of
the memory, where the executable program is stored.
DS − It stands for Data Segment. It consists of data used by the program and it accessed in the data
segment by an offset address or the content of other register that holds the offset address.
SS − It stands for Stack Segment. It handles memory to store data and addresses during execution.
ES − It stands for Extra Segment. ES is additional data segment, which is used by the string to hold the
extra destination data.
Instruction pointer − It is a 16-bit register used to hold the address of the next instruction to be
executed.
Note: Summary of register
Data Registers
AX = Accumulator Register
BX = Base Register
DX = Data Register
CX = Count Register
Index Registers
SI = Source Index
DI = Destination Index
Segment Registers
DS = Data Segment
SS = Stack Segment
ES = Extra Segment
CS = Code Segment
Pointer Registers
IP = Instruction Pointer
BP = Base Pointer
SP = Stack Pointer
Explain the various addressing modes of 8086 microprocessor with example.
ADDRESSING MODES OF 8086
1) Immediate addressing mode
2) Register addressing mode
3) Direct memory addressing mode
4) Register based indirect addressing mode
5) Register relative addressing mode
6) Base indexed addressing mode
7) Relative based indexed addressing mode
8) Implied addressing mode
1) Immediate addressing mode
The addressing mode in which the data operand is a part of the instruction itself is known as immediate
addressing mode.
Example:
MOV CX, 4929 H, ADD AX, 2387 H, MOV AL, FFH
2) Register addressing mode
It means that the register is the source of an operand for an instruction.
Example:
MOV CX, AX ; copies the contents of the 16-bit AX register into
; the 16-bit CX register),
ADD BX, AX
3) Direct addressing mode
The addressing mode in which the effective address of the memory location is written directly in the
instruction.
Example:
MOV AX, [1592H], MOV AL, [0300H]
4) Register indirect addressing mode
This addressing mode allows data to be addressed at any memory location through an offset address
held in any of the following registers: BP, BX, DI & SI.
Example:
MOV AX, [BX] ; Suppose the register BX contains 4895H, then the contents
; 4895H are moved to AX
ADD CX, {BX}
5) Based addressing mode
In this addressing mode, the offset address of the operand is given by the sum of contents of the BX/BP
registers and 8-bit/16-bit displacement.
Example:
MOV DX, [BX+04], ADD CL, [BX+08]
6) Indexed addressing mode
In this addressing mode, the operands offset address is found by adding the contents of SI or DI register
and 8-bit/16-bit displacements.
Example:
MOV BX, [SI+16], ADD AL, [DI+16]
7) Based-index addressing mode
In this addressing mode, the offset address of the operand is computed by summing the base register to
the contents of an Index register.
Example:
ADD CX, [AX+SI], MOV AX, [AX+DI]
8) Based indexed with displacement mode
In this addressing mode, the operands offset is computed by adding the base register contents. An Index
registers contents and 8 or 16-bit displacement.
Example:
MOV AX, [BX+DI+08], ADD CX, [BX+SI+16]
What is pipeline? Explain instruction pipeline in brief
Pipeline in 8086 is a technique which is used in advanced microprocessors, was the
microprocessor executes a second instruction before the completion of first. That is many instructions
are simultaneously pipelined at different processing stage.
The advantages of pipelining is performance improvement, we are able to pump more instructions and
get improved in processor speed as we are able to execute parts of instructions in parallel to parts of
other instruction.
An instruction pipeline reads instruction from the memory while previous instructions
are being executed in other segments of the pipeline. Thus we can execute multiple
instructions simultaneously. The pipeline will be more efficient if the instruction cycle is
divided into segments of equal duration.
In the most general case computer needs to process each instruction in following sequence
of steps:
1) Fetch the instruction from memory (FI)
2) Decode the instruction (DA)
3) Calculate the effective address
4) Fetch the operands from memory (FO)
5) Execute the instruction (EX)
6) Store the result in the proper place
Here the instruction is fetched on first clock cycle in segment 1.
Now it is decoded in next clock cycle, then operands are fetched and finally the
instruction is executed. We can see that here the fetch and decode phase overlap due
to pipelining. By the time the first instruction is being decoded, next instruction is
fetched by the pipeline.
In case of third instruction we see that it is a branched instruction. Here when it is
being decoded 4th instruction is fetched simultaneously.
What is Memory Segmented? List out the advantages and disadvantages of memory
Segmentation
Segmentation is the process in which the main memory of the computer is logically divided into
different segments and each segment has its own base address. It is basically used to enhance the speed of
execution of the computer system, so that the processor is able to fetch and execute the data from the memory
easily and fast.
Need for Segmentation –
The Bus Interface Unit (BIU) contains four 16 bit special purpose registers (mentioned below) called as
Segment Registers.
Code segment register (CS): is used for addressing memory location in the code segment of the memory,
where the executable program is stored.
Data segment register (DS): points to the data segment of the memory where the data is stored.
Extra Segment Register (ES): also refers to a segment in the memory which is another data segment in the
memory.
Stack Segment Register (SS): is used for addressing stack segment of the memory. The stack segment is that
segment of memory which is used to store stack data.
Advantages of the Segmentation The main advantages of segmentation are as follows:
 It provides a powerful memory management mechanism.
 Data related or stack related operations can be performed in different segments.
 Code related operation can be done in separate code segments.
 It allows to processes to easily share data.
 It allows extending the address ability of the processor, i.e. segmentation allows the use
of 16 bit registers to give an addressing capability of 1 Megabytes. Without
segmentation, it would require 20 bit registers.
 It is possible to enhance the memory size of code data or stack segments beyond 64 KB
by allotting more than one segment for each area.
Disadvantages of Memory Segmentation
• It is a costly technique as compared to the other one.
• External fragmentation is there in it.
• Since there is a variably sized partition. So, it is difficult to allocate memory to them.
Important question for Exam:
1) Draw and explain the pin diagram of 8085 Microprocessor.
2) Explain 8086 architecture with the help of its EU and BIU
3) Draw the 8086 architecture with the help of its EU and BIU
4) Explain the addressing mode of 8085 Microprocessor.
5) Explain the addressing mode of 8086 Microprocessor.
6) What is pipeline? Explain instruction pipeline in brief
*********************************************
Unit-3
Instruction cycle
Time required to execute and fetch an entire instruction is called instruction cycle. It
consists:
 Fetch cycle – The next instruction is fetched by the address stored in program
counter (PC) and then stored in the instruction register.
 Decode instruction – Decoder interprets the encoded instruction from instruction
register.
 Reading effective address – The address given in instruction is read from main
memory and required data is fetched. The effective address depends on direct
addressing mode or indirect addressing mode.
 Execution cycle – consists memory read (MR), memory write (MW), input output
read (IOR) and input output write (IOW)
The time required by the microprocessor to complete an operation of accessing
memory or input/output devices is called machine cycle. One time period of
frequency of microprocessor is called t-state. A t-state is measured from the falling
edge of one clock pulse to the falling edge of the next clock pulse.
Fetch cycle takes four t-states and execution cycle takes three t-states.
Note:
Instruction Cycle: The time required to execute an instruction is called instruction
cycle.
Machine Cycle: The time required to access the memory or input/output devices is
called machine cycle.
T-State: The machine cycle and instruction cycle takes multiple clock periods. A
portion of an operation carried out in one system clock period is called as T-state.
MACHINE CYCLES OF 8085:
The 8085 microprocessor has 5 (Five) basic machine cycles. They are
1. Op-code fetch cycle (4T)
2. Memory read cycle (3 T)
3. Memory write cycle (3 T)
4. I/O read cycle (3 T)
5. I/O write cycle (3 T)




Each instruction of the 8085 processor consists of one to five machine cycles, i.e., when the 8085
processor executes an instruction, it will execute some of the machine cycles in a specific order.
The processor takes a definite time to execute the machine cycles. The time taken by the processor to
execute a machine cycle is expressed in T-states.
One T-state is equal to the time period of the internal clock signal of the processor.
The T-state starts at the falling edge of a clock.
Timing Diagram of 8085 Microprocessor
Timing Diagram is a graphical representation. It represents the execution time taken by each
instruction in a graphical format. The execution time is represented in T-states
Point to remember while making timing diagram.

CLK (OUT) : It is the 37th pin of the 8085 IC and acts as the system clock that keeps the record
of time duration required by each operation to get completed.

A8 to A15 :The address bus is a group of sixteen lines i.e A0-A15. The address bus is
unidirectional, i.e., bits flow in one direction from the microprocessor unit to the peripheral
devices and uses the high order address bus.

AD0 to AD7: The address bus is denoted by A whereas the data bus is denoted by D. The pin
configuration denotes the lower order multiplexed address and data bus bits from AD0 to AD7.
Control and Status Signals:
 ALE – It is an Address Latch Enable signal. It goes high during first T state of a machine cycle and
enables the lower 8-bits of the address, if its value is 1 otherwise data bus is activated.
 IO/M’ – It is a status signal which determines whether the address is for input-output or memory.
When it is high(1) the address on the address bus is for input-output devices. When it is low(0) the
address on the address bus is for the memory.
 SO, S1 – These are status signals. They distinguish the various types of operations such as halt,
reading, instruction fetching or writing.


RD’ – It is a signal to control READ operation. When it is low the selected memory or inputoutput device is read.
WR’ – It is a signal to control WRITE operation. When it goes low the data on the data bus is
written into the selected memory or I/O location.


Opcode fetch machine cycle of 8085:
Each instruction of the processor has one byte opcode.
The opcode are store in memory. So the processor executes the opcode fetch machine cycle to fetch the
opcode from memory.
 Hence, every instruction starts with opcode fetch machine cycle.
o The time taken by the processor to execute the opcode fetch cycle is 4T.
o In this time, the first, 3 T-states are used for fetching the opcode from memory and the remaining Tstates are used for internal operations by the processor.
2. Memory read cycle (3 T)



The memory read machine cycle is executed by the processor to read a data byte from memory.
The processor takes 3T states to execute this cycle.
The instructions which have more than one byte word size will use the machine cycle after the opcode
fetch machine cycle
Memory Write Machine Cycle of 8085:
 The memory write machine cycle is executed by the processor to write a data byte in a memory location.
 The processor takes,3T states to execute this machine cycle.



I/O Read Cycle of 8085:
The I/O Read cycle is executed by the processor to read a data byte from I/O port or from the peripheral,
which is I/O, mapped in the system.
The processor takes 3T states to execute this machine cycle.
The IN instruction uses this machine cycle during the execution
I/O write cycle (3 T)
 The I/O write machine cycle is executed by the processor to write a data byte in the I/O port or to
a peripheral, which is I/O, mapped in the system
 The processor takes, 3T states to execute this machine cycle
Timing Diagram of MOV, MVI, IN, OUT, LDA, STA
i)MOV
E.g. MOV A,B
ii) Timing diagram for MVI B, 43H.

Fetching the Opcode 06H from the memory 2000H. (OF machine
cycle)

Read (move) the data 43H from memory 2001H. (memory read)

IN Timing diagram for IN C0H
 Fetching the Op-code DBH from the memory 4125H.
 Read the port address C0H from 4126H.
 Read the content of port C0H and send it to the accumulator.
 Let the content of port is 5EH
Timing diagram for STA 526AH
Step to solve
 STA means Store Accumulator -The contents of the accumulator is stored in the specified
address (526A).
 The Opcode of the STA instruction is said to be 32H. It is fetched from the memory 41FFH (see
fig). - OF machine cycle
 Then the lower order memory address is read(6A). – Memory R
 Read the higher order memory address (52).- Memory Read Machine Cycle.
 The combinations of both the addresses are considered and the content from accumulator is written in
526A. – Memory Write Machine Cycle

Assume the memory address for the instruction and let the content of accumulator is C7H. So,
C7H from accumulator is now stored in 526A
Memory Interfacing and generation of chip select signal
A microprocessor has to be interfaced with various peripherals to perform various functions. Let's discuss about
the Interfacing techniques in detail.
 We know that a microprocessor is the CPU of a computer.
 A microprocessor can perform some operation on a data and give the output. But to perform the operation we
need an input to enter the data and an output to display the results of the operation.
Interfacing Types
There are two types of interfacing in context of the 8085 processor.
(a) Memory Interfacing.
(b) I/O Interfacing.
1. Microprocessor 8085 can access 64Kbytes memory since address bus is 16-bit. But it is not always
necessary to use full 64Kbytes address space. The total memory size depends upon the application.
2. Generally EPROM (or EPROMs) is used as a program memory and RAM (or RAMs) as a data memory.
When both, EPROM and RAM are used, the total address space 64Kbytes is shared by them.
3. The capacity of program memory and data memory depends on the application.
4. It is not always necessary to select 1 EPROM and 1 RAM. We can have multiple EPROMs and multiple
RAMs as per the requirement of application.
5. We can place EPROM/RAM anywhere in full 64 Kbytes address space. But program memory (EPROM)
should be located from address 0000H since reset address of 8085 microprocessor is 0000H.
6. It is not always necessary to locate EPROM and RAM in consecutive memory For example: If the
mapping of EPROM is from 0000H to OFFFH, it is not must to locate RAM from 1000H. We can locate
it anywhere between 1000H and FFFFH. Where to locate memory component totally depends on the
application.
The memory interfacing requires to:

Select the chip


Identify the register
Enable the appropriate buffer.
Microprocessor system includes memory devices and I/O devices. It is important to note that
microprocessor can communicate (read/write) with only one device at a time, since the data, address and control
buses are common for all the devices. In order to communicate with memory or I/O devices, it is necessary to
decode the address from the microprocessor. Due to this each device (memory or I/O) can be accessed
independently.
Control Signals of 8085
The 8085 Microprocessor provides RD and WR signals to initiate read or write cycle. Because these
Control Signals of 8085 are used both for reading/writing memory and for reading/writing an input device, it is
necessary to generate separate read and write signals for memory and I/O devices.
The 8085 provides IO/M signal to indicate whether the initiated cycle is for I/O device or for memory
device. Using IO/M signal along with RD and WR, it is possible to generate separate four Control Signals of
8085.
Exam Questions:
 Define Instruction Cycle, Machine Cycle and T-state and draw the timing diagram of Opcode fetch
cycle.
 Draw the timing diagram of MVI A, 32H and explain it.
 Draw the timing diagram of STA 526 AH and explain its.
 Draw the timing diagram of MOV A,B and explain its.
*********************
Unit-4
Assembly Language program
Instruction Set of 8085
An instruction is a binary pattern designed inside a microprocessor to perform a
specific function. The entire group of instructions that a microprocessor supports is
called Instruction Set.
8085 has 246 instructions. Each instruction is represented by an 8-bit binary value.
These 8- bits of binary value is called Op-Code or Instruction Byte.
Following are the classification of instructions:
a)
b)
c)
d)
e)
Data Transfer Instruction
Arithmetic Instructions
Logical Instructions
Branching Instructions
Control Instructions
a) Data Transfer Instruction
These instructions move data between registers, or between memory and registers.
These instructions copy data from source to destination. While copying, the contents
of source are not modified.
Example: MOV, MVI
b) Arithmetic Instructions
These instructions perform the operations like addition, subtraction, increment and
decrement.
Example: ADD, SUB, INR, DCR
c)Logical Instructions
These instructions perform logical operations on data stored in registers and memory.
The logical operations are: AND, OR, XOR, Rotate, Compare and Complement.
Example: ANA, ORA, RAR, RAL, CMP, CMA
d) Branching Instructions
Branching instructions refer to the act of switching execution to a different instruction
sequence as a result of executing a branch instruction. The three types of branching
instructions are: Jump, Call and Return.
e) Control Instructions
The control instructions control the operation of microprocessor. Examples: HLT, NOP,
EI (Enable Interrupt), DI (Disable Interrupt).
1. 8085 instruction set.
Sr.
Instruction
Description
Example
DATA DATA TRANSFER INSTRUCTIONS
1.
MOV Rd, Rs
This instruction copies the contents of the source
MOV M, Rs
register into the destination register; the contents of the
source register are not altered. If one of the operands is
MOV Rs, M
a memory location, its location is specified by the
contents of the HL registers.
The 8-bit data is stored in the destination register or
2.
MVI Rd,
memory. If the operand is a memory location, its
data MVI M,
location is specified by the contents of the HL
data
registers.
3.
LDA 16-bit address
The contents of a memory location, specified by a 16bit address in the operand, are copied to the
accumulator. The contents of the source are not
altered.
4.
LDAX B/D Reg. pair
The contents of the designated register pair point to
a memory location. This instruction copies the
contents of that memory location into the accumulator.
The contents of either the register pair or the memory
location are not altered.
5.
LXI Reg.-pair, 16-bit data
The instruction loads 16-bit data in the register
pair
designated in the operand.
6.
LHLD 16-bit address
The instruction copies the contents of the memory
location pointed out by the 16-bit address into register
L and copies the contents of the next memory location
into register H. The contents of source memory
locations are not altered.
7.
STA 16-bit address
The contents of the accumulator are copied into the
memory location specified by the operand. This is a 3byte instruction, the second byte specifies the loworder address and the third byte specifies the highorder address.
8.
STAX Reg. pair
The contents of the accumulator are copied into the
memory location specified by the contents of the
operand (register pair). The contents of the
accumulator are not altered.
MOV B, C
MOV B, M
MVI B, 57H
MVI M, 57H
LDA 2034H
LDAX B
LXI H, 2034H
LXI H, XYZ
LHLD 2040H
STA 4350H
STAX B
Sr.
Instruction
Description
Example
9.
SHLD 16-bit address
10.
XCHG
11.
SPHL
12.
XTHL
SHLD 2470H
The contents of register L are stored into the memory
location specified by the 16-bit address in the operand
and the contents of H register are stored into the next
memory location by incrementing the operand. The
contents of registers HL are not altered. This is a 3byte instruction, the second byte specifies the loworder address and the third byte specifies the highorder address.
The contents of register H are exchanged with the XCHG
contents of register D, and the contents of register L
are exchanged with the contents of register E.
The instruction loads the contents of the H and L SPHL
registers into the stack pointer register, the contents of
the H register provide the high-order address and the
contents of the L register provide the low-order
address. The contents of the H and L registers are not
altered.
The contents of the L register are exchanged with the XTHL
stack location pointed out by the contents of the stack
pointer register. The contents of the H register are
exchanged with the next stack location (SP+1);
however, the contents of the stack pointer register are
not altered.
PUSH
The contents of the register pair designated in the
B
operand are copied onto the stack in the following
PUSH
sequence. The stack pointer register is decremented
A
and the contents of the high order register (B, D, H,
A) are copied into that location. The stack pointer
register is decremented again and the contents of the
low-order register (C, E, L, flags) are copied to that
location.
13.
PUSH Reg. pair
14.
POP Reg. pair
The contents of the memory location pointed out by
the stack pointer register are copied to the low-order
POP
register (C, E, L, status flags) of the operand. The
HPOP
stack pointer is incremented by 1 and the contents of
A
that memory location are copied to the high-order
register (B, D, H, A) of the operand. The stack pointer
register is again incremented by 1.
15.
OUT 8-bit port address
The contents of the accumulator are copied into the
I/O port specified by the operand.
16.
IN 8-bit port address
The contents of the input port designated in the
operand are read and loaded into the accumulator.
OUT F8H
IN 8CH
ARITHMETIC INSTRUCTIONS
Sr.
17.
Instruction
ADD R
ADD M
18.
ADC
R
ADC
M
19.
ADI 8-bit data
20.
ACI 8-bit data
21.
DAD Reg. pair
22.
23.
SUB
R
SUB
M
SBB
R
SBB
M
Description
Example
The contents of the operand (register or memory) are
added to the contents of the accumulator and the result
is stored in the accumulator. If the operand is a
memory location, its location is specified by the
contents of the HL registers. All flags are modified to
reflect
the
result
of
the
addition.
The contents of the operand (register or memory) and
the Carry flag are added to the contents of the
accumulator and the result is stored in the accumulator.
If the operand is a memory location, its location is
specified by the contents of the HL registers. All flags
are modified to reflect the result of the addition.
ADD B
ADD M
ADC B
ADC
M
ADI 45H
The 8-bit data (operand) is added to the contents of
the accumulator and the result is stored in the
accumulator. All flags are modified to reflect the
result of the addition.
The 8-bit data (operand) and the Carry flag are added ACI 45H
to the contents of the accumulator and the result is
stored in the accumulator. All flags are modified to
reflect the result of the addition.
DAD H
The 16-bit contents of the specified register pair are
added to the contents of the HL register and the sum is
stored in the HL register. The contents of the source
register pair are not altered. If the result is larger than
16 bits, the CY flag is set. No other flags are affected.
The contents of the operand (register or memory) are
subtracted from the contents of the accumulator, and
the result is stored in the accumulator. If the operand is
a memory location, its location is specified by the
contents of the HL registers. All flags are modified to
reflect the result of the subtraction.
The contents of the operand (register or memory) and
the Borrow flag are subtracted from the contents of the
accumulator and the result is placed in the
accumulator. If the operand is a memory location, its
location is specified by the contents of the HL
registers. All flags are modified to reflect the result of
the subtraction.
SUB B
SUB M
SBB B
SBB M
Sr.
Instruction
Description
Example
24.
SUI 8-bit data
25.
SBI 8-bit data
26.
INR
R
INR
M
SUI 45H
The 8-bit data (operand) is subtracted from the
contents of the accumulator and the result is stored in
the accumulator. All flags are modified to reflect the
result of the subtraction.
The 8-bit data (operand) and the Borrow flag are SBI 45H
subtracted from the contents of the accumulator and
the result is stored in the accumulator. All flags are
modified to reflect the result of the subtraction.
The contents of the designated register or memory are INR B
incremented by 1 and the result is stored in the same INR M
place. If the operand is a memory location, its location
is specified by the contents of the HL registers.
27.
INX R
28.
29.
DCR
R
DCR
M
DCX R
30.
DAA
The contents of the designated register pair are INX H
incremented by 1 and the result is stored in the same
place.
The contents of the designated register or memory are DCR B
decremented by 1 and the result is stored in the same DCR M
place. If the operand is a memory location, its location
is specified by the contents of the HL registers.
The contents of the designated register pair are DCX H
decremented by 1 and the result is stored in the same
place.
The contents of the accumulator are changed from a DAA
binary value to two 4-bit binary coded decimal (BCD)
digits. This is the only instruction that uses the
auxiliary flag to perform the binary to BCD
conversion, and the conversion procedure is described
below. S, Z, AC, P, CY flags are altered to reflect the
results of the operation.
If the value of the low-order 4-bits in the accumulator
is greater than 9 or if AC flag is set, the instruction
adds 6 to the low-order four bits.
If the value of the high-order 4-bits in the accumulator
is greater than 9 or if the Carry flag is set, the
instruction adds 6 to the high-order four bits.
Sr.
Instruction
Description
Example BRANCHING INSTRUCTIONS
31.
JMP 16-bit address
The program sequence is transferred to the memory
location specified by the 16-bit address given in the
operand.
JMP 2034H
JMP XYZ
Jump conditionally
The program sequence is transferred to the memory location specified
by the 16-bit address given in the operand based on the specified flag
of the PSW as described below.
32.
JC 16-bit address
Jump on Carry, Flag Status: CY=1
JC 2050H
33.
JNC 16-bit address
Jump on no Carry, Flag Status: CY=0
JNC 2050H
34.
JP 16-bit address
Jump on positive, Flag Status: S=0
JP 2050H
35.
JM 16-bit address
Jump on minus, Flag Status: S=1
JM 2050H
36.
JZ 16-bit address
Jump on zero, Flag Status: Z=1
JZ 2050H
37.
JNZ 16-bit address
Jump on no zero, Flag Status: Z=0
JNZ 2050H
38.
JPE 16-bit address
Jump on parity even, Flag Status: P=1
JPE 2050H
39.
JPO 16-bit address
Jump on parity odd, Flag Status: P=0
JPO 2050H
40.
CALL 16-bit address
The program sequence is transferred to the memory
location specified by the 16-bit address given in the
operand. Before the transfer, the address of the next
instruction after CALL (the contents of the program
counter) is pushed onto the stack.
CALL 2034H
CALL XYZ
Call conditionally
The program sequence is transferred to the memory location specified
by the 16-bit address given in the operand based on the specified flag
of the PSW as described below. Before the transfer, the address of the
next instruction after the call (the contents of the program counter) is
pushed onto the stack.
41.
CC 16-bit address
Call on Carry, Flag Status: CY=1
CC 2050H
42.
CNC 16-bit address
Call on no Carry, Flag Status: CY=0
CNC 2050H
43.
CP 16-bit address
Call on positive, Flag Status: S=0
CP 2050H
44.
CM 16-bit address
Call on minus, Flag Status: S=1
CM 2050H
45.
CZ 16-bit address
Call on zero, Flag Status: Z=1
CZ 2050H
46.
CNZ 16-bit address
Call on no zero, Flag Status: Z=0
CNZ 2050H
47.
CPE 16-bit address
Call on parity even, Flag Status: P=1
CPE 2050H
48.
CPO 16-bit address
Call on parity odd, Flag Status: P=0
CPO 2050H
Sr.
Instruction
Description
49.
RET
The program sequence is transferred from the RET
subroutine to the calling program. The two bytes
from the top of the stack are copied into the program
counter, and program execution begins at the new
address.
Return
from
conditionally
50.
51.
52.
53.
54.
55.
56.
57.
RC
RNC
RP
RM
RZ
RNZ
RPE
RPO
subroutine
Example
The program sequence is transferred from the subroutine to the calling
program based on the specified flag of the PSW as described below.
The two bytes from the top of the stack are copied into the program
counter, and program execution begins at the new address.
Return on Carry, Flag Status: CY=1
RC
Return on no Carry, Flag Status: CY=0
RNC
Return on positive, Flag Status: S=0
RP
Return on minus, Flag Status: S=1
RM
Return on zero, Flag Status: Z=1
RZ
Return on no zero, Flag Status: Z=0
RNZ
Return on parity even, Flag Status: P=1
RPE
Return on parity odd, Flag Status: P=0
RPO
58. PCHL
The contents of registers H and L are copied into the PCHL
program counter. The contents of H are placed as the
high-order byte and the contents of L as the loworder byte.
59. RST 0-7
The RST instruction is equivalent to a 1-byte call RST 3
instruction to one of eight memory locations
depending upon the number. The instructions are
generally used in conjunction with interrupts and
inserted using
external
hardware.
However
these can be used as software instructions in a program
to transfer program execution to one of the eight
locations. The addresses are:
Instruction
Restart Address
RST 0
0000H
RST 1
0008H
RST 2
0010H
RST 3
0018H
RST 4
0020H
RST 5
0028H
RST 6
0030H
RST 7
0038H
Sr.
Instruction
Description
The 8085 has four additional interrupts and these interrupts generate RST instructions
thus do not require any external hardware.
60. TRAP
It restart from address 0024H
61. RST 5.5
It restart from address 002CH
62. RST 6.5
It restart from address 0034H
63. RST 7.5
It restart from address 003CH
LOGICAL INSTRUCTIONS
The contents of the operand (register or memory) are
64. CMP R
compared with the contents of the accumulator. Both
CMP M
contents are preserved. The result of the comparison is
shown by setting the flags of the PSW as follows:
if (A) < (reg/mem): carry flag is set
if (A) = (reg/mem): zero flag is set
if (A) > (reg/mem): carry and zero flags are reset
65. CPI 8-bit data
The second byte (8-bit data) is compared with the
contents of the accumulator. The values being
compared remain unchanged. The result of the
comparison is shown by setting the flags of the PSW
as follows:
if (A) < data: carry flag is
set if (A) = data: zero flag is
set
if (A) > data: carry and zero flags are reset
The contents of the accumulator are logically ANDed
66. ANA
with the contents of the operand (register or memory),
R
and the result is placed in the accumulator. If the
ANA
operand is a memory location, its address is specified
M
by the contents of HL registers. S, Z, P are modified to
reflect the result of the operation. CY is reset. AC is
set.
67. ANI 8-bit data
The contents of the accumulator are logically ANDed
with the 8-bit data (operand) and the result is placed in
the accumulator. S, Z, P are modified to reflect the
result of the operation. CY is reset. AC is set.
The contents of the accumulator are Exclusive ORed
68. XRA
with the contents of the operand (register or memory),
R
and the result is placed in the accumulator. If the
XRA
operand is a memory location, its address is specified
M
by the contents of HL registers. S, Z, P are modified to
reflect the result of the operation. CY and AC are
reset.
Example
internally and
TRAP
RST 5.5
RST 6.5
RST 7.5
CMP B
CMP
M
CPI 89H
ANA
B
ANA
M
ANI 86H
XRA
B
XRA
M
Sr.
Instruction
Description
Example
69.
XRI 8-bit data
XRI 86H
70.
ORA
R
ORA
M
71.
ORI 8-bit data
72.
RLC
73.
RRC
74.
RAL
75.
RAR
76.
CMA
77.
CMC
The contents of the accumulator are Exclusive ORed
with the 8-bit data (operand) and the result is placed in
the accumulator. S, Z, P are modified to reflect the
result of the operation. CY and AC are reset.
The contents of the accumulator are logically ORed
with the contents of the operand (register or memory),
and the result is placed in the accumulator. If the
operand is a memory location, its address is specified
by the contents of HL registers. S, Z, P are modified to
reflect the result of the operation. CY and AC are reset.
The contents of the accumulator are logically ORed
with the 8-bit data (operand) and the result is placed in
the accumulator. S, Z, P are modified to reflect the
result of the operation. CY and AC are reset.
Each binary bit of the accumulator is rotated left by
one position. Bit D7 is placed in the position of D0 as
well as in the Carry flag. CY is modified according
to bit D7. S, Z, P, AC are not affected.
Each binary bit of the accumulator is rotated right by
one position. Bit D0 is placed in the position of D7 as
well as in the Carry flag. CY is modified according
to bit D0. S, Z, P, AC are not affected.
Each binary bit of the accumulator is rotated left by
one position through the Carry flag. Bit D7 is placed
in the Carry flag, and the Carry flag is placed in the
least significant position D0. CY is modified
according to bit D7. S, Z, P, AC are not affected.
Each binary bit of the accumulator is rotated right by
one position through the Carry flag. Bit D0 is
placed in the Carry flag, and the Carry flag is placed in
the most significant position D7. CY is modified
according to bit D0. S, Z, P, AC are not affected.
The contents of the accumulator are complemented.
No flags are affected.
The Carry flag is complemented. No other flags are
affected.
ORA
B
ORA
M
ORI 86H
RLC
RRC
RAL
RAR
CM
A
CM
C
78. STC
The Carry flag is set to 1. No other flags are affected.
CONTROL INSTRUCTIONS
79. NOP
No operation is performed. The instruction is fetched
and decoded. However no operation is executed.
STC
NOP
Sr.
Instruction
Description
Example
80.
HLT
HLT
81.
DI
82.
EI
83.
RIM
The CPU finishes executing the current instruction
and halts any further execution. An interrupt or reset is
necessary to exit from the halt state.
The interrupt enable flip-flop is reset and all the
interrupts except the TRAP are disabled. No flags are
affected.
The interrupt enable flip-flop is set and all interrupts
are enabled. No flags are affected. After a system reset
or the acknowledgement of an interrupt, the interrupt
enable flip-flop is reset, thus disabling the interrupts.
This instruction is necessary to re enable the interrupts
(except TRAP).
This is a multipurpose instruction used to read the
status of interrupts 7.5, 6.5, 5.5 and read serial data
input bit. The instruction loads eight bits in the
accumulator with the following interpretations.
D7
D6
SI
D
I7
I6
Serial Input
Data bit
Interrupts
pending if
84.
SIM
D4
D3
D2
D1
D0
I5
IE
7.5
6.5
5.5
InteSeri
al
Output
DI
EI
RIM
Interrupt
masked
if bit=1
This is a multipurpose instruction and used to SIM
implement the 8085 interrupts 7.5, 6.5, 5.5, and serial
data output. The instruction interprets the accumulator
contents as follows.
8085 Programs
1. Program to add two 8-bit numbers.
Statement: Add numbers 05H & 13H and display result in output port 03H.
MVI A,05H
MVI B,13H
ADD B
OUT 03H
HLT
//Move data 05H to accumulator
//Move data 13H to B register
//Add contents of accumulator and B register
//Transfer result to output port 03H
//Terminate the program.
Input: A=05H B=13H
Output: (port 03H) = 18H
2. Program to add two 8-bit numbers.
Statement: Add numbers from memory location 2050H & 2051H and store result in
memory location 2055H.
LDA 2051H
B,A
LDA 2050H
B
STA 2055H
//Load contents of memory location 2051 to accumulator MOV
//Move contents of accumulator to B register
//Load contents of memory location 2050 to accumulator ADD
// Add contents of accumulator and B register
//Store contents of accumulator in memory location 2055H HLT
//Terminate the program.
Input:
Memory Location
2050H
2051H
Data
45H
53H
Output:
Memory Location
2055H
Data
98H
3. Program to subtract two 8-bit numbers.
Statement: Subtract numbers 25H & 12H and display result in output port 01H.
MVI A,25H
MVI B,12H
SUB B
OUT 01H
HLT
//Move data 05H to accumulator
//Move data 13H to B register
//Add contents of accumulator and B register
//Transfer result to output port 01H
//Terminate the program.
Input: A=25H B=12H
Output: (port 03H) = 13H
4. Program to subtract two 8-bit numbers.
Statement: Subtract numbers from memory location 2050H & 2051H and store result
in memory location 2055H.
LDA 2051H
B,A
//Load contents of memory location 2051 to accumulator MOV
//Move contents of accumulator to B register
LDA 2050H
B
STA 2055H
//Load contents of memory location 2050 to accumulator SUB
// Add contents of accumulator and B register
//Store contents of accumulator in memory location 2055H HLT
//Terminate the program.
Input:
Memory Location
2050H
2051H
Data
65H
53H
Output:
Memory Location
2055H
Data
12H
5. Program to find 1’s complement of a number.
Statement: Input number from memory location 2013H and store result in memory
location 2052H.
LDA 2013H
STA 2052H
HLT
//Load contents from memory location 2013H to accumulator CMA
//Complement contents of accumulator
//Store result in memory location 2052H
//Terminate the program.
Input:
Memory Location
2013H
Data
12H
Output:
Memory Location
2052H
Data
EDH
6. Program to find 2’s complement of a number.
Statement: Input number from memory location 2013H and store result in memory
location 2052H.
LDA 2013H
ADI 01H
STA 2052H
//Load contents from memory location 2013H to accumulator CMA
//Complement contents of accumulator
//Add 01H to the contents of accumulator
//Store result in memory location 2052H HLT
//Terminate the program.
Input:
Memory Location
2013H
Data
12H
Output:
Memory Location
2052H
Data
EEH
7. Program to right shift 8-bit numbers.
Statement: Shift an eight-bit data four bits right. Assume data is in memory location
2051H. Store result in memory location 2055H.
LDA 2051H
RAR
RAR
RAR
STA 2055H
HLT
//Load data from memory location 2051H to accumulator RAR
//Rotate accumulator 1-bit right
//Store result in memory location 2055H
//Terminate the program.
8. Program to left shift 8-bit numbers.
Statement: Shift an eight-bit data four bits left. Assume data is in memory location
2051H. Store result in memory location 2055H.
LDA 2051H
RAR
RAR
RAR
STA 2055H
HLT
//Load data from memory location 2051H to accumulator RAL
//Rotate accumulator 1-bit left
//Store result in memory location 2055H
//Terminate the program.
9. Program to add two 16-bit numbers.
Statement: Add numbers 1124H & 2253H and store result in memory location 2055H
& 2056H.
LXI H,1124H
LXI D,2253H
MOV A,L
ADD E
MOV L,A
MOV A,H
ADC D
MOV H,A
SHLD 2055H
//Load 16-bit data 1124H to HL pair
//Load 16-bit data 2253H to DE pair
//Move contents of register L to Accumulator
//Add contents of Accumulator and E register
//Move contents of Accumulator to L register
//Move contents of register H to Accumulator
//Add contents of Accumulator and D register with carry
//Move contents of Accumulator to register H
//Store contents of HL pair in memory address 2055H & 2056H HLT
//Terminate the program.
Input:
Register Pair
HL
DE
Output:
Memory Location
2055H
2056H
Data
1124H
2253H
Data
77H
33H
10. Program to add two 16-bit numbers.
Statement: Input first number from memory location 2050H & 2051H and second
number from memory location 2052H & 2053H and store result in memory location
2055H & 2056H.
LHLD 2052H
XCHG
LHLD 2050H
MOV A,L
ADD E
MOV L,A
MOV A,H
ADC D
MOV H,A
SHLD 2055H
//Load 16-bit number from memory location 2052H & 2053H to HL pair
//Exchange contents of HL pair and DE pair
//Load 16-bit number from memory location 2050H & 2051H to HL pair
//Move contents of register L to Accumulator
//Add contents of Accumulator and E register
//Move contents of Accumulator to L register
//Move contents of register H to Accumulator
//Add contents of Accumulator and D register with carry
//Move contents of Accumulator to register H
//Store contents of HL pair in memory address 2055H & 2056H HLT
//Terminate the program.
Input:
Memory Location
2050H
2051H
2052H
2053H
Output:
Memory Location
Data
33H
45H
24H
34H
Data
2055H
2056H
57H
79H
11. Program to subtract two 16-bit numbers.
Statement: Subtract number 1234H from 4897H and store result in memory location
2055H & 2056H.
LXI H,4567H
LXI D,1234H
MOV A,L
MOV L,A
A,H
SBB D
H,A
SHLD 2055H
//Load 16-bit data 4897H to HL pair
//Load 16-bit data 1234H to DE pair
//Move contents of register L to Accumulator SUB E
//Subtract contents of Accumulator and E register
//Move contents of Accumulator to L register MOV
//Move contents of register H to Accumulator
//Subtract contents of Accumulator and D register with borrow MOV
//Move contents of Accumulator to register H
//Store contents of HL pair in memory address 2055H & 2056H HLT
//Terminate the program.
Input:
Register Pair
HL
DE
Output:
Memory Location
2055H
2056H
Data
4897H
1234H
Data
63H
36H
12. Program to subtract two 16-bit numbers.
Statement: Input first number from memory location 2050H & 2051H and second
number from memory location 2052H & 2053H and store result in memory location
2055H & 2056H.
LHLD 2052H //Load 16-bit number from memory location 2052H & 2053H to HL pair
XCHG
//Exchange contents of HL pair and DE pair
LHLD 2050H //Load 16-bit number from memory location 2050H & 2051H to HL pair
MOV A,L
//Move contents of register L to Accumulator SUB E
//Subtract contents of Accumulator and E register
MOV L,A
//Move contents of Accumulator to L register MOV
A,H
//Move contents of register H to Accumulator
SBB D
//Subtract contents of Accumulator and D register with carry MOV
H,A
//Move contents of Accumulator to register H
SHLD 2055H
//Store contents of HL pair in memory address 2055H & 2056H HLT
//Terminate the program.
Input:
Memory Location
2050H
2051H
2052H
2053H
Output:
Memory Location
2055H
2056H
Data
78H
45H
24H
34H
Data
54H
11H
13. Program to multiply two 8-bit numbers.
Statement: Multiply 06 and 03 and store result in memory location 2055H.
MVI A,00H MVI
B,06H MIV C,03H
X: ADD B DCR C
JNZ X
STA 2055H HLT
14. Program to divide to 8-bit numbers.
Statement: Divide 08H and 03H and store quotient in memory location 2055H and remainder in
memory location 2056H.
MVI A,08H MVI
B,03H MVI C,00H
X: CMP B
JC Y
SUB
B INR
C
JMP
X
Y: STA 2056H MOV
A,C STA 2055H HLT
15. Program to find greatest among two 8-bit numbers.
Statement: Input numbers from memory location 2050H & 2051H and store greatest number in memory
location 2055H.
LDA 2051H MOV
B,A LDA 2050H
CMP B
JNC X MOV A,B
X: STA 2055H HLT
16. Program to find smallest among two 8-bit numbers.
Statement: Input numbers from memory location 2050H & 2051H and store smallest number in memory
location 2055H.
LDA 2051H MOV
B,A LDA 2050H
CMP B
JC X MOV A,B
X: STA 2055H HLT
17. Program to find whether a number is odd or even.
Statement: Input number from memory location 2050H and store result in 2055H. LDA 2050H
ANI 01H JZ X
MVI A,0DH
JMP Y
X: MVI A,0EH Y: STA
2055H HLT
18. Program to count no. of 1’s in given number.
Statement: Input number from memory location 2050H and store result in 2055H. LDA 2050H
MVI C,08H MVI
B,00H X: RAR
JNC Y
INR B
Y: DCR
C
JNZ X MOV A,B
STA 2055H HLT
19. Display number from 1 to 10.
LXI
H,2050H
MVI B,01H
MVI C,0AH
X: MOV
M,B
INX
H
INR
B
DCR
C
JNZ
X
HLT
20. Find sum of numbers from 1 to 10.
LXI
H,2050H
MVI B,01H
MVI
C,0AH
MVI A,00H
X: ADD B
INX
H
INR
B
DCR
C
JNZ
X
STA
2055H
HLT
21. Display all odd numbers from 1 to 10.
LXI
H,2050H
MVI B,01H
MVI C,0AH
X: MOV
M,B
INX
H
INR
B
INR
B
DCR
C
DCR
C
JNZ
X
HLT
22. Display all even numbers from 1 to 20.
LXI
H,2050H
MVI B,02H
MVI C,14H
X: MOV
M,B
INX
H
INR
B
INR
B
DCR
C
DCR
C
JNZ
X
HLT
23. Display all even numbers from 10 to 50.
LXI
H,2050H
MVI B,0AH
MVI C,32H
X: MOV
M,B
INX
H
INR
B
INR
B
DCR
C
DCR
C
JNZ
X
HLT
24. Find sum of 10 numbers in array.
LXI
H,2050H
MVI
C,OAH
MVI A,00H
X: MOV
B,M ADD
B
INX
H
DCR
C
JNZ
X
STA
2060H
HLT
25. Find the largest element in a block of data. The length of the block is in the memory
location 2200H and block itself starts from memory location 2201H. Store the maximum
number in memory location 2300H.
LDA
2200H
MOV C,A
LXI
H,2201
MVI
A,00H X:
CMP M
JNC Y
MOV
A,M
Y: INX
H
DCR
C
JNZ
X
STA
2300H
HLT
26. Find smallest number in array.
LDA
2200H
MOV C,A
LXI
H,2201H
MVI A,00H
X: CMP M
JC Y
MOV
A,M Y:
INX H
DCR C
JNZ X
STA
2300H
HLT
27. Generate Fibonacci series upto 10th term.
LXI
H,2050H
MVI C,08H
MVI B,00H
MVI D,01H
MOV M,B
INX H
MOV M,D
X: MOV
A,B
ADD D
MOV
B,D
MOV
D,A INX
H MOV
M,A
DCR C
JNZ X
HLT
28. Sort 10 numbers in ascending order in array.
MVI C,0AH DCR C
X: MOV D,C
LXI
H,2050H
Y: MOV
A,M INX
H CMP
M JC Z
MOV B,M MOV
M,A DCX H MOV
M,B INX H
Z: DCR D
JNZ Y
DCR
C JNZ
X
HLT
29. Sort numbers in descending order in array. Length of array is in memory
location 2050H.
LDA 2050H MVI
C,A DCR C
X: MOV D,C
LXI
H,2051H
Y: MOV
A,M INX
H CMP M
JNC Z
MOV B,M MOV
M,A DCX H MOV
M,B INX H
Z: DCR D
JNZ Y
DCR
C JNZ
X
HLT
30. Multiply two 8 bit numbers 43H & 07H. Result is stored at address 3050 and 3051.
LXI H,0000H MVI
D,00H MVI E,43H
MVI C,07H X: DAD
D
DCR C JNZ X
SHLD 2050H HLT
31. Multiply two 8 bit numbers stored at address 2050 and 2051. Result is stored at
address 3050 and 3051.
LDA 2050H MOV
E,A LDA 2051H
MOV C,A MVI
D,00H LXI H,0000H
X: DAD D
DCR C JNZ X
SHLD 3050H HLT
8086 Programs
1. Program to add two 8-bit numbers.
Statement: Add data 05H & 13H and store result in memory location 2050H. MOV AL,05H
MOV BL,13H ADD AL,BL MOV
2050H,AL HLT
2. Program to add two 8-bit numbers.
Statement: Input numbers from memory location 2050H and 2051H and store in memory location 2055H.
MOV SI,2050H MOV AL,[SI]
INC SI
MOV BL,[SI] ADD AL,BL MOV
2055H,AL HLT
3. Program to add two 16-bit numbers.
Statement: Add numbers 1122H & 2233H and store result in memory location 2055H.
MOV AX,1122H MOV BX,2233H
ADD AX,BX MOV 2055H,AH
MOV 2056H,AL HLT
4. Program to subtract two 8-bit numbers.
Statement: Subtract data 05H from 13H and store result in memory location 2050H. MOV AL,13H
MOV BL,05H SUB AL,BL MOV
2050H,AL HLT
5. Program to subtracct two 8-bit numbers.
Statement: Input numbers from memory location 2050H and 2051H and store in memory location 2055H.
MOV SI,2050H MOV AL,[SI]
INC SI
MOV BL,[SI] SUB AL,BL
MOV 2055H,AL HLT
6. Program to subtract two 16-bit numbers.
Statement: Subtract numbers 1122H from 2233H and store result in memory location 2055H.
MOV AX,2233H MOV BX,1122H
SUB AX,BX MOV 2055H,AH
MOV 2056H,AL HLT
7. Program to multiply two 8-bit numbers.
Statement: Multiply 06H & 03H and store result in memory location 2055H. MOV AL,06H
MOV BL,03H MUL BL
MOV 2055H,AL HLT
8. Program to multiply two 8-bit numbers.
Statement: Multiply 43H & 13H and store result in memory location 2055H and 2056H. (This program works
for 16-bit too.)
MOV AX,0043H MOV BX,0013H
MUL BX
MOV 2055H,AH MOV 2056H,AL
HLT
9. Program to divide two 8-bit numbers.
Statement: Divide 43H & 13H and store result in memory location 2055H. MOV AL,43H
MOV BL,13H DIV BL
MOV 2055H,AL HLT
10. Program to divide two 8-bit numbers.
Statement: Divide 43H & 13H and store quotient in 2055H and remainder in 2056H. MOV AL,43H
MOV BL,13H MOV CL,00H X:
CMP AL,BL
JNC
Y SUB
AL,BL
INC CL
Y: MOV 2056H,AL MOV
AL,BL MOV 2055H,AL
HLT
11. Program to divide two 16-bit numbers.
Statement: Divide 1243H & 0013H and store result in memory location 2055H & 2056H.
MOV AX,1243H MOV BX,0013H
DIV BX
MOV 2055H,AL MOV 2056H,BL
HLT
12. Program to find sum of numbers from 1 to 10.
MOV AL,00H MOV BL,01H
MOV CL,0AH X: ADD BL
INC BL LOOP
X
MOV 2055H,AL HLT
13. Program to display numbers from 1 to 20.
MOV SI,2050H‘ MOV BL,01H
MOV CL,14H X: MOV [SI],BL
INC BL LOOP
X
HLT
14. Program to find factorial of given number. (Number is in memory location 2050H).
MOV CX,2050H MOV AX,00H
X: MUL CX
LOOP X MOV 2055H,AH
MOV 2056H,AL HLT
(Likewise all programs done in 8085 can be done in 8086)
15. Program to display string “I love my country” in screen.
.DATA
MESSAGE DB "I love my country$"
.CODE START:
MOV AX,DATA MOV
DS,AX
MOV AH,09H INT 21H
MOV AH,4CH INT
21H
END START
16. Program to display string “I love my country” in screen character by character.
.DATA
MESSAGE DB "I love my country$"
.CODE
START:
MOV AX,DATA MOV
DS,AX
LEA SI,MESSAGE MOV
CL,11H L1:MOV DX,[SI]
MOV AH,02H INT 21H
INC SI LOOP L1
MOV AH,4CH INT
21H
END START
17. Program to reverse any string.
.DATA
MESSAGE DB "BSC CSIT$"
.CODE
START:
MOV AX,DATA MOV
DS,AX
LEA SI,MESSAGE
MOV CL,08H L1:MOV
BX,[SI]
PUSH BX INC SI
LOOP L1
MOV CL,05H L2:POP DX
MOV AH,02H INT
21H LOOP L2
MOV AH,4CH INT
21H
END START
(This program can be used for example program for stact PUSH and POP operation)
Some Exam Questions:
1) Write a program in 8-bit microprocessor to multiply two 16-bit numbers and store in the
memory location starting from 3500H. Save the carry bits in the location starting from
3600H
2) Write an assembly language program to find the greatest number in an array in using
8 bit microprocessor. (Assume appropriate array data and address where minimum
array size of 20 should be considered.)
3) Write an assembly language program to find the smallest number in an array using 8
bit microprocessor. (Assume appropriate array data and address where minimum
array size of 15 should be considered.)
4) Ten number of 8-bit data stored at memory location 6000H. Write a program for 8085
microprocessor to calculate the sum of odd numbers and store the sum of odd
numbers and store the sum at 6010H.(The sum may exceed 8-biys).
5) Write an assembly language program to subtract two 16-bit numbers.
6) Write and explain assembly language program to multiply 05H and 06H.
7) Write an ALP for 8086 to read string and print it in the reverse order.
UIT V
Basic I/O, Memory R/W & Interrupt Operations
#Explain I/O Operations method Memory Mapped I/O and I/O
Mapped I/O.
CPU uses two methods to perform input/output operations between the CPU and peripheral devices in the
computer. These two methods are called memory mapped IO and IO mapped IO.


Memory-mapped IO uses the same address space to address both memory and I/O devices.
On the other hand, IO mapped IO uses separate address spaces to address memory and IO
devices.

Memory Mapped I/O
Memory mapped IO uses one address space for memory and input and output devices. In other words, some
addresses are assigned to memory while others are assigned to store the addresses of IO devices.
There is one set of read and write instruction lines. The same set of instructions work for both memory and IO
operations. Therefore, the instructions used to manipulate memory can be used for IO devices too. Hence, it
can lessen the addressing capability of memory because some are occupied by the IO.
I/O Mapped I/O
IO mapped IO uses two separate address spaces for memory locations and for IO devices. There are two
separate control lines for both memory and IO transfer. In other words, there are different read-write
instruction for both IO and memory.
IO read and IO write are for IO transfer whereas memory read and memory write are for memory transfer. IO
mapped IO is also called port-mapped IO or isolated IO.
The main difference between memory mapped IO and IO mapped IO is that the memory mapped IO uses
the same address space for both memory and IO device while the IO mapped IO uses two separate
address spaces for memory and IO device.
#Differences between Memory-mapped I/O and I/O mapped I/O
S.N.
1.
Memory-mapped I/O
The I/O devices and memory, both are
treated as memory.
2.
The I/O devices are provided with 16-bit
address values (in 8085)
The interfaced devices are accessed by the
memory read or memory write cycles.
The peripherals or the I/O ports are treated as
memory locations. Thus, all the instructions
related to the memory can be utilized for the
data exchange between the processor and
the I/O device.
In the memory-mapped ports, the information
data can be moved to the I/O devices from
any register or vice versa.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
The full memory address space cannot be
used solely for addressing memory for
interfacing.
Data transfer is possible between any register
and I/O device.
Here, a large number of I/O ports (216 ports)
are possible to be used for interfacing.
While executing the memory, write or read
cycles, the IO/M` is set to low (IO/M` = 0 ).
There is more decoder hardware involved.
Separate control signals are not required
since we have a unified memory space.
We can perform arithmetic and logical
operations on the data.
I/O mapped I/O
The I/O devices are treated as I/O
devices and the memory is treated as
memory.
The I/O devices are provided with 8-bit
address values. (In 8085)
The interfaced devices are accessed by
the I/O read or I/O write cycles.
Only the IN and the OUT instructions can
be put to use for transferring information
between the I/O device and the
processor.
In the I/O mapped ports, the information
bytes can be moved around between
the ports and the accumulator register
only.
The full memory address space can be
used solely for addressing memory for
interfacing.
Data transfer is possible between the
accumulator and I/O device only.
Only 256 I/O ports i.e., 28 ports, are made
available for interfacing.
While executing the I/O write or read
cycles, the IO/M` is set to high (IO/M` = 1
).
There is less decoder hardware involved.
Special control signals are used here
since we have separate memory spaces.
We cannot perform arithmetic and
logical operations on the data.
#Discuss DMA with the help its advantages and application
Direct Memory Access (DMA)
•
•
•
•
•
•
•
Direct memory access (DMA) is a method that allows an input/output (I/O) device to send or receive
data directly to or from the main memory, bypassing the CPU to speed up memory operations.
The process is managed by a chip known as a DMA controller (DMAC).
It moves the data between memory and peripheral without bothering the CPU. This means it frees up
both CPU power and bandwidth between CPU and main memory.
For a CPU based copy, the data has to go into and out of the CPU, which is often a slow process and
blocks both the core doing the copy and the other cores. And if the data flow has gaps, as it will in the
case of HDD and network, the CPU can sit there wasting time until more data becomes available.
If the data rate is very low, DMA is overkill. But if the data is either fast or large, DMA offloads the
CPU and lets it get on with useful work.
The problem of slow data transfer between input-output port and memory or between two memories is
avoided by implementing Direct Memory Access (DMA) technique.
This is faster as the microprocessor/computer is bypassed and the control of address bus and data bus is
given to the DMA controller.
Advantages & Disadvantages of DMA
Advantages



Transferring the data without the involvement of the processor will speed up the read-write task.
DMA reduces the clock cycle requires to read or write a block of data.
DMA allows faster processing since the processor can be working on something else while the
peripheral can be populating memory.
DMA enables more efficient use of interrupts.
High transfer rates.
DMA capable device can communicate directly with memory.
Implementing DMA also reduces the overhead of the processor.




Disadvantages
•
•
Cost of DMA hardware.
Data has to be stored in continuous memory locations.
•
DMA controller is slow in comparison to CPU.
Application of DMA
•
•
•
•
DMA has been a built-in feature of PC architecture since the introduction of the original IBM
PC.
PC-based DMA was used for floppy disk I/O in the original PC and for hard disk I/O in later
versions.
PC-based DMA technology, along with high speed bus technology, is driven by data storage,
communications, and graphics needs-all of which require the highest rates of data transfer
between system memory and I/O devices.
Applications areas are: cinemas, theatres, hotels, railway stations, shopping centres,
trade shows, museums & many more.
Explain the different DMA transfer Modes
DMA Transfer Modes
There are 3 different modes of DMA data transfer. They vary by how DMA controller
determines when to transfer data (but actual data transfer process remains the same in all
three cases).
(a) Burst Mode



Entire block of data is transferred in one continuous sequence.
Once the DMA controller is granted access to the system bus by CPU, it transfer all bytes of
data in the data block before relinquishing control of system buses back to the CPU.
This mode is useful for loading programs or data files into memory, but it keeps CPU idle for
relatively long period of time.
(b) Cycle Stealing Mode


DMA controller obtains access to system bus as in burst mode; transfers one byte of data
and returns the control of the system bus to CPU. It continually issues requests using Bus
Request (BR) signals, transferring one byte of data per request, until it has transferred its entire
block of data. (steals one CPU cycle).
The data block is not transferred as quickly as in burst mode, but the CPU is not idled for long
period of time as in burst mode.
(c) Transparent Mode





DMA controller only transfers data when CPU is performing operations that do not use system
buses.
The main advantage of this mode is that CPU never stops executing its program.
The main disadvantages of this mode are
Hardware needed to determine when the CPU is not using the system buses can be quite
complex and relatively expensive.
Requires highest time to transfer a block of data as compared to above two modes.
Explain DMA operation with the help of its block diagram and timing
diagram.
Direct Memory Access Controller & it’s Working
DMA controller is a hardware unit that allows I/O devices to access memory directly without
the participation of the processor. Here, we will discuss the working of the DMA controller.
Below we have the diagram of DMA controller that explains its working:
1. Whenever an I/O device wants to transfer the data to or from memory, it sends the DMA
request (DRQ) to the DMA controller. DMA controller accepts this DRQ and asks the CPU to
hold for a few clock cycles by sending it the Hold request (HLD).
2. CPU receives the Hold request (HLD) from DMA controller and relinquishes the bus and sends
the Hold acknowledgement (HLDA) to DMA controller.
3. After receiving the Hold acknowledgement (HLDA), DMA controller acknowledges I/O
device (DACK) that the data transfer can be performed and DMA controller takes the
charge of the system bus and transfers the data to or from memory.
4. When the data transfer is accomplished, the DMA raise an interrupt to let know the processor
that the task of data transfer is finished and the processor can take control over the bus
again and start processing where it has left.
Now the DMA controller can be a separate unit that is shared by various I/O devices, or it
can also be a part of the I/O device interface.
Direct Memory Access Diagram
After exploring the working of DMA controller, let us discuss the block diagram of the DMA
controller. Below we have a block diagram of DMA controller.
Whenever a processor is requested to read or write a block of data, i.e. transfer a block of
data, it instructs the DMA controller by sending the following information.
1. The first information is whether the data has to be read from memory or the data has to be
written to the memory. It passes this information via read or write control lines that is between
the processor and DMA controllers control logic unit.
2. The processor also provides the starting address of/ for the data block in the memory, from
where the data block in memory has to be read or where the data block has to be written in
memory. DMA controller stores this in its address register. It is also called the starting address
register.
3. The processor also sends the word count, i.e. how many words are to be read or written. It
stores this information in the data count or the word count register.
4. The most important is the address of I/O device that wants to read or write data. This
information is stored in the data register
# Interrupt based I/O is efficient compared to polled I/O". 'Justify this
statement with general working mechanism in both methods.
Polled interrupt:
Polled interrupt are handled using software and are there fores lower compared to
vectored (hardware) interrupts. In this method, there is one common branch address for all
interrupts. The program that takes care of interrupts begins at the branch address and polls the
interrupts sources in sequence. The order in which they are tested determines the priority of
each interrupt. The highest priority source is tested first, and if its interrupt signal is on, control
branches to a servicer outline for this source. Otherwise, the next lower priority source is tested,
and so on. Thus, the initial service routine for all interrupts consists of a program that tests the
interrupt sources in sequence and branches to one of many possible service routines.
Polled interrupts are very simple. But or large number of devices, the time required to poll each
device may exceed the service to the device. In such case, the faster mechanism called chained
interrupt is used.
Chained interrupt:
This is hardware: concept for f handling the multiple interrupts in this technique, the devices are
connected in a chain fashion as shown in figure below for selling up the priority system.
Here the device with the highest priority placed in the first position, followed by lower
priority devices. Suppose that on or more devices interrupt the process or at a time. In response,
the process or saves its current status and then generates an interrupt acknowledge (INTA)
signal to the highest priority device, which is device 1 in our case. If this device has generated
the interrupt it will accept the INTA signal from the processor; otherwise, it will pass INTA on
to the next device until the INTA is accepted by the interrupting device,
Once accepted, the device provides a means to the process or for finding the interrupt address
vector using external hardware. Usually there questing device responds by placing a word on
the data lines. With the help of hardware, it generates interrupts vector address. This word is
referred to as vector, which the process or used as a pointer to the appropriate device service
routine.
This avoids the need to execute a general interrupt service routing first. So this technique
is also referred to as vectored interrupts.
#Differentiate between vectored and non- vectored interrupt. Where
and how 8259 PIC can be used to handle interrupts.
Vectored internet
Non-Vectored internet
Vectored internet is an interrupt in which the address Non- vectored internet is an internet in which the
of the service routine is hardwired.
address of the service routine heads to be supplied
externally by the device.
The address of the subroutine is already known to
the CPU.
The device will have to supply the address of the
subroutine to the microprocessor
In 8085 microprocessor, RIT S.S, RIT 6.5, RST 7.5
and TRAP are vectored interrupts.
In 8085 microprocessor, INTR is non vectored
interrupt.
An interrupt for which the internal hardware
automatically transfer the program control to a
specific memory location is called vectored
interment.
Find the address of theses vectored interrupt is very
easy.
An interrupt for which, an external hardware (e.g.
I/O device) is required to provide address at which
the program control needs to be transfer is called
Non- vectored interrupt
The address in non- vectored interrupt is not predefined.
The INTR is a non -vectored interrupt. Hence when
a device interrupts through INTR, it has to supply
the address of ISR after receiving interrupt
acknowledge signal.
The TRAP, PST 7.5, RST 6.5 and RST 5.5 are
vectored interrupts.
The 8259 Programmable Interrupt Controller
The 8259 A programmable interrupt controller designed to work with Intel microprocessors
8085, 8086 and 8088. The 8259A interrupt controller can
 Manage eight interrupts according to the instructions written into its control registers. This is
equivalent to proving eight interrupt pins on the processor in place of one INTR (8085) pin.
 Vector can interrupt request anywhere in the memory map. However, all eight interrupts are
spaced at the interval of either four or eight locations. This eliminates all the major drawback
of the 8085 interrupts in which all interrupts are vectored to memory locations on page 00H.
 Resolve eight levels of interrupt priorities in a variety of modes, such as fully nested mode,
automatic rotation mode, and specific rotation mode.
 Mask each interrupt request individually.
 Read the status of pending interrupts, in-service interrupts, and masked interrupts.
 Be set up to accept either the level- triggered or the edge -triggered interrupt request.
 Be expanded to 64 priority levels by cascading additional 8259As.
 Be set up to work with either the 8085 microprocessor mode or the 886/8088 microprocessor
mode.
The 8259A is upward- compatible with its predecessor, the 8259. The main difference
between the two is that the 8259 A can be used with Intel's 8086 /88 16-bit
microprocessor. It also includes additional features such as the level- triggered mode,
buffered mode, and automatic- end-of interrupt mode. To simplify the explanation of the
8259A, illustrative examples will not include the cascade mode or the 8086/88 mode and
will be limited to modes continuously used with the 8085.
#What is hardware and software interrupt? Difference between
Hardware Interrupt and Software Interrupt.
1. Hardware Interrupt :
Hardware Interrupt is caused by some hardware device such as request to start an
I/O, a hardware failure or something similar. Hardware interrupts were introduced as a way
to avoid wasting the processor’s valuable time in polling loops, waiting for external events.
For example, when an I/O operation is completed such as reading some data into the
computer from a tape drive.
2. Software Interrupt :
Software Interrupt is invoked by the use of INT instruction. This event immediately
stops execution of the program and passes execution over to the INT handler. The INT
handler is usually a part of the operating system and determines the action to be taken. It
occurs when an application program terminates or requests certain services from the
operating system.
For example, output to the screen, execute file etc.
Difference between Hardware Interrupt and Software Interrupt.
S.N. Hardware Interrupt
Software Interrupt
1
Hardware interrupt is an interrupt
generated from an external device
or hardware.
Software interrupt is the interrupt that is
generated by any internal system of the
computer.
2
It do not increment the program
counter.
It increment the program counter.
3
Hardware interrupt can be invoked
with some external device such as
request to start an I/O or
occurrence of a hardware failure.
Software interrupt can be invoked with
the help of INT instruction.
4
It has lowest priority than software
interrupts
It has highest priority among all interrupts.
S.N. Hardware Interrupt
Software Interrupt
5
Hardware interrupt is triggered by
external hardware and is
considered one of the ways to
communicate with the outside
peripherals, hardware.
Software interrupt is triggered by software
and considered one of the ways to
communicate with kernel or to trigger
system calls, especially during error or
exception handling.
6
It is an asynchronous event.
It is synchronous event.
7
Hardware interrupts can be
classified into two types they are: 1. Software interrupts can be classified into
Maskable Interrupt. 2. Non Maskable two types they are: 1. Normal Interrupts.
Interrupt.
2. Exception
8
Keystroke depressions and mouse
movements are examples of
hardware interrupt.
All system calls are examples of software
interrupts
#What is the Difference Between Maskable and Non Maskable
Interrupt
The main difference between maskable and non maskable interrupt is that a CPU can either disable or
ignore a maskable interrupt, but it is not possible to disable or ignore a non-maskable interrupt by the
instructions of a CPU.
Generally, an interrupt is an event caused by a component other than the CPU. It indicates the CPU of an
external event that requires immediate attention. Furthermore, interrupts occur asynchronously. Maskable and
non-maskable interrupts are two types of interrupts.
S.N.
Maskable Interrupt
Non-Maskable Interrupt
1
Maskable interrupt is a hardware
Interrupt that can be disabled or
ignored by the instructions of CPU.
A non-maskable interrupt is a hardware
interrupt that cannot be disabled or ignored by
the instructions of CPU.
2
When maskable interrupt occur, it
can be handled after executing the
current instruction.
When non-maskable interrupts occur, the
current instructions and status are stored in
stack for the CPU to handle the interrupt.
3
Maskable interrupts help to handle
lower priority tasks.
Non-maskable interrupt help to handle higher
priority tasks such as watchdog timer.
4
Maskable interrupts used to
interface with peripheral device.
Non maskable interrupt used for emergency
purpose e.g power failure, smoke detector etc
.
5
In maskable interrupts, response
time is high.
In non maskable interrupts, response time is
low.
6
It may be vectored or non-vectored.
All are vectored interrupts.
7
Operation can be masked or made
pending.
Operation Cannot be masked or made
pending.
8
RST6.5, RST7.5, and RST5.5 of
8085 are some common examples
of maskable Interrupts.
Trap of 8085 microprocessor is an example
for non-maskable interrupt.
Some Exam Questions:
a. Describe the working mechanism of DMA. Draw the internal architecture of the
8237 DMAC along with a timing diagram illustrating the process of DMA
transfers.
b. Differentiate between vectored and non-vectored interrupts. Where and how
8259 PIC can be used to handle interrupts.
c. What is the importance of interrupt in microprocessor based system? Explain
how interrupt controller(8259) can be used to handle interrupts.
d. What is DMA? Explain DMA data transfer with suitable diagram.
****************************************************
Unit-6
I/O Interface
#Explain the serial and parallel transmission/communication
Serial communication:
Serial communication is the common method of transmitting data between a computer and a peripheral device
such as a programmable instrument or even another computer. In Serial Transmission, data-bit flows from one
computer to another computer in bi- direction. In this transmission one bit flows at one clock pulse. In Serial
Transmission, 8 bits are transferred at a time having a start and stop bit. Serial transmission is used for longdistance communication. The serial port on our PC is a full duplex device.
The main advantages of serial communication are:



It is cost-effective
It is appropriate for long-distance communication.
More reliable
Parallel communication
In data transmission, parallel communication is a method of conveying multiple binary digits
(bits) simultaneously. In Parallel Transmission, many bits( 8 bits) are flow together
simultaneously from one computer to another computer. Parallel Transmission is faster than serial
transmission to transmit the bits. Parallel transmission is used for short distance.
The main advantages of Parallel transmission
 Transmits data at a higher speed.


Suits better for short-distance communication.
Set of bits are transferred simultaneously.
#Differences between Serial And Parallel Transmission
1.
Serial transmission requires a single line to communicate and transfer data whereas, parallel transmission requires multiple lines.
2.
Serial transmission is used for long-distance communication. As against, parallel transmission is used for the shorter distance.
3.
Error and noise are least in serial as compared to parallel transmission. Since one bit follows another in Serial Transmission whereas,
in Parallel Transmission multiple bits are sent together.
4.
Parallel transmission is faster as the data is transmitted using multiples lines. On the contrary, in Serial transmission data flows
through a single wire.
5.
Serial Transmission is full-duplex as the sender can send as well as receive the data. In contrast, Parallel Transmission is half-duplex
since the data is either sent or received.
6.
The special types of converters are required in a serial transmission system to convert the data between the internal parallel form and
serial form while there is no such requirement of converters in parallel transmission systems.
7.
Serial transmission cables are thinner, longer and economical in comparison with the Parallel Transmission cables.
8.
Serial Transmission is simple and reliable. Conversely, Parallel Transmission is unreliable and complicated.
Comparison Chart of
BASIS FOR
COMPARISON
Meaning
SERIAL
TRANSMISSION
Data flows in bidirection, bit by bit
Cost
Economical
Bits transferred at 1 1 bit
clock pulse
PARALLEL
TRANSMISSION
Multiple lines are used to
send data, i.e. 8 bits or 1
byte at a time
Expensive
8 bits or 1 byte
Speed
Slow
Fast
Applications
Used for long-distance
communication.
E.g., Computer to
computer
Only one
Short distance.
E.g., computer to a
printer
Number of
communication
channel required
Need of converters
N number of
communication channels
are needed
Required to convert the Not required
signals according to the
need.
#Discuss synchronous and asynchronous serial data communication
As we know in Serial Transmission data is sent bit by bit, in such a way that each bit follows
another. It is of two types namely, Synchronous and Asynchronous Transmission.
Synchronous Transmission:
In Synchronous Transmission, data is sent in form of blocks or frames. This transmission is the full
duplex type. Between sender and receiver the synchronization is compulsory. In Synchronous
transmission, there is no gap present between data. It is more efficient and more reliable
than asynchronous transmission to transfer the large amount of data.
Asynchronous Transmission:
In Asynchronous Transmission, data is sent in form of byte or character. This transmission is
the half duplex type transmission. In this transmission start bits and stop bits are added with
data. It does not require synchronization.
and Asynchronous Transmission
S.N Synchronous Transmission
#Difference between
Synchronous Transmission
Asynchronous Transmission
1.
In Synchronous transmission, Data is sent
in form of blocks or frames.
In asynchronous transmission, Data is sent in form of
byte or character.
2.
Synchronous transmission is fast.
Asynchronous transmission is slow.
3.
Synchronous transmission is costly.
Asynchronous transmission is economical.
4.
In Synchronous transmission, time
interval of transmission is constant.
In asynchronous transmission, time interval of
transmission is not constant, it is random.
5.
In Synchronous transmission, There is no
gap present between data.
In asynchronous transmission, There is present gap
between data.
Efficient use of transmission line is
done in synchronous transmission.
While in asynchronous transmission,
transmission line remains empty during gap
in character transmission.
Synchronous transmission needs
precisely synchronized clocks for
the information of new bytes.
Asynchronous transmission have no need of
synchronized clocks as parity bit is used in
this transmission for information of new
bytes.
6.
7.
#What are the different ways (method) of parallel data communication? Explain.
1)
Simple I/O


When we need to get digital data from input device, into microprocessor, all we have to do is
connect the switch to an I/O port line and read the port.
Likewise, when we need to output data to simple display device, such as LED, all we have to do
is connect the input of the LED buffer on an output port pin.
Timing diagram of simple I/O
2)
Strobe I/O


In many applications, valid data is present on an external device only at a certain time, so it must
be read in at that time.
E.g. the ASCII-encoded keyboard. When a key is pressed, circuitry on the keyboard sends out
the ASCII code for the pressed key on eight parallel data lines, and then sends out a strobe
signal on another line to indicate that valid data is present on the eight data lines.
Timing diagram of strobe I/O
3)
Single Handshake I/O data transfer.
Timing diagram of single handshake I/O
 The peripheral output some parallel data and sends STB signal to MPU.
 The MPU detects STB signal on a polled or interrupt basis and reads data bytes.
 Then the MP sends on ACK signal to the peripheral to indicate that the data has
been read and the peripheral can send to next byte of data
4)
Double Hand shake I/O data transfer
Timing diagram of single Double handshake I/O




For data transfer where even more coordination is required between the sending
system and the receiving system, a double handshake is used.
The sending (peripheral) device asserts its STB line low to ask the receiving device
whether it is ready or not for data reception.
The receiving system raises its ACK line high to indicate that it is ready.
The peripheral device then sends the byte of data and raises its STB line high to assure
that the valid data is available for the receiving device (MP).
When MP reads the data, it drops its ACK line low to indicate that it has received the
data and requests the sending system to send next byte of data.

#Explain 8251 USART with the help of its neat block diagram.
•
8251 is a USART (Universal Synchronous Asynchronous Receiver Transmitter) for serial
data communication.
•
It acts as a mediator between microprocessor and peripheral to transmit serial data into
parallel form and vice versa.
•
It takes data serially from peripheral (outside devices) and converts into parallel data. After
converting the data into parallel form, it transmits it to the CPU.
•
Similarly, it receives parallel data from microprocessor and converts it into serial form. After
converting data into serial form, it transmits it to outside device (peripheral).
1) Read/Write Control Logic
• The control logic interfaces the chip with the processor, and monitors the data flow. It
controls the overall working by selecting the operation to be done.
2) Data bus buffer
• This block helps in interfacing the internal data bus of 8251 to the system data bus. The data
transmission is possible between 8251 and CPU by the data bus buffer block.
3) Transmit Buffer
• This block is used for parallel to serial converter that receives a parallel byte for conversion
into serial signal and further transmission onto the common channel.
– TXD: It is an output signal, if its value is one, means transmitter will transmit the data.
4) Transmit control
• This block is used to control the data transmission with the help of following pins:
– TXRDY: It means transmitter is ready to transmit data character.
– TXEMPTY: An output signal which indicates that TXEMPTY pin has transmitted all
the data characters and transmitter is empty now.
TXC: An active-low input pin which controls the data transmission rate of transmitted
data.
5) Receive buffer
• This block acts as a buffer for the received data.
– RXD: An input signal which receives the data.
6) Receive control
• This block controls the receiving data.
– RXRDY: An input signal indicates that it is ready to receive the data.
– RXC: An active-low output signal which controls the data transmission rate of
received data.
– SYNDET/BD: An input or output terminal.
7) Modem control (modulator/demodulator)
• A device converts analog signals to digital signals and vice-versa and helps the computers to
communicate over telephone lines or cable wires. The following are active-low pins of
Modem.
- DSR: Data Set Ready signal is an input signal.
- DTR: Data terminal Ready is an output signal.
- CTS: It is an input signal which controls the data transmit circuit.
- RTS: It is an output signal which is used to set the status RTS.
#Explain 8255PPI with the help of a neat block diagram.
•
•
•
•
PPI 8255 is a general purpose programmable I/O device designed to interface the CPU with
its outside world such as keyboard.
We can program it according to the given condition. It can be used with almost any
microprocessor.
It consists of three 8-bit bidirectional I/O ports i.e. PORT A, PORT B and PORT C. We
can assign different ports as input or output functions.
8255A has three ports, i.e., PORT A, PORT B, and PORT C.
– Port A contains one 8-bit output latch/buffer and one 8-bit input buffer.
– Port B is similar to PORT A.
– Port C can be split into two parts, i.e. PORT C lower (PC0-PC3) and PORT C upper
(PC7-PC4) by the control word.
8255A Block Diagram
Fig: Block Diagram of 8255A PPI
•
•
•
•
•
It consists of 40 pins and operates in +5V regulated power supply.
Port C is further divided into two 4-bit ports i.e. port C lower and port C upper and port C can
work in either BSR (bit set rest) mode or in mode 0 of input-output mode of 8255.
Port B can work in either mode or in mode 1 of input-output mode.
Port A can work either in mode 0, mode 1 or mode 2 of input-output mode.
It has two control groups, control group A and control group B. Control group A consist of
port A and port C upper. Control group B consists of port C lower and port B.
#Explain the Operating modes of 8255A /Explain Bit set reset (BSR) mode &
Input/output Mode
1) Bit set reset (BSR) mode :
•
•
If MSB of control word (D7) is 0, PPI works in BSR mode. In this mode only port C bits are
used for set or reset.
The contents of the control register are called the control word that specifies the input/
output functions of each port.
2) Input/output Mode
There are three types of the input/output mode. They are as follows:
Mode 0
•
In this mode all the three ports (port A, B, C) can work as simple input function or simple
output function. In this mode there is no interrupt handling capacity.
Mode 1
•
•
In this mode either port A or port B can work as simple input port or simple output port, and
port C bits are used for handshake signals before actual data transmission. It has interrupt
handling capacity.
Example: A CPU wants to transfer data to a printer. In this case since speed of processor is
very fast as compared to relatively slow printer, so before actual data transfer it will send
handshake signals to the printer for synchronization of the speed of the CPU and the
peripherals.
Mode 2
•
Bi-directional data bus mode. In this mode only port A works, and port B can work either in
mode 0 or mode 1. 6 bits ports C are used as handshake signals. It also has interrupt handling
capacity.
#What is RS 232 interface? Explain with DTE and DCE.
RS232 is a standard protocol used for serial communication, it is used for connecting computer
and its peripheral devices to allow serial data exchange between them. In simple terms RS232
defines the voltage for the path used for data exchange between the devices. It specifies
common voltage and signal level, common pin wire configuration and minimum, amount of
control signals.
Fig: RS-232

DTE - A DTE stands for data terminal equipment is an end instrument that convert user
information into signals or reconverts the receive signal. A male connector is used in DTE and
has pin out configuration.

DCE - A DCE stands for data communication equipment's. It sits between the DTE and data
transmission circuit for example modem. A DCE device uses a female connector which has
holes on the surface to hold male connector.
#How RS232 Works? When it Interconnection between DTE-DCE and its application
•
•
•
•
RS232 works on the two-way communication that exchanges data to one another. There are
two devices connected to each other, (DTE) Data Transmission Equipment& (DCE) Data
Communication Equipment which has the pins like TXD, RXD, and RTS & CTS.
Now, from DTE source, the RTS generates the request to send the data. Then from the other
side DCE, the CTS, clears the path for receiving the data.
After clearing a path, it will give a signal to RTS of the DTE source to send the signal. Then
the bits are transmitted from DTE to DCE.
Now again from DCE source, the request can be generated by RTS and CTS of DTE
sources clears the path for receiving the data and gives a signal to send the data.
•
This is the whole process through which data transmission takes place.
Application of RS-232
•
•
•
RS232 serial communication is used in old generation PCs for connecting the peripheral
devices like mouse, printers, modem, scanner etc.
Nowadays, RS232 is replaced by advanced USB.
It is still used by some microcontroller boards, receipt printers, point of sale system (PoS), etc.
#Draw the RS-232 Pin Configuration – 9 pin MALE Connector
The most commonly used type of serial cable connectors is 9-pin connectors DB9 and 25-pin connector DB-25.
Each of them may be a male or female type. Nowadays most of the computers use the DB9 connector for
asynchronous data exchange. The maximum length of the RS-232 cable is 50ft.
New RS232 has nine pins as mentioned earlier. These nine pins are arranged in the port as shown in RS232
Connector Pin out. The DCE and DTE ports are exactly similar except for the direction of data flow. These nine
pins are roughly divided in to three categories and we will discuss each category below.
Pin Number Pin Name Description
DATA pins (Data flow takes through these pins)
2
RXD
Receive Data (Data is received though this pin)
3
TXD
Transmit Data (Data is transmitted through this pin)
CONTROL pins (These pins are for establishing interface and to avoid data loss)
1
CD
Carrier Detect(Set by MODEM when answer is received by remote MODEM )
4
DTR
Data Terminal Ready(Set by PC to prepare MODEM to be connected to telephone
circuit)
6
DSR
Data Set Ready(Set by MODEM to tell PC it is ready to receive and send data)
7
RTS
Request To Send(Set by PC to tell MODEM that MODEM can begin sending data)
8
CTS
Clear To send(Set by MODEM to tell PC that it is ready to receive data)
9
RI
Set by MODEM to tell PC a ringing condition has been detected.
GND
Ground (Used as reference for all pin voltage pulses)
REFERENCE
5
#Explain the RS 232 PIN description
It is a 25-pin connector, each pin has its function is as follows.
PIN 1: (Protective Ground); It is a ground Pin.
PIN 2: Transmit Data.
PIN 3: Receive Data.
PIN 2 & PIN 3: These pins are the most important pins for data transmitting and receiving. The 1 & 2-pins are used to
data transmission and pin-3 used to data receiving purpose.
PIN 4: Request to send.
Pin 5: Clear to send.
PIN 6: Data Set Ready.
PIN 20: Data terminal Ready.
PIN 4, PIN 5, PIN 6, PIN 20: These pins are the handshaking pins(flow of control). Normally terminals cannot transmit
the data until clear to send transmission is received from the DCE.
PIN 7: This pin is the common reference for all signals, including data, timing, and control signals. The DCE and DTE
work properly across the serial interface and the pin-7 must be connected both ends without interface would not work.
PIN 8: This pin is also known as received line signal detector carrier detect. This signal is activated when a suitable
carrier is established between the local and remote DCE devices.
PIN9: This pin is a DTE serial connector, this signal follows the incoming ring to an extent. Normally this signal is used
by DCE auto-answer mode.
PIN 10: Test Pin.
PIN 11: standby select.
PIN 12: Data Carrier Detect.
PIN 13: Clear to send.
PIN 14: Transmit data.
PIN 15: Transmit clock.
PIN 17: Receive clock.
PIN 24: External Clock.
PIN 15, 17, 24; Synchronous modems use the signals on these pins. These pins are controlled bit timing.
PIN 16: Receive data.
PIN 18: Test Pin.
PIN 19: Request to send.
PIN 21: (Signal Quality Detector); This pin Indicates the quality of the received carrier signal because the transmitting
modem must be sent 0 or either 1 at each bit time, the modem controls the timing of the bits from the DTE.
PIN 22: (Ring Indicator): The ringing indicator means the DCE informs the DTE that the phone is ringing. All the
modems designed for directly connected to the phone network equipped with the auto-answer.
PIN 23: Data Signal Rate Detector
Exam Questions:
1) How DTE and DCE are wired using RS 232 cable? Explain the process of double
handshaking I/O.
2) Explain the Operating modes of 8255A /Explain Bit set reset (BSR) mode & Input/output
Mode
3) What are the different ways (method) of parallel data communication? Explain.
4) Difference between Synchronous Transmission and Asynchronous Transmission
******************Good Luck**********************
Unit-7
Advance Microprocessor
#Define 80286 Microprocessor? Explain the features of 80286 Microprocessor.
80286 Microprocessor is a 16-bit microprocessor that has the ability to execute 16-bit
instruction at a time. It has non-multiplexed data and address bus. The size of data bus is 16bit whereas the size of address bus is 24-bit.It was invented in February 1982 by Intel. 80286
microprocessor was basically an advancement of 8086 microprocessor. Further in 1985, Intel
produced upgraded version of 80286 which was a 32-bit microprocessor.
Features of 80286 Microprocessor
 The Intel 80286 is a high-performance 16-bit microprocessor.
 It has been specially designed for multiuser and multitasking systems.
 Various versions of 80286 are available that run on 12.5 MHz,10 MHz and 8MHz clock
frequencies.
 80286 is upwardly compatible with 8086 in terms of instruction set. (That is the
8086,8088,80186,80286 CPU family all contain the same instruction set)
 The memory management which is an important task of the operating system is now
supported by a hardware unit called memory management unit.
 The 80286 is the first CPU to incorporate the integrated memory management unit.
 It has four-level memory protection and support for virtual memory and operating
system
 It is available in variety of pin packages such as 68-pin PLCC (Plastic Leaded Chip
Carrier), Ceramic LCC (Leadless Chip Carrier), and PGA(Pin Grid Array).
 It has 24 address lines and 16 data lines.  There are two operating modes for 80286
 The real address mode
 The protected virtual memory address mode
 In real address mode the processor can address up to 1MB of physical memory.
 The virtual address mode is for multiuser/multitasking system. In this mode of operation
the memory management unit can manage up to 1GB of virtual memory.
 In virtual address mode one user cannot interface with the other. Also users cannot
interface with operating system. These features are called protection
#Write some advantage of 80286 Microprocessor over 8086 Microprocessor.
80286 more advantageous than 8086 microprocessor are

It has non-multiplexed address and data bus that reduces operational speed.

The addressable memory in case of 80286 is 16 MB.

It offers an additional adder for address calculation.

80286 has faster multipliers that lead to quick operation.

The performance per clock cycle of 80286 is almost twice when compared with 8086 or
8088.

80286 in PVAM can address up to 8192 virtual memory segment of 64k bytes each.

The 80286 then has a virtual address space of 1 Gigabyte
#Explain the mode of Operating modes of 80286 microprocessor Operating Modes of
80286
Real Address Mode
•
•
•
80286 just act as a faster version of 8086.
And program for 8086 can be executed without modification in 80286.
In real address mode the processor can address up to 1 MB of physical memory.
Protected Virtual Address Mode
•
80286 supports multitasking because multiple programs can be executed using virtual
memory.
•
Able to run several program at the same time
•
Able to protect memory space for another program
•
In this mode the processor can address up to 16 MB of physical memory whereas 8086 can
address only 1 MB.
•
In this mode the processor can address up to 1 GB of virtual memory.
•
80286 can treat external storage as it were physical memory and execute programs that are too
large to be contained in physical memory.
As using virtual memory, space for other programs can be saved. Sometimes bulky
programs also do exist that cannot be stored in physical memory, so virtual memory is
utilized in order to execute large programs. This mode is used in 80286, so that in case of
memory failure in real address mode, it can stay in protected manner.
#Write the difference between Real Address Mode and Protected Virtual Address
Mode
Real Address Mode
Can only address 1MB of system
memory and act as fast 8086
Doesn't supports the concept of virtual
memory.
Real mode provides not support for
memory protection, multitasking, or code
privilege levels.
Initially every processor is in Real Mode
i.e MSW PE= 0
Protected Virtual Address Mode
Can address till 16MB of system memory
Supports the concept of virtual memory
Protected mode provides support for
memory protection, multitasking, or code
privilege levels.
Microprocessor will switch to this mode
by setting MSW PE- bit
80286 and explain the functional unit of its.
#Dra
w the
Microp
rocesso
r of
The CPU, central processing unit of 80286 microprocessor, consists of 4 functional block:




Address Unit
Bus Unit
Instruction Unit
Execution Unit
Internal Block Diagram of 80286  The CPU may be viewed to contain four functional parts,
viz.
(a) Address Unit (AU)
(b) Bus Unit (BU)
(c) Instruction Set (IU)
(d) Execution Unit (EU)
Address unit
Calculate the physical addresses of the instruction and data that the CPU want to access
•Address lines derived by this unit may be used to address different peripherals.
•Physical address computed by the address unit is handed over to the BUS unit.
Bus Interface Unit
•Performs all memory and I/O read and write operations.
•Take care of communication between CPU and a coprocessor.
•Transmit the physical address over address bus A0– A23.
•Prefetcher module in the bus unit performs this task of prefetching.
•Bus controller controls the prefetcher module.
•Fetched instructions are arranged in a 6 – byte prefetch queue.
Instruction Unit
•Receive arranged instructions from 6 byte prefetch queue.
•Instruction decoder decodes up to 3 prefetched instruction and are latched them onto a
decoded instruction queue.
•Output of the decoding circuit drives a control circuit in the Execution unit.
Execution unit
•EU executes the instructions received from the decoded instruction queue sequentially.
•Contains Register Bank.
•contains one additional special register called Machine status word (MSW) register --- lower
4 bits are only used.
•ALU is the heart of execution unit.
•After execution ALU sends the result either over data bus or back to the register bank.
Or
The Address Unit (AU) is responsible for calculating the physical address of instructions and
data that CPU wants to access.
This physical address computed by the address unit is handed over to the Bus Unit (BU) of
the CPU.
The address latches and drivers in the bus unit transmit the physical address thus formed over
the address bus A0-A23.
One of the major function of the bus unit is to fetch instruction bytes from the memory.
The Instruction Unit(IU) accepts instructions from the prefetch queue and an instruction
decoder decodes them one by one.  The output from the decoding circuit drives a control
circuit in the Execution Unit (EU) is responsible for instructions received from the decoded
instruction queue, which sends the data part of the instruction over the data bus.
#Explain the register used in 80286
The 80286 CPU contains almost the same set of registers, as in 8086
(a) Eight 16-bit general purpose registers
(b) Four 16-bit segment registers
(c) Status and control register
(d) Instruction Register
The flag register bits D0, D2, D4, D6, D7 and D11 are modified according to the result of the execution of logical and
arithmetic instructions. These are called status flag bits.
The 80286 CPU contains almost the same set of registers, as in 8086
(a) Eight 16-bit general purpose registers
(b) Four 16-bit segment registers
(c) Status and control register
(d) Instruction Register
The flag register bits D0, D2, D4, D6, D7 and D11are modified according to the result of the execution
of logical and arithmetic instructions. These are called status flag bits.
The additional fields available in 80286 flag registers are,
IOPL-I/O Privilege Field (bits D12 and D13)
NT - Nested Task flag (bit D14)
PE - Protection Enable (bit D16)
MP – Monitor Processor Extension (bit D17)
Processor Extension Evaluator (bit D19)
Machine Status Flag (MSW)
The machine status word consists of four flags.
o
o
These are – PE,MP,EM, and TS of the four lower order bits D19 to D16 of the upper word of the flag
register.
The LMSW and SMSW instructions are available in the instruction set of 80286 to write and read the
MSW in real address mode.
#Explain Privilege level of 80286 Microprocessor
There are four types of privilege levels
1.
00 - kernel level (highest privilege level)
2.
01 - OS services
3.
10 - OS extensions
4.
11 - Applications (lowest privilege level)
Figure: Privilege Level
-
-
-
Each task assigned a privilege level, which indicates the priority or privilege of
that task.
It can only changed by transferring the control, using gate descriptors, to a
new segment.
A task executing at level 0, the most privileged level, can access all the
data segment defined in GDT and LDT of the task.
-
A task executing at level 3, the least privileged level, will have the most
limited access to data and other descriptors.
-
-
The use of rings allows for system software to restrict tasks from accessing
data.
In most environments, the operating system and some device drivers run in
ring 0 and applications run in ring 3.
#Explain LDT, GDT and IDT. Differentiate LDT and GDT
Global Descriptor Table (GDT):
-
The 80286 has a single Global Descriptor Table (GDT) which is shared
between all tasks and addresses up to 512MB of the virtual address space.
-
The Global Descriptor Table or GDT is a data structure used by Intel x86family
processors
starting
with
the
80286
in
order
characteristics of the various memory areas used
to
define
the
during program
execution, including the base address, the size and access privileges like
execute- ability and write-ability.
Local Descriptor Table (LDT):
-
Each task will have its own Local Descriptor Table (LDT) which is a private
512MB of address space.
-
LDT is essential to implement separate address spaces for multiple processes.
-
The operating system will switch the current LDT when scheduling a new
process, using the LDT machine instruction.
Descriptor Table (LDT):
IDT used to store interrupt gates and task gate
LIDT instruction is used to Load Interrupt Descriptor table.
Differentiate LDT and GDT:
-
-
LDT is actually defined by a descriptor inside the GDT, while the GDT is
directly defined by a linear address.
-
The lack of symmetry between both tables is underlined by the fact that the
current LDT can be automatically switched on certain events, notably if TSSbased multitasking is used, while this is not possible for the GDT.
-
The LDT also cannot store certain privileged types of memory segments.
-
The LDT is the sibling of the Global Descriptor Table (GDT) and similarly
defines up to 8191 memory segments accessible to programs.
-
-
LDT (and GDT) entries which point to identical memory areas are called
aliases.
Instruction to load GDT is LGDT(Load Global Descriptor Table) and
instruction to load LDT is LLDT(Load Global Descriptor Table). Both are
privileged instructions.
#Write the Features of 80386 Microprocessor
Features of 80386 Microprocessor
The 80386 microprocessor is an enhanced version of the 80286 microprocessor
Memory-management unit is enhanced to provide memory paging.
The 80386 also includes 32-bit extended registers and a 32-bit address and data bus.
These extended registers include EAX, EBX, ECX, EDX, EBP, ESP, EDI, ESI, EIP and EFLAGS.
The 80386 has a physical memory size of 4GBytes that can be addressed as a virtual memory with
up to 64TBytes.
The 80386 is operated in the pipelined mode, it sends the address of the next instruction or
memory data to the memory system prior to completing the execution of the current instruction
This allows the memory system to begin fetching the next instruction or data before the current is
completed. This increases access time.
The instruction set of the 80386 is enhanced to include instructions that address the 32-bit
extended register set.
The 80386 memory manager is similar to the 80286, except the physical addresses generated by
the MMU are 32 bits wide instead of 24-bits.
The concept of paging is introduced in 80386
80386 support three operating modes:
 Real Mode(default)
 Protected Virtual Address Mode (PVAM)
 Virtual Mode
The memory management section of 80386 supports virtual memory, paging and four levels of
protection.
The 80386 includes special hardware for task switching
#Explain the architecture of the80386 with a neat block diagram.
The internal architecture of the 80386 includes six functional units that operate in parallel. The
parallel operation is called as pipeline processing.
Fetching, decoding execution, memory management, and bus access for
several instructions are performed simultaneously.
The six functional units of the 80386 are
1.Bus Interface Unit
2.Code Pre-fetch Unit
3.Instruction Decoder Unit
4.Execution Unit
5.Segmentation Unit
6.Paging Unit
-
The Bus Interface Unit connects the 80386 with memory and I/O. Based on internal
requests for fetching instructions and transferring data from the code pre-fetch unit,
the 80386 generates the address, data and control signals for the current bus
cycles.
-
The code pre-fetch unit pre-fetches instructions when the bus interface unit is not
executing the bus cycles. It then stores them in a 16-byte instruction queue for
decoding by the instruction decode unit.
-
The instruction decode unit translates instructions from the pre-fetch queue into
micro-codes. The decoded instructions are then stored in an instruction queue
(FIFO) for processing by the execution unit.
-
The execution unit processes the instructions from the instruction queue. It contains
a control unit, a data unit and a protection test unit.
-
The control unit contains microcode and parallel hardware for fast multiply, divide
and effective address calculation. The unit includes a 32-bit ALU, 8 general purpose
registers and a 64-bit barrel shifter for performing multiple bit shifts in one clock. The
data unit carries out data operations requested by the control unit.
-
-
The protection test unit checks for segmentation violations under the control of
microcode.
The segmentation unit calculates and translates the logical address into linear
addresses at the request of the execution unit.
The translated linear address is sent to the paging unit. Upon enabling the paging
-
mechanism, the 80386 translates these linear addresses into physical addresses. If
paging is not enabled, the physical address is identical to the linear address and no
translation is necessary.
#Explain Register organization of 80386
The Register organization of 80386 is as follows:
Figure:80386 General Purpose, Index and Pointer Register
General Purpose Register

Registers EAX, EBX, ECX, EDX, EBP, EDI and ESI are regarded as general purpose or
multipurpose registers.
- EAX
(ACCUMULATOR): The accumulator is used for instructions such as
multiplication, division and some of the adjustment instructions. In 80386 and
above, the EAX register may also hold the offset address of a location in memory
system.
- EBX (BASE INDEX): This can hold the offset address of a location in the memory
system in all version of the microprocessor. It the 80386 and above EBX also can
address memory data.
- ECX (count): This acts as a counter for various instructions.
- EDX
(data): EDX is a general-purpose registers that holds a part of the result for
multiplication or part of the division. In the 80386 and above this register can also
address memory data.
Pointer and Index Register
- EBP
(Base Pointer): EBP points to a memory location in all version of the
microprocessor for memory data transfers.
- ESP (Stack Pointer): ESP addresses an area of memory called the stack. The stack
memory is a data LIFO data structure. The register is referred to as SP if used in 16
bit mode and ESP if referred to as a 32 bit register.
- EDI (Destination index): EDI often addresses string destination data for the string
instruction. It also functions as either a 32-bit (EDI) or 16-bit (DI) general-purpose
register.
- ESI (Source index): ESI can either be used as ESI or SI. It is often used to the
address source string data for the string instructions. Like EDI ESI also functions as a
general-purpose registers.
80386 Segment Register
- CS
(Code): The code segment is a section of memory that holds the code used
by the microprocessor. The code segment registers defines the starting address
of the section of memory holding code.
- SS (Stack): The stack segment defines the area of memory used for the stack. The
stack entry point is determined by the stack segment and stack pointer registers.
The BP registers also addresses data within the stack segment.
- DS (Data) – The data section contains most data used by a program. Data are
accessed in the data segment by an offset address of the contests of other
registers that hold the offset address.
- ES (extra) – The extra segment is used to hold information about string transfer and
manipulation
- FS
and GS – These are supplement segment registers available in the 80386 and
above microprocessors to allow two additional memory segments for access by
programs.
EIP (Instruction Pointer):
EIP addresses the next instruction in a section of memory defined as a code segment. This register is IP
(16bit) when microprocessor operates in the real mode and EIP (32 bits) when 80386 and above operate
in protected mode
Figure:80386 Instruction Pointer and Flag Register
Flag Register:
Indicates the condition of the microprocessor and controls its operations. Flag
registers are also upward compatible since the 8086-80268 have 16bit registers and
the 80386 and above have EGLAF register (32 bits)
Figure: 80386 Flag Register
-
-
-
-
-
IOPL (I/O Privilege level): IOPL is used in protected mode operation to
select the privilege level for I./O devices. IF the current privilege level is
higher or more trusted than the IOPL, I/O executed without hindrance. If
the IOPL is lover than the current privilege level, an interrupt occurs,
causing execution to suspend. Note that an IPOL is 00 is the highest or
more trusted; if IOPL is 11, it’s the lowest or least trusted.
NT (Nested Task): The nested task flag is used to indicate that the current
task is nested within another task in protected mode operation. This flag is
when the task I nested by software.
RF (Resume): The resume flag is used with debugging to control the
resumption of execution after the next instruction.
VM (Virtual Mode): The VM flag bit selects virtual mode operation in a
protected mode system.
Note: All the other flag bit is having similar description as in 8086 flag
register.
System Address Register:
Four memory management registers are used to specify the locations of data
structures which control segmented memory management.
-
GDTR (Global Descriptor Table Register) and IDTR (Interrupt Descriptor
Table Register) be loaded with instructions which get a 6 byte data item
from memory
-LDTR (Local Descriptor Table Register) and TR (Task Register) can be
loaded with instructions which take a 16-bit segment selector as an
operand.
Special 80386 Register
-
Control Register: Four Control Register (CR0-CR3)
-
Debug Register: Eight Debug Register (DR0-DR7)
-
Test Register: Two Test Register (TR6-TR7)
#Explain the concept of paging in 80386 Microprocessor
Paging Operation: Paging is one of the memory management techniques
used for virtual memory multitasking operating
•The segmentation scheme may divide the physical memory into a variable
size segments but the paging divides the memory into a fixed size pages.
•The segments are supposed to be the logical segments of the program,
but the pages do not have any logical relation with the program.
•The pages are just fixed size portions of the program module or data.
system.
The advantage of paging scheme is that the complete segment of a task
need not be in the physical memory at any time.
•Only a few pages of the segments, which are required currently for the
execution need to be available in the physical memory. Thus the memory
requirement of the task is substantially reduced, relinquishing the available
memory for other tasks.
•Whenever the other pages of task are required for execution, they may be
fetched from the secondary storage.
•The previous page which are executed, need not be available in the
memory, and hence the space occupied by them may be relinquished for
other tasks.
Thus paging mechanism provides an effective technique to manage the
physical memory for multitasking systems.
Paging Unit:
The paging unit of 80386 uses a two level table mechanism to convert a
linear address provided by segmentation unit into physical addresses. The
paging unit converts the complete map of a task into pages, each of size
4K. The task is further handled in terms of its page, rather than segments. The
paging unit handles every task in terms of three components namely page
directory, page tables and page itself.
Paging Descriptor Base Register:
The control register CR2 is used to store the 32-bit linear address at which the
previous page fault was detected. The CR3 is used as page directory
physical base address register, to store the physical starting address of the
page directory. The lower 12 bit of the CR3 are always zero to ensure the
page size aligned directory. A move operation to CR3 automatically loads
the page table entry caches and a task switch operation, to load CR0
suitably.
Page Directory :
This is at the most 4Kbytes in size. Each directory entry is of 4 bytes,thus a
total of 1024 entries are allowed in a directory. The upper 10 bits of the linear
address are used as an index to the corresponding page directory entry.
The page directory entries point to page tables.
•Page Tables:
Each page table is of 4Kbytes in size and many contain a maximum of 1024
entries. The page table entries contain the starting address of the page and
the statistical information about the page. •The upper 20 bit page frame
address is combined with the lower 12 bit of the linear address. The address
bits A12- A21 are used to select the 1024 page table entries. The page table
can be shared between the tasks.
 The P bit of the above entries indicate, if the entry can be used in
address translation.
 If P=1, the entry can be used in address translation, otherwise it cannot
be used.
 The P bit of the currently executed page is always high.
 The accessed bit A is set by 80386 before any access to the page. If
A=1, the page is accessed, else unaccessed.
 The D bit ( Dirty bit) is set before a write operation to the page is
carried out. The D-bit is undefined for page director entries.
 The OS reserved bits are defined by the operating system software.
 The User / Supervisor (U/S) bit and read/write bit are used to provide
protection. These bits are decoded to provide protection under the 4
level protection model.
 The level 0 is supposed to have the highest privilege, while the level 3 is
supposed to have the least privilege.
 This protection provide by the paging unit is transparent to the segmentation unit.
Exam Questions:
o
o
o
o
Explain the architecture of the80386 with a neat block diagram.
Explain Register organization of 80386 microprocessor
Explain the architecture of the80386 with a neat block diagram
Explain the concept of paging in 80386 Microprocessor
*****************************
Tribhuwan University Institute of Science and Technology
Bachelor Level / Second-semester
SUBJECT: Microprocessor
Level: Bsc. CSIT (Second Semester)
F.M:60
Model Question Set-1
Long answer questions: (Any two)
Group A
1. Draw pin diagram of 8085 microprocessor with appropriate labeling.
2. What is machine cycle, T- state and instruction cycle? Draw a timing diagram for
STA 2000h memory instruction (choose any memory locations for loading STA 2000h
instructions.
3. Write an assembly language program to find the greatest number in an array in
using 8 bit microprocessor (Assume appropriate array data and address where
minimum assay size 20 should be considered)
Short answer the questions (Any Eight)
1) Discuss the bus system in 8085 microprocessor.
2) What is flag? Explain the flags that are present in 8086 microprocessor.
3) Draw a neat diagram of 8237 DMA controller and explain it.
4) What is descriptor? What is its use? Differentiate between GTD and LTD.
5) Differentiate between memory mapped I/O and IO mapped IO.
6) Differentiate between push and pop Instruction with example illustrating the use of
these instruction.
7) Draw and explain the timing diagram for the execution of the instruction MVI A, 32H
8) Write and explain assembly language program to multiple 05H and 06 H.
9) Explain the function of following signals
a. ALE
b. INTR
c. TRAP
*****Best of Luck ******
Tribhuwan University Institute of Science and Technology
Bachelor Level / Second-semester
SUBJECT: Microprocessor
Level: Bsc. CSIT (Second Semester)
F.M:60
Model Question Set-2
Long answer questions: (Any two)
Group A
1) Draw the block diagram of 8086 microprocessor and explain its functional units.
2) What is addressing mode? Explain the different types of addressing mode used in
8085 microprocessor.
3) Explain the Instruction set of 8085 Microprocessor. Write an ALP for 8086 to read a
string and display the string in uppercase.
Short answer the questions (Any Eight)
1) Draw differentiate between Von Neumann and Harvard Architect.
2) What is segmented Memory? List out the advantages and disadvantage of
segmentation.
3) Draw a timing diagram of instruction LDA 3000H and explain it.
4) Explain 8259 PIC with the help of its block diagram.
5) Explain the register organization of 80386 microprocessor.
6) How DTE and DCE are wired using Rs-232 cable. Explain the process of double
handshake I/O..
7) Explain the method was of parallel data transfer.
8) Differentiate between vectored and non-vectored interrupts. Where and how 8259
PIC can be used to handle interrupts.
9) What are different operating mode in 80286 Microprocessor? Explain in brief about
each mode
*****Best of Luck ******
Tribhuwan University Institute of Science and Technology
Bachelor Level / Second-semester
SUBJECT: Microprocessor
Level: Bsc. CSIT (Second Semester)
F.M:60
Model Question Set-3
Long answer questions: (Any two)
Group A
1. Draw logical block diagram or 80286 microprocessor and explain its functional unit.
2. What is addressing mode? Explain different addressing mode in 8085
microprocessor.
3. Explain 8255 PP1 with the help of a neat block diagram.
4. Write a assembly language program to find the smallest number in a array using bit
microprocessor (Assume appropriate array. data and address where minimum array
size of 15 should be consider.
Short answer the questions (Any Eight)
1) Explain the operation of the basic microprocessor using block diagram.
2) What is pipeline? Explain Instruction pipeline in brief.
3) Draw a timing diagram of instruction MOV A, 32 H and explain it.
4) Discuss DMA with the help of its advantages and application.
5) Explain the concept of paging in 80386 microprocessor.
6) What are the differences between parallel and serial communication? Explain RS
232 interface.
7) Write an ALP for 8086 to reed a string and display the string in uppercase.
8) Write an assembly language program for 8086 microprocessor to display "Computer
Science and Information Technology" .
9) Write short note on :
a) Macro Assembler
b) BSR Mode
*****Best of Luck ******
Tribhuwan University Institute of Science and Technology
Bachelor Level / Second-semester
SUBJECT: Microprocessor
Level: Bsc. CSIT (Second Semester)
F.M:60
Model Question Set-4
Long answer questions: (Any two)
Group A
1) Draw and explain the functional block diagram of 8085 microprocessor.
2) Explain the addressing mode of 8086 Microprocessor
3) Write a program in 8-bit Microprocessor to multiply two 16 bits numbers (ABCDh and
1234h) and store in the memory location starting from 3000h.
Short answer the questions (Any Eight)
1) Describe various components of CPU with suitable diagram.
2) Make distinction between instruction and directives. Explain with examples.
3) Write 8086 program to input a upper case character from keyboard and display it in
lowercase.
4) Sketch and explain in RS 232 9 pin connection.
5) Describe various methods of parallel communication.
6) Describe the various addressing modes of 8086 microprocessor.
7) Write an assembly language program to read string from keyboard and display in
reverse order
8) Draw a block diagram of 8255 PPI and explain.
9) Write short notes on:
a) Double Handshaking
b) RS-232 serial connector
*****Best of Luck ******