2018 IEEE 68th Electronic Components and Technology Conference
Backward Compatible Connectors for Next Generation PCIe Electrical I/O
Lei Shan, Daniel Freidman
Craig Kennedy, Warren Persak, Kevin Lau
T. J. Watson Research Center, IBM Corporation
Yorktown Heights, New York
leis@us.ibm.com
Amphenol Corporation
Nashua, New Hampshire
craig.kennedy@amphenol-tcs.com
Abstract— A backward compatible PCIe connector targeting
25-32Gb/s per-channel data rates was jointly developed under
a collaboration between IBM Research and Amphenol
Corporation. To demonstrate the improvement on
loss/reflection/crosstalk, an evaluation board with both original
and new PCIe connector footprints was designed, fabricated,
and tested. 3D full-wave simulations were performed and
correlated with measurement results. Optimal pad and ground
configurations were used to update PCIe channel
budget/specifications and provide design recommendations for
potential PCIe Gen5 channels.
on loss/reflection/crosstalk over the existing PCIe connector
(v3.0), an evaluation board and matching PCIe daughter
cards were designed and fabricated. Landing pads, contact
pads, and signal/ground via configurations were optimized
and implemented in the designs for hardware-level direct
comparisons at data rates up to 32Gbps. Microwave probe
launches on both top and bottom layers of the evaluation
board were adopted to save space and minimize the negative
effects of test fixtures. An Agilent E8364C 4-port 50GHz
network analyzer was used for all passive channel
measurements, and the results were correlated with 3D fullwave simulations. Inverse FFT of the frequency-domain
results was performed to create time-domain reflectometer
plots to identify major impedance discontinuities. Timedomain bit-to-bit eye-diagram simulations were also
performed. In this paper, the above work is described,
results summarized for updated PCIe channel
budget/specifications, and design recommendations s for 2532Gbps/channel electrical interconnects are presented.
Keywords-PCIe Gen5; Backward compatible; 32Gbps.
I. INTRODUCTION
System performance has been closely associated with
microelectronics evolution in the past five decades. As
semiconductor fabrication feature size approaches its
fundamental limits, package-level integration is emerging as
a substitution for future system scaling, which in turn highly
depends on I/O bandwidth [1].
Since originally introduced in 2003, PCI Express (PCIe)
has evolved through three generations, from the original
2.5Gbps to 5Gbps (v2.0) to 8Gbps (v3.0). Recently, the
industry has been seeking solutions to further extend the
PCIe I/O standard to a fourth generation at 16Gbps (v4.0)
and potentially a fifth generation at 25-32Gbps (v5.0) to
address ever increasing system bandwidth demand [2]. At
25Gbps and above, signal integrity becomes a major hurdle,
as the connector design has been unchanged since it was
originally introduced for much lower operating speeds, i.e.
2.5Gbps. In particular, the contact design causes not only
impedance variation along the signal path but also
destructive standing-wave resonances due to pin “stubs” and
discontinuities of the connector structure.
As such,
researchers are exploring alternative connector designs and
even considering optical PCIe substitutions [3]. However,
these alternative solutions are not backward compatible with
existing footprint and daughter card designs, and therefore
tend to elevate the cost of PCIe implementations.
In this work, IBM Research collaborated with Amphenol
Corporation to jointly develop a backward compatible PCIe
connector to achieve 25-32Gbps/channel signaling, aiming
at a cost-effective card-edge connection for smooth boardto-board transitions. To demonstrate potential improvement
2377-5726/18/$31.00 ©2018 IEEE
DOI 10.1109/ECTC.2018.00270
II. CONNECTOR OPTIMIZATION
There are numerous research and development activities
related to 25-32Gbps electrical card-edge connectors and
standards, however, most propose new mechanisms and/or
standards that are not compatible with the existing PCIe
channels and result in cost increase and design difficulties.
In this work, backward compatibility is a top priority,
together with impedance control and resonance removal. In
particularly, the contact fingers are optimized in the
following three areas as depicted in Figure 1:
(1) Thinner and shorter pin head to reduce pin stub beyond
contact point; (2) wider pin body for better impedance
control (targeting 85ohm differential); (3) slightly longer pin
neck to improve signal transition from landing pads to pin
body.
Figure 1. Contact finger optimization
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Mechanically, the new PCIe connector comes in two
versions, i.e. “standard” and “slim” as shown in Figure 2.
The “standard” version is fully backward compatible and
may be used as a drop-in replacement for the existing PCIe
Gen3 connector. The “slim” version bears a narrower body
design for high density applications. Both come with the
convex ridge removed, which not only saves on-board
space, but also enables straight vertical Automated Optical
Inspection (AOI). Figure 3 shows an image of the new PCIe
x16 connector.
individual channel is 25mm, through lines with and without
transition vias are also placed on the board for impedance
check and de-embedding purposes. The total board
thickness of about 1.6mm is chosen such that PCIe daughter
cards may also be added to the evaluation board and then
singulated after fabrication.
Figure 2. New PCIe vs. existing PCIe connector
Figure 4. Evaluation board layout and cross-section
Figure 3. New PCIe x16 connector
III. EVALUATION BOARD AND DAUGHTER CARD DESIGNS
In order to assess the electrical characteristics of the new
PCIe connector, an evaluation board was designed and
fabricated as shown in Figure 4. The evaluation board
measures 125mm x 250mm and includes various card-edge
connector sites for contact pad comparisons. In addition to
the newly developed PCIe connector (X16), there are a few
other connector variants on the board, including the existing
PCIe Gen3 connector (X16), DDR4 memory connector, and
a customized CardEdge connector. For the PCIe connectors,
all sixteen differential channels are routed for various
sensitivity tests to be detailed in the following section. Eight
channels are routed through microstrip lines on top surface,
and the remaining channels are routed to the bottom layer
with vias. As the total microstrip line length to access each
Figure 5. Sensitivity test configurations
The total channel lengths are under 5cm (including
loopback on the daughter cards), and standard FR4 material
is used for low cost and fast prototyping. The cross-section
is simplified, and only the top and bottom layers are wired
with microstrip lines (150um line width), with four internal
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ground layers as signal line and via references. In order to
save space and minimize test fixture parasitics, signals are
launched via surface GSG probing sites on top and bottom
layers, whereas the bottom signal traces are connected to the
top connector mounting pads with vias. This configuration
allows us to test the effects of ground cutout under the
mounting pads as well as of via locations on signal
propagation and channel coupling as shown in Figure 5.
IV. MEASUREMENTS
PCIe adopts differential signaling to secure signal
integrity at aggressive data-rate. Therefore, for a complete
channel measurement, a minimum of four ports is required.
In this work, an Agilent E8364C 4-port 50GHz network
analyzer is used for all measurements. GGB 225um GS and
SG probes are selected to achieve balance between
performance and flexibility.
Figure 8. Assembled evaluation board and daughter cards
The evaluation board was assembled with a PCIe v3.0
X16 connector, the new PCIe X16 connector, and with a
DDR4 connector as shown in Figure 8. Corresponding
daughter cards were alternated for various test
combinations.
Figure 6. Daughter card designs, DC1 and DC2
Figure 6 shows the PCIe daughter card designs. All
signal pins are assigned in accordance with the PCIe v3.0
standard, i.e. differential signal channels on the same side
are isolated with two ground pins, and signal channels on
the opposite side of the card are offset by 2X the contact
pitch. Excessive contact pads tend to introduce significant
parasitic capacitance and inductance, which results in
unwanted resonances. Therefore, in addition to using the
standard contact pad length (4.2mm), shorter (3.2mm) ones
are used in two daughter card designs shown in Figure 6. In
the upper design (DC1), only the signal pads are shortened,
while both signal and ground pads are truncated in the lower
design (DC2).
To accommodate four probes landing simultaneously,
the daughter card establishes loopback connections between
contacts on the opposite sides of the daughter card with vias
as shown in Figure 7. Two types of measurements may be
implemented, from either top or bottom surfaces. The latter
includes via transitions through the board.
Figure 9. Through test sites for impedance check and de-embedding
Figure 9 shows the measured differential insertion loss
and reflection of “25mm through” test sites on top (without
via) and bottom layers (with via). Differential line pitch
matches the connector pin pitch of 1mm (150um line width
and 850um spacing), and therefore results in weak coupling
within pairs. Insertion loss in both cases (with and without
via) are almost identical up to 16GHz. Via effects on
Figure 7. Probe launching and positioning
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insertion loss may be observed above 16GHz. Reflection of
the “25mm through” is under -20dB up to 30GHz, which
indicates that the fabricated differential line impedance is
close to the 100 ohm target. The higher reflection of through
lines on the bottom layer is attributed to via transitions
through the board. For the 32Gbps data-rate (16GHz
fundamental frequency), via transitions elevate reflection by
~6dB, but won’t have any impact on insertion loss.
Figure 11. New PCIe connector, DC1 vs. DC2
Figure 10. New PCIe connector with DC1 daughter card
The measured differential insertion loss and reflection of
all eight channels on the top layer are shown in Figure 10,
for the new PCIe connector with the DC1 daughter card.
These measurement results are plotted in the same charts to
compare the effects of various solder pads and ground via
configurations, including full vs. half ground cutout
underneath the landing pads, and single vs. double ground
via, etc. For frequencies under 20GHz, there are no obvious
effects on either insertion loss and reflection, which
indicates that for the target data rate (32Gbps) landing pad
and ground via configurations are secondary factors for
surface wiring/feed. The reflection magnitudes draw
immediate attention, as they are well above -10dB beyond
10GHz. This is partially due to the impedance mismatch
between the instrument and the connector. The standard
instrument differential impedance is 100 ohm, while the
connector is designed for 85 ohm differential channels. The
actual reflection is expected to be lower in real applications.
The insertion loss at 16GHz is ~-10dB, which includes two
connector transitions, i.e. from board to daughter card, then
from daughter card back to board. In typical applications,
only one of the two transitions is involved, and insertion
loss is about half of the measured value, i.e. -5dB.
For a given seating height, the signal pad length on
daughter card is directly associated with the “pad stub”
resonance, and therefore, it is a common practice to partially
remove the signal pad close to the card edge to move the
stub resonance to higher frequency. The notches of both
curves at ~31GHz in Figure 11 are due to this stub
resonance. In both DC1 and DC2 daughter card designs, the
signal pads are shortened by 1mm, from 4.2mm down to
3.2mm. The difference between the two designs is on the
ground pads, i.e. DC1 with full ground pads and DC2 with
shortened ground pads (3.2mm). In both cases, the adjacent
ground planes underneath the pad region are cleared out.
Below 20GHz, the ground pad length shows very limited
effects on both insertion loss and reflection. A secondary
resonance (notch on insertion loss curve) may be observed
at ~27GHz, however, it should not have much effect on the
signal integrity at a 32Gbps data rate.
Similarly, the effects of top vs. bottom wiring observed
in Figure 9 are overwhelmed by connector discontinuities,
and therefore, exhibit minimum impacts on insertion loss
and minor effects on reflection as shown in Figure 12.
Beyond 25Gbps, crosstalk influence may become critical
to signal integrity. In order to measure differential crosstalk
with a 4-port VNA, the most suitable setup focuses on the
far end crosstalk of adjacent channels with unused terminals
floating as shown in Figure 13. The bottom eight channels
of the new PCIe connector with DC2 daughter card are
plotted in four curves. Again, the structural differences are
reflected in landing pad ground cutout and ground via
configurations. Below 20GHz, crosstalk values are nearly
identical. Beyond 20GHz, double ground via helps reduce
far end crosstalk to certain extent.
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to 50GHz. On the 220mm side, reflection is dominated by
transmission line attenuation, which could be very low if
designed properly. In this case, -20dB reflection is achieved
up to 30GHz.
Figure 14. Long and lossy PCIe channel
Figure 12. New PCIe connector, Top vs. Bottom
Figure 15. New PCIe connector vs. PCIe Gen3 connector
Figure 13. New PCIe connector, Far End Cross-Talk
A channel consisting of 262mm lines (220mm+42mm)
on FR4 standard loss material is included on the board as
shown in Figure 14. As expected, the total insertion loss is
close to -40dB at 16GHz. Therefore, low loss material is
required for long-reach channels. However, longer channel
length may tolerate higher reflection due to connectors. The
reflection at the 42mm side is already reduced to -12dB up
Based on the above observations, the improvement of
connector itself is the key to loss, reflection, and crosstalk
reduction. Figure 15 shows the comparisons between the
new PCIe connector and existing Gen3 PCIe connector.
Insertion loss of the new PCIe connector is significantly
reduced below 28GHz, together with lower reflection over
similar frequency range, which is mostly attributed to the
change of major resonance from 20GHz up to 31GHz. The
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secondary resonances at 9GHz, 12.5GHz, and 18GHz on the
PCIe Gen3 connector may negatively affect signal integrity
of 18Gbps, 25Gbps, and 36Gbps data transmission as well.
V. MODEL-HARDWARE CORRELATIONS
In addition to new PCIe connector development,
achieving good model-hardware correlation is another
important task of this project, which in turn assists I/O
designers on optimizing link topologies and achieving
signal integrity goals.
ANSYS HFSS 3D full wave modeling tool was used for
frequency domain simulations. In order to properly capture
the transitions of board-to-connector and connector-todaughter card, all major components are simulated in one
complete model, including the probe launches, on-board
transmission lines, connector, and daughter card. Figure 16
shows the complete view of the 3D model, which includes
all eight channels on the top layer of the evaluation board.
Lumped ports are used to properly reflect the signal
launching with GS and SG probes.
Figure 17. Model-hardware correlations
Figure 16. 3D model including board, connector, and daughter card
Figure 18. 10-inch channel with new PCIe connector
The frequency range and step are chosen in accord with
VNA measurements, i.e. 50GHz and 10MHz. Figure 17
shows the comparisons between the simulation and
measurement results on the new PCIe connector with DC1
daughter card. Reasonable correlations are found in both
insertion loss and reflection responses. On the insertion loss
curves, a small discrepancy occurs between 20GHz and
26GHz, with relatively greater differences above 31GHz.
Neither should have much impact on time domain
simulations of 32Gbps signaling, especially for long
channels with attenuated high frequency content. As for the
reflection responses, the simulation captures most periodic
behaviors, with slightly higher energy up to 8GHz (~3dB).
The latter is normally expected for HFSS simulations on
skinny transmission lines, and again, this effect diminishes
over lossy channels. For short channels, it may be improved
by increasing mesh density or creating transmission line
models with other appropriate simulation tools.
A typical PCIe channel is simulated and shown in Figure
18, with the channel including the new PCIe connector and
10-inch low loss transmission lines (Megtron 6). Insertion
loss is about -15dB at 16GHz, and reflection is under -10dB
over the entire frequency range.
The above channel is used for time domain simulations,
and the resulting eye diagrams are shown in Figure 19.
Figure 19(a) includes the results at 25Gbps data-rate with
15ps rise/fall edges. Without equalization, the eye height
and width are limited to low double digit values. By adding
a simple 2-TAP FFE at the transmitter, the eye is
significantly improved, exhibiting 210mV height and 30ps
width, which is more than sufficient for the receiver to
recover data with low error rate. The results running at
32Gbps data-rate are shown in Figure 19(b). Without
equalization, the eye is totally closed. By adding a simple 2TAP FFE, the eye is opened up to 126mV height and 20ps
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width, which is also sufficient for the receiver to recover
data with low error rate.
2-TAP FFE) than current PCIe v3.0 standard. Compared
with the connector effects on insertion loss, reflection, and
crosstalk, pad and via configurations are secondary factors.
By integrating all critical transitions in complete 3D
simulations, good model-hardware correlations were found,
which will provide confidence to I/O designers in making
link topology and material selection decisions.
(a) 25Gbps
VII. ACKNOWLEDGEMENT
(b) 32Gbps
The authors appreciate the helpful suggestions and
recommendations from IBM server group I/O design team
and discussions with Amphenol card-edge development
team.
REFERENCES
Figure 19. Eye-diagrams on 10” channel with new PCIe connector
Based on the channel shown in Figure 17 (new PCIe
connector with DC1 daughter card), a simulated TDR
impedance plot is shown in Figure 20. The channel starts at
the 1ns point with a slight impedance bump due to the probe
launch, followed with the microstrip transmission line at
exactly 100 ohm. The capacitive dip at 1.16ns is associated
with the landing pad on the PCB. The connector finger
impedance (slightly over 80 ohm) is seen near 1.2ns, then
followed by the contact pad on the daughter card at 1.24ns.
The transmission line on daughter card liess between 1.28ns
and 1.4ns, and the remaining trace is related to the mirror
path from daughter card back to the board. In general, the
new PCIe connector impedance is reasonably controlled to
the target 85 ohm impedance.
[1]
[2]
[3]
Figure 20. Simulated TDR on new PCIe connector with DC1 daughter
card
VI. CONCLUSIONS
In this joint development effort, a new backward
compatible PCIe connector was developed. An evaluation
board and matched daughter cards were designed and
fabricated to allow direct comparison between the new PCIe
connector to the existing PCIe connector (Gen3). At 16GHz
(for 32Gbps), insertion loss is reduced by 10dB, and
reflection is lowered by 2dB, which significantly improves
the channel robustness and ensures long-reach channel
signal integrity with equal or less I/O power budget (simple
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“Package level integration: challenges and opportunities”, Solid State
Technology, Insight for Electronics Manufacturing
“PCI-SIG® Fast Tracks Evolution to 32GT/s with PCI Express 5.0
Architecture”, Business Wire, June 07, 2017
“PCIe Still Strong Despite Alternatives”, EE Times, April 25, 2014