I/O Testing, I/O
DFT and I/O
Design Verification
(DV) fundamentals
• 3 Days
I/O Testing, I/O DFT and I/O Design
Verification (DV) fundamentals
• Objectives:
• In depth concepts, terminology, information on how to develop and
implement tests for opens and shorts, IO pin leakage, input voltage and
output voltage tests. Provide IO DV definitions of commonly used
parameters related to I/O signal pins and how these parameters are
characterized in an ATE environment.
• The aims of this course are to:
• Equip students with the knowledge of common IO tests in HVM TP
• Provide a basic idea of how to characterize or perform DV on IO tests
Classes for PDE skillsets improvements
Product & Test Engineering
No of days
Trainer
Dates
An Advanced Peek into Product and Test Engineering
1
Ms. Kng Saw Eng
24-Jul
IO Testing, IO DFT and IO Design Verification (DV) fundamentals
3
Ms. Kng Saw Eng
22-24 Aug
Data Analysis Method and How it impact in HVM #1
2
Ms. Kng Saw Eng
28-29 Aug
Industrial Radio Frequency (RF) theorems in Testing
3
Ms. Lee Ying Ying
4-6 Sep
Agenda
Day 1
Day 2
Day 3
• Pre-Test
• Leakage Test
• Opens and Shorts Test
• Standby Current (ISB/SICC)
• Importance of I/O Design
Validation
• VCC Continuity
• Boundary Scan in IO tests
• DFT - JTAG
• Input Voltage Tests
• Output Voltage Tests
• I2C
• SPI
• I/O DV Parameters
• DC Parameters
• AC Parameters
• The Future
• Post-Test
Recap for Advanced Peek
• DUT?
• Test Program?
• Why Testing?
• Where do we Test? Why?
• What are the components in an ATE?
Participation!
Participation!
Participation!
I/O = INPUT/OUTPUT
• The DUT - A semiconductor device being tested is often called the Device Under
Test
I/O
Electrical Properties
Impedance
Leakage
Voltage input/output levels
Timings
Single or differential signaling
States of being
Transmit, Receive, Idle, Tri-state
Logic and Memory
Specific protocols
for communicating
information
I/O
I/O Testing
• The process of sorting the defective from non-defective ( segregating
the bad and good units) in manufacturing/production.
• Comprised of DC testing that verifies the voltage and current parameters
• AC testing that verifies the device can perform logical operations within
specified-timing constraints
Have Fun!
Open/Closed/Short Circuit
Current, I
Open Circuit
Identify!
Short circuit
Open circuit
Closed circuit.
Closed Circuit
Current, I (High)
Short circuit
Short Circuit
Fuse
Current, I
Closed circuit
OPENS AND SHORTS TEST
• Test objectives:
• To verify that electrical contact is made to all signal pins on the DUT and that no signal pin is
shorted to another signal pin, power, or ground pin.
• To ensure the setup/orientation of tester/Prober/handler is correct.
• Bad opens and shorts test limits can fail good parts or let bad parts escape
• Finding the right test kill limits require characterization of I-V transfer curve
• Different types of shorts: pin short to ground, pin-to-pin short (maybe bent pins), or
with/without resistance
• This is typically the 1st test performed (at wafer and package)
• Types of Open/Short Test
• DC Test method/Serial Static method
• Functional Test method
Equipment
u1
I/O Buffer
• Buffer with ESD protection
Vcc
#1
To Core Logic
#2
Vss
10
Slide 10
u1
Let's student guess is Input or Output pad?
user, 3/10/2017
Types of Defects
1. Wrong set-up/orientation of the IC in the test equipment
Correct Orientation
Wrong Orientation
Open Circuit =>1.5V OR
Short Circuit =< 0.2V
Types of Defects
2. Missing/functioning incorrectly/damaged protection diode
Open Circuit =>1.5V
Short Circuit =< 0.2V
Types of Defects
3. Defects in die for wafer and wire bond for package
Broken\Missing wire bonds
Open Circuit =>1.5V
Improperly installed wire bonds
Open Circuit =>1.5V
Types of Defects
Shorts Defects
Leadframe whiskers
All 4 cases are Short Circuit =< 0.2V
OPENS AND SHORTS TEST
• How to Conduct Open Test
• The test conditions for Open Tests is normally not specified in the data sheet. However, there
are standard values which apply to most devices.
• To conduct the open tests, the ESD protection Diode circuit of each input pin is used
• PMU will be used in Force Current Measure voltage mode to perform the Open / Short test.
• 2 methods to conduct Opens Test
• Ground Diode Method
• Power Supply Diode Method
Recap! Diode
Characteristics
What is Diode Characteristics?
• A diode : Allows current to flow in one
direction.
I
• This is the electrical symbol of a diode.
Anode
Cathode
What is Diode Characteristics?
• The current flows in the same direction
as the arrow
• We call this a forward bias, in general, a
current cannot go in the opposite
direction.
What is Diode Characteristics?
• A current can flow in the opposite direction if
a very high voltage is applied.
• This very high voltage is called the diode
breakdown voltage or symbolized as 𝑩𝑹 .
When this happens, the diode is now in a
reverse bias mode.
𝑉
Opens Test
• How to conduct Open Tests (Method 1 – GND Diode Check)
• Set Vcc/Vdd =0V
• Apply -100uA current on the Pin Under Test
• Measure Voltage on the Pin Under Test
• If there is good contact, Pass, -0.7V Voltage will be measured
• If there is NO good contact, Fail, Voltmeter will have very large negative voltage reading
Opens Test
• How to conduct Open Tests (Method 2 – Vdd Diode Check)
• Similar to as earlier, except for the reverse current flow
• Set Vcc/Vdd =0V
• Apply 100uA current on the Pin Under Test
• Measure Voltage on the Pin Under Test
• If there is good contact, Pass, 0.7V Voltage will be measured
• If there is NO good contact, Fail, Voltmeter will have very large negative voltage reading
Shorts Test
• How to conduct Shorts Tests (Method 1 – GND Diode Check)
• Apply 0V to all other pins that is not tested.
• Apply -100uA current on the Pin Under Test
• Measure Voltage on the Pin Under Test
• If there is NO Short circuit to VCC/GND/another pin, Pass, -0.7V Voltage will be measured
• If there is Short to GND/Power Supply Pin/another pin, Fail, 0.0V Voltage will be
measured
OPENS AND SHORTS TEST – DC Test Method
• Open and Short test concept, they are pretty similar
• Combine both tests into one  more productive!
• Upon combined, here are the test conditions on the Pin Under test as earlier
• Apply 0V to all other pins that is not tested
• Apply -100uA Current on the Pin Under Test
• Measure Voltage on the Pin Under Test
• This is done repeated for 100uA and repeatedly as each pin is individually tested.
Scenario
Measurement Result
Good Contact, Pass
-0.7V/0.7V
Open, No Good Contact, Fail
High Negative/Positive Voltage will be
measured
Shorted to Vcc/GND/Another Pin, Fail
0.0V
I/O IV curve
OPENS AND SHORTS TEST
• Fundamental of opens & shorts
testing with the “parametric”
approach.
• Parametric approach means
measure and check the result of
each input pin on the package.
• Assuming each pin are tested in
sequentially, test time for a package
will gradually increase if the pin
count increase.
OPENS AND SHORTS TEST
Activity~
• Sample Datalog:
• Failing Pin
• Short : __________
• Open : __________
Number
Site
Result
Test Name
Pin
Channel
Low Limit Measured
200
0
FAIL
cont_P2
p23
7
-1.5000V
201
0
PASS
cont_P2
p22
31
-1.5000V
-785.3mV -200.0000mV -100.0000uA
202
0
PASS
cont_P2
p21
23
-1.5000V
-953.0mV -200.0000mV -100.0000uA
203
0
PASS
cont_P2
p20
48
-1.5000V
-877.4mV -200.0000mV -100.0000uA
204
0
FAIL
cont_ctr
cs
4
-1.5000V -0.0004mV -200.0000mV -100.0000uA
205
0
PASS
cont_ctr
prg
30
-1.5000V -943.96mV -200.0000mV -100.0000uA
-8.630V
High Limit
Force
-200.0000mV -100.0000uA
Defects/Problems
Problem or Defect
Tester setup problems (for example, TIU seating problems)
Correct DUT orientation
Correct probe card alignment and planarization
Bent or broken pogo pins on the TIU
Broken or contaminated contactor (for example, solder flakes)
Wire sweep during plastic encapsulations
Wire droop in ceramic packages
Missing wirebonds
Package pin-to-pin shorts (for example, leadframe whiskers)
Pin-to-VCC/VSS shorts
Open or broken package pins (for example, plastic flashing on pin)
Silicon defects in ESD structures
Fail Shorts
Fail Opens
Vcc Continuity
• Test objectives:
• To screen for manufacturing defects that cause a short between Vcc and Vss at both die and
package levels
• For tester/hardware protection from damage due to high current brought about by shorted
VCC and VSS lines.
• It is the equivalent of the I/O opens/shorts test for the VCCs and VSSs.
• There is no published spec in the datasheet relating to VCC continuity
• Force voltage or Force Current method?
•
•
•
•
No DUT preconditioning is required. DUT need not to power up
Low current usage to prevent activating DUT transistors
More accurate for PMU than forced voltage method
More test time efficient and simpler to implement
Vcc Continuity
• Test Methodology
• Precondition all pins to GND (0V).
• Force current on the VCC under test pin being.
• Measure the voltage vs. expected limit.
Vdd = 0V
I
Power Supply Pin
Pin Under Test
0V
0V
0V
0V
0V
0V
Current Source
Voltmeter
Vss, Gnd Pin
BREAK
Design for Testability (DFT)
• What is DFT?
• Insert circuitry that has little to do with device
functionality, but
• Improve testability : controllability & observability
• Why DFT?
• Improve test quality : high fault coverage
• Reduce test cost : shorten test length and test time
• Reduce time to market : easier to debug and
diagnosis
Input
Pins
TMS
TCK
Output
Pins
Control
Signals
TAP Controller
Instruction Decoder
• Design For Testability (DFT) techniques, e.g.
• Test Point Insertion : Adding control and
observation points
• Internal Scans : FF-based, Latch-based
• External Scan : JTAG (1149.1)
Device
Logic
Instruction Register
TDI
Bypass Register
MUX
TDO
Design for Testability (DFT)
Think
• What are the Penalty of DFT ?
•
•
•
•
•
Design effort overhead
Performance degradation
Hardware overhead : extra area, extra pins
Yield loss : larger area  lower yield
Power overhead : power tax of testing
• Which of the following is NOT true about DFT?
A. DFT reduces designer’s effort
B. DFT cost extra hardware and power
C. DFT reduces test cost so it is needed for complex design
What is External Scan?
• What is External Scan?
• Stitch device input/output pins into a shift register : Serial scan path through the IO pins
• To gain observability and controllability on the device input/output
• Also known as boundary scan because it is “wrap” outside the device logic
Input
Pins
TMS
TCK
Device
Logic
Output
Pins
Control
Signals
TAP Controller
Instruction Decoder
Instruction Register
TDI
Bypass Register
MUX
TDO
Boundary Scan/JTAG
• Boundary scan standard is needed to allow chips from different vendors to be
tested together
• IEEE 1149.1 Standard aka JTAG
• Why use boundary scan?
•
•
•
•
Board level test and diagnosis
Test on-board interconnect among chips : Connectivity tests between components
Test on-chip system logic
Device testing on the DC specifications :eg VIL/VIH, VOL/VOH, IOZ
Examples Of Boundary Scan Testing
Board Level test for multiple chips
Input :X X X X
Output :X X X X
1 0 1 X X X X X
X X X X X D O D
X X X X  First scan in
X X X X  First scan out
Test on-board for connectivity among chips
Bridge fault & stuck-at fault detection
Examples Of Boundary Scan Testing
Device testing on the DC
specifications
Input : X 1 1 X
Input : X 0 1 X
Input : X 1 0 X
First scan in
X X X X
X X X X
X X X X
First scan out
Good Output : X X X X X X 1 X
Good Output : X X X X X X 0 X
Good Output : X X X X X X 0 X
Test on-chip system logic : AND gate example
JTAG Architecture
• JTAG Components
1. Test Access Port (TAP) 4 dedicated test pins
2. FSM TAP controller
3. Registers : Instruction Registers, Boundary Scan Registers, Bypass Registers
4. Instruction Decoder
Device
Logic
TMS
TCK
Output
Pins
Control
Signals
TAP Controller
Instruction Decoder
Instruction Register
TDI
Bypass Register
MUX
TDO
JTAG Architecture : TAP
Activity!
• 4 mandatory TAP
•
•
•
•
• 1 optional TAP
TDI : Test Data Input
TDO :Test Data Output
TCK : Test Clock
TMS : Test Select Mode
Input
Pins
TMS
TCK
• TRST: Reset of Test Logic (Active Low)
Device
Logic
Output
Pins
Control
Signals
TAP Controller
Instruction Decoder
Instruction Register
TDI
Bypass Register
MUX
TDO
JTAG Architecture : TAP
Activity!
• What is TAP?
•
The Test Access Ports (TAPs) are general purpose ports and provide access to the test function of the IC between the application circuit and the
chip's I/O pads. It includes four mandatory pins TCK, TDI, TDO and TMS and one optional pin TRST
• TDI (Test Data In):
•
Serial data in sampled on rising edge with internal weak pull-up
• TDO (Test Data Out):
•
•
Serial data out sampled on falling edge. Negative edge flop is placed at the TDO output buffer
Open drain where output driver will be disabled except during shifting/scanning  parallel connection of board level test data paths when
required
• TMS (Test Mode Select):
•
Used to control the FSM. TMS sampled on rising edge and has internal weak pull-up
• TCK (Test Clock In):
•
•
Dedicated test clock for the TAP
At board level, TCK frequency depends on the smallest FMAX device. Must not share with system clock to allow real time monitoring
• There is an optional TRST pin which is an async reset.
•
•
If TRST# is not present, there is always a synchronous reset available within the FSM. TMS=1 for 5 TCK will bring it back to Reset State
TRST need to be weak pull-up
38
Why TDI, TMS and TRST Need Pull-Up?
• TMS: TAP controller back to reset after 5 TCK
• TDI: Bypass instruction (ALL1) is loaded
• TRST:
Provide safe states to the boundary scan without
interfering with the device normal functionality
39
JTAG Architecture : TAP Controller
• Control JTAG Operation
• 16 states Finite State Machine
• Clock is TCK
• Input is TMS
• Test Logic-Reset
•
•
•
•
Reset JTAG Circuits
How to reset JTAG?
TMS = 111…., or
TRST = 0
JTAG States
JTAG state
Function
TDO driven by
TDO output
(Reset)
Initializes Instruction Register (IR) with IDCODE instruction
---
Disabled
(Run/Idle)
State between scan operations
---
Disabled
(Select-DR)
Transition state
---
Disabled
(Select-IR)
Transition state
---
Disabled
(Capture-IR)
Parallel loads IR with ‘0101010101’ on rising edge of TCK
---
Disabled
(Shift-IR)
Shifts TDI into IR on rising edge of TCK; Shifts IR out on TDO on falling edge of
TCK
Instruction Register
Enabled
(Exit1-IR)
Transition state
---
Disabled
(Pause-IR)
Hold state to pause shifting of IR
---
Disabled
(Exit2-IR)
Transition state
---
Disabled
(Update-IR)
Instruction in IR is latched to be the active instruction on falling edge of TCK
---
Disabled
(Capture-DR)
Parallel loads Test Data Register (DR) with data (if provided) on rising edge of
TCK
---
Disabled
(Shift-DR)
Shifts TDI into DR on rising edge of TCK; Shifts DR out on TDO on falling edge
of TCK
Test Data Register
Enabled
(Exit1-DR)
Transition state
---
Disabled
(Pause-DR)
Hold state to pause shifting of DR
---
Disabled
(Exit2-DR)
Transition state
---
Disabled
(Update-DR)
Loads update registers (if provided) in parallel with shifted in DR
---
Disabled
TDO output buffer ONLY enabled during Shifting, rest of the time is disabled/pull-up
41
JTAG : Timings of FSM
Capture action
Update action
BKM:TDI and TMS changes at falling edge of TCK to give enough setup time on the rising edge of TCK
42
DFT – what we have cover so far..
• IEEE 1149.1
• Boundary scan standard
• Aka JTAG
• Why use boundary scan?
• Board-level, interconnect, system logic,
• JTAG components
•
•
•
•
Test Access Port
TAP controller (16-state FSM)
Registers
Instruction Decoder
JTAG : Food For Thought
• What is the max number of 1’s needed
to initialize the JTAG?
• TMS = 111… ???
Think!
BREAK (Optional)
JTAG : Registers
• Data Registers, DR
• Bypass Register, BR
• Boundary Scan Register, BSR
Mandatory
Register!
• Instruction Register, IR
• Optional Registers
• Device ID Register
• Device Specific Register
• The registers shared the same TDI/TDO
Input
Pins
TMS
TCK
Device
Logic
Output
Pins
Control
Signals
TAP Controller
Instruction Decoder
Instruction Register
TDI
Bypass Register
MUX
TDO
JTAG : The Bypass Register
• Purpose : Provide short cut from TDI to TDO
• One-bit FF(register) : Shift data from TDI to TDO when ShiftDR=1
*DR = Data
Register
Input
Pins
TMS
TCK
Device
Logic
Output
Pins
Control
Signals
TAP Controller
Instruction Decoder
Instruction Register
TDI
Bypass Register
MUX
TDO
JTAG : Boundary Scan Register, BSR
• Purpose : Control device I/O pins; Observe device I/O pins
• BSR consists of Boundary Scan Cells(BSC)
Input BSC
Input
Pins
TMS
TCK
Output BSC
Device
Logic
Output
Pins
Control
Signals
TAP Controller
Instruction Decoder
Instruction Register
TDI
Bypass Register
MUX
TDO
JTAG : Input Boundary Scan Cell, BSC
• Each Input BSC contain:
• 2 FF : capture/scan FF, output FF
• 2 ctrl signals : ShiftDR, Mode
• 2 clocks : ClockDR, Update DR
Input
Pins
TMS
TCK
Device
Logic
Output
Pins
Control
Signals
TAP Controller
Instruction Decoder
Instruction Register
TDI
Bypass Register
MUX
TDO
JTAG : Input BSC Operation
• Normal : Input pin to device logic
• BSC is transparent
Operations
Normal
Scan
Update
Capture
Control Signal
Mode ShiftDR
0
X
X
1
1
X
X
0
Clock
Device
ClockDR
UpdateDR
ClockDR
Device
logic
JTAG : Input BSC Operation
• SCAN : Shift from one Scan FF to next scan FF
• Does NOT interfere with device logic
Operations
Normal
Scan
Update
Capture
Control Signal
Mode ShiftDR
0
X
X
1
1
X
X
0
Clock
system
ClockDR
UpdateDR
ClockDR
JTAG : Input BSC Operation
• Update : Load data from scan FF to output FF
• Apply test pattern to device logic
Operations
Normal
Scan
Update
Capture
Control Signal
Mode ShiftDR
0
X
X
1
1
X
X
0
Clock
system
ClockDR
UpdateDR
ClockDR
JTAG : Input BSC Operation
• Capture : From device input to capture FF
• Capture test response
Operations
Normal
Scan
Update
Capture
Control Signal
Mode ShiftDR
0
X
X
1
1
X
X
0
Clock
system
ClockDR
UpdateDR
ClockDR
Summary of Input BSC Operations
JTAG : Output BSC Operation
• Very similar structure to input BSC, but different direction
Input
Pins
TMS
TCK
Device
Logic
Output
Pins
Control
Signals
TAP Controller
Instruction Decoder
Instruction Register
TDI
Bypass Register
MUX
TDO
JTAG : Output BSC Operation
• For output BSC, please fill in table for 4 operations
Operations
Normal
Scan
Update
Capture
Control Signal
Mode ShiftDR
0
X
X
1
1
X
X
0
Clock
Think!
JTAG : Instruction Register
• Purposes
• Shift in instruction from TDI
• Store JTAG instructions for instruction decoder
Input
Pins
TMS
TCK
Device
Logic
Output
Pins
Control
Signals
TAP Controller
Instruction Decoder
Instruction Register
TDI
Bypass Register
MUX
TDO
JTAG : Instruction Register
• Two layers of FF : scan FF & output FF
• How to load the instruction?
• ShiftIR=1, clock IR = 1, clock IR = 1
• UpdateIR
• Scan does NOT interfere with instruction decoder
TAP Instruction Register Access
TCK
TMS
CLAMP = 0000100
Update-IR
Shift-IR
Exit1-IR
Capture-IR
Select-IR-Scan
Select-DR-Scan
Run-Test/Idle
Test-LogicReset
TAP
Controller
State
Run-Test/Idle
TDI
TDO
Instruction
Register
Output
"IDCODE"
"CLAMP"
BKM:TDI and TMS changes at falling edge of TCK to give enough
setup time on the rising edge of TCK
Let’s watch a video!
TAP Instruction Register Access
TCK
TMS
CLAMP = 0000100
Update-IR
Shift-IR
Exit1-IR
Capture-IR
Select-IR-Scan
Select-DR-Scan
Run-Test/Idle
Test-LogicReset
TAP
Controller
State
Run-Test/Idle
TDI
TDO
Instruction
Register
Output
"IDCODE"
"CLAMP"
TAP Instruction Register Access
TCK
TMS
CLAMP = 0000100
Update-IR
Shift-IR
Exit1-IR
Capture-IR
Select-IR-Scan
Select-DR-Scan
Run-Test/Idle
Test-LogicReset
TAP
Controller
State
Run-Test/Idle
TDI
TDO
Instruction
Register
Output
"IDCODE"
"CLAMP"
TAP Instruction Register Access
TCK
TMS
CLAMP = 0000100
Update-IR
Shift-IR
Exit1-IR
Capture-IR
Select-IR-Scan
Select-DR-Scan
Run-Test/Idle
Test-LogicReset
TAP
Controller
State
Run-Test/Idle
TDI
TDO
Instruction
Register
Output
"IDCODE"
"CLAMP"
TAP Instruction Register Access
TCK
TMS
CLAMP = 0000100
Update-IR
Shift-IR
Exit1-IR
Capture-IR
Select-IR-Scan
Select-DR-Scan
Run-Test/Idle
Test-LogicReset
TAP
Controller
State
Run-Test/Idle
TDI
TDO
Instruction
Register
Output
"IDCODE"
"CLAMP"
TAP Instruction Register Access
TCK
TMS
CLAMP = 0000100
Update-IR
Shift-IR
Exit1-IR
Capture-IR
Select-IR-Scan
Select-DR-Scan
Run-Test/Idle
Test-LogicReset
TAP
Controller
State
Run-Test/Idle
TDI
TDO
Instruction
Register
Output
"IDCODE"
"CLAMP"
TAP Instruction Register Access
TCK
TMS
MSB
LSB
TDI
LSB
CLAMP = 0000100
0 0 1
Update-IR
Shift-IR
Exit1-IR
Capture-IR
Select-IR-Scan
Select-DR-Scan
Run-Test/Idle
Test-LogicReset
TAP
Controller
State
Run-Test/Idle
MSB
0 0 0 0
TDO
Instruction
Register
Output
"IDCODE"
"CLAMP"
TAP Instruction Register Access
Shift-IR : The output arrives @ TDO on the
failing edge of TCK
TCK
TMS
Shift-IR
CLAMP = 0000100
Update-IR
Exit1-IR
Capture-IR
Select-IR-Scan
Select-DR-Scan
Run-Test/Idle
Test-LogicReset
TAP
Controller
State
Run-Test/Idle
TDI
TDO
Instruction
Register
Output
1 0 0 0 0 0
"IDCODE"
0
"CLAMP"
TAP Instruction Register Access
TCK
TMS
CLAMP = 0000100
Update-IR
Shift-IR
Exit1-IR
Capture-IR
Select-IR-Scan
Select-DR-Scan
Run-Test/Idle
Test-LogicReset
TAP
Controller
State
Run-Test/Idle
TDI
TDO
Instruction
Register
Output
"IDCODE"
"CLAMP"
TAP Instruction Register Access
TCK
TMS
CLAMP = 0000100
.
Update-IR
Shift-IR
Exit1-IR
Capture-IR
Select-IR-Scan
Select-DR-Scan
Run-Test/Idle
Test-LogicReset
TAP
Controller
State
Run-Test/Idle
TDI
TDO
Instruction
Register
Output
"IDCODE"
"CLAMP"
TAP Instruction Register Access
TCK
TMS
CLAMP = 0000100
Update-IR
Shift-IR
Exit1-IR
Capture-IR
Select-IR-Scan
Select-DR-Scan
Run-Test/Idle
Test-LogicReset
TAP
Controller
State
Run-Test/Idle
TDI
TDO
Instruction
Register
Output
"IDCODE"
"CLAMP"
TAP Instruction Register Access
TCK
TMS
CLAMP = 0000100
Update-IR
Shift-IR
Exit1-IR
Capture-IR
Select-IR-Scan
Select-DR-Scan
Run-Test/Idle
Test-LogicReset
TAP
Controller
State
Run-Test/Idle
TDI
TDO
Instruction
Register
Output
"IDCODE"
"CLAMP"
TAP Instruction Register Access
TCK
TMS
CLAMP = 0000100
Update-IR
Shift-IR
Exit1-IR
Capture-IR
Select-IR-Scan
Select-DR-Scan
Run-Test/Idle
Test-LogicReset
TAP
Controller
State
Run-Test/Idle
TDI
TDO
Instruction
Register
Output
"IDCODE"
"CLAMP"
More on The FSM
Activity!
• The TDI signal is always sampled on the rising of edge of TCK, starting on
the second entry into the Shift-xR state.
• The data shifted out is placed on TDO on the falling edge of TCK starting on
the first entry into the Shift-xR state.
• The last sample of TDI is always performed when exiting the Shift-xR state.
• In the Capture-xR state, the contents of the register are latched into the
corresponding shift register (the instruction shift register or the data shift
register) on the next rising edge of TCK.
• The contents of the selected shift register are latched into the selected
data register (or instruction register) in the Update-xR state. This is done
on the falling edge of TCK when in the update state
72
JTAG : How to Load Instruction
• Initialize JTAG : TMS = 11111
• Test-Logic-Reset state (regardless of initial state)
• Select IR : TMS = 01100
• ShiftIR state
• Load Instruction : TMS = 0…..0
• Keep in ShiftIR state
• Instruction shifted in via TDI
• Finish : TMS = 110
• Back to Run-Test-Idle state
Load
Instruction
JTAG : Instruction Decoder
Normal IO
Data registers
Boundary Scan Register
• Instruction Decoder generates
control signals
Normal
IO
• Mode
• Select (DR)
User defined register
• Rising edge of TCK
Device ID register
Bypass register
• ClockDR, ClockIR
• TAP state transition
mode 1
• Falling edge of TCK
• UpdateDR, UpdateIR
• TDO Output
Normal
IO
Core Logic
(system circuitry)
mode n
Instruction Decoder
TDI
Instruction register
ClockDR
ShiftDR
UpdateDR
TDI
TCK
TRST
ClockIR
ShiftIR
UpdateIR
Select
TAP
Controller
TCK
Shift
D
Q
TDO
JTAG – what we cover so far..
• Data Register (DR)
• Bypass register (BR)
• Boundary scan register (BSR)
• Input Boundary Scan Cell
• Output Boundary Scan Cell
• Each BSC
• 2 controls : ShiftDR, Mode
• 2 clocks : ClockDR, UpdateDR
• 4 operations : normal, scan, capture, update
• Instruction Register (IR)
• Control signals generated by instruction decoder
JTAG : Instructions
IEEE 1149.1 Instruction Set
• 4 mandatory instructions : must implement
• Others are optional : up to designer’s decision
JTAG : How to Load Instruction
• Apply TMS Sequence
• Initialize JTAG : 11111
• Load Instruction : 01100  0…..0 
110
• Number of zeros =
• Total length of the Instruction Register
• Of all chips on board
• Instruction code is shifted via TDI
• JTAG specified Instruction code
• EXTEST = 000 … (all zeros)
• BYPASS = 111 … (all ones)
• Other codes specified by designers
Load
Instruction
JTAG : EXTEST
• Purpose : External test
• Test external off-chip wire interconnections among chips
Input :
Output :
X X X X
X X X X
1 0 1 X X X X X
X X X X X D O D
X X X X  First scan in
X X X X  First scan out
JTAG : EXTEST (Example 1/3)
• 1. Load Instruction
Initialize TAP
11111
TMS
TDI
TDO
Final state
Test logic state
Load Instruction
01100* 000 0000**
000 0000
Shift-IR
110
Run-test/Idle
Left bit shifted in first
*chip #1, IR has 4 bits, chip #2 IR has 3 bits
 Total length of IR = 7 bits
IR = 0000
Input :
Output :
X X X X
X X X X
IR = 000
1 0 1 X X X X X
X X X X X D O D
X X X X  First scan in
X X X X  First scan out
JTAG : EXTEST (Example 2/3)
• 2. Scan-In-Update ( shift data in )
Scan-In
TMS
TDI
TDO
Final state
100 0000 0000 0000 0000 1
xxxx xxxx x101 xxxx
Shift-DR
Update
1
1
Update-DR Select DR-scan
TDI
TDO
IR = 0000
IR = 000
Left bit shifted in first
*chip #1, DR has 8 bits, chip #2 DR has 8 bits  Total length of IR = 16 bits
JTAG : EXTEST (Example 3/3)
• 3. Capture-Scan-Out
Capture
TMS
TDI
TDO
Final state
0
Scan Out
0
0000 0000 0000 0000
110
xxxx HLHx xxxx xxxx
Capture-DR
Shift-DR
Run-test/Idle
Left bit shifted in first
*chip #1, DR has 8 bits, chip #2 DR has 8 bits  Total length of IR = 16 bits
JTAG : BYPASS INSTRUCTION
• Purpose : bypass scan data from TDI to TDO of a chip
• Through bypass register (BR, 1 bit)
• Example :
• Go through chip#1 : 24 clocks
• Bypass chip#1 : 1+8+8 clocks = 17 clocks
Bypass Saves Time !
Quiz!
Breakout
Session
JTAG : BYPASS INSTRUCTION
 Suppose we add chip#1 to our board.
Initialize TAP
 We want to apply EXTEST to chip#2 and chip#3.
11111
TMS
TDI
 Please modify TMS/TDI/TDO sequence to bypass chip#1.TDO
Final state
NOTE:
01100* 000 0000**
000 0000
Test logic state
Shift-IR
Scan-In
 BYPASS instruction code for chip#1 = ‘11’
 EXTEST instruction code ‘000’ and ‘0000’
IR = 0000
Load Instruction
IR = 000
TMS
TDI
TDO
Final state
100 0000 0000 0000 0000 1
xxxx xxxx x101 xxxx
Shift-DR
0
Run-test/Idle
Update
1
1
Update-DR Select DR-scan
Capture
TMS
TDI
TDO
Final state
110
Scan Out
0
0000 0000 0000 0000 110
xxxx HLHx xxxx xxxx
Capture-DR
Shift-DR
Run-test/Idle
JTAG Instructions ..
• We cover two mandatory instructions
• EXTEST (000…0)
• Test wires among chips
• Scan-in, update, capture, scan-out
• BYPASS (111….1)
• Bypass chips to save time
Points to Remember on JTAG 1149.1
• 4 dedicated pins (TDI, TCK, TMS, TDO) with 1 optional pin TRST
• TDI, TCK, TMS: week pull-up
• TDO: open drain
• 16 states FSM
• Registers: boundary scan , data (core), instruction, bypass
• Think of boundary scan as scan chain around the IO peripherals
• Mandatory instructions: BYPASS, SAMPLE,PRELOAD and EXTEST
• Pin timings:
• TDI & TMS: clocked in at rising edge of TCK
• TDO: clocked out at falling edge of TCK
• Does NOT interfere with Chip operation
• Can be used at various stages from on-chip to system level – flexible
• Provide sufficient test coverage of stuck-at faults for digital/DC interconnects
• Have limitation on AC coupled signals and differential signals
• Taken care by 1149.6 (not covered in this material)
Quiz!
Time Check!
I/O Testing, I/O DFT and
I/O Design Verification
(DV) fundamentals
(DAY 2)
Have Fun!
Leakage
• What is leakage?
• Defects and problems :
• leakage current which may flow via these circuit elements, example
• gate oxides of the input/output buffer transistors
• ESD diodes junctions
• Leakage path which may exists in between bond wires in package, traces in package, pin outside of the
package
• Leakage path in loadboard
Leakage Test
• The goal of leakage test is to:
• Screen for fab process excursions
• Assembly defects and damage caused during back-end manufacturing handling
• Leakage is a quality and reliability required screen for IO and output only pins
• Leakage inherently is a strong function of the silicon device process generation
Leakage Test
• How to Conduct Leakage Test
• The Leakage Tests ensures that input meet the design parameters and guarantees that the
input will not source or sink more current than specified
• Leakage is measured by simply forcing a DC voltage on the input pin of the device under test
and measuring the small current flowing into or out of the pin.
• 2 methods
Check the device
• Vcc Leakage Test, IIL
• Vss Leakage Test, IIH
• Vcc Leakage Test, IIL – leakage path from Vcc to input pin
• Vss Leakage Test, IIH – leakage path from input pin to Vss, Ground
specifications !
Leakage Test
Vcc Leakage Test
• How to conduct Vcc Leakage Test, IIL
1.
2.
3.
4.
5.
6.
Apply Vddmax(Vccmax) to the Vdd(Vcc)
Apply Vih to all input pins except Pin Under Test
Apply Vil to Pin Under Test
Measure current on the Pin Under Test
Check the measured current with Device Spec
Repeat to the next input pin
Vdd = 5.5V
Power Supply Pin
IIL
5V
0V
Pin Under Test
Amp-meter
5V
5V
5V
Vss, Gnd Pin
Voltage Source
5V
Leakage Test
Vss Leakage Test
• How to conduct Vss Leakage Test, IIH
1.
2.
3.
4.
5.
6.
Apply Vddmax(Vccmax) to the Vdd(Vcc)
Apply Vil to all input pins except Pin Under Test
Apply Vih to Pin Under Test
Measure current on the Pin Under Test
Check the measured current with Device Spec
Repeat to the next input pin
Vdd = 5.5V
Power Supply Pin
IIH
0V
5V
Pin Under
Under Test
Test
Amp-meter
Voltage Source
0V
0V
0V
0V
Vss, Gnd Pin
Leakage Test
Pad-to-Pad Leakage Test
• Able to isolate any defects between pads or pins
• Pad-to-pad leakage is done by driving adjacent pins to the opposite power supplies
Pad-to-Pad Leakage Test
• Pad-to-pad leakage is done by driving adjacent pins to the opposite power supplies
• The presence of a low-impedance path between the pins will result in a high measured
current
94
Serial vs Parallel Leakage
• There are two ways to perform leakage test on pins:• Serial
• Parallel
• The difference between these 2 methods is how the
measurement is carried out on the pin.
• Serial  Each pin is tested one at a time (serially) using the system PMU,
• Parallel  All/More than one pin are tested at once (parallel) using the
system PMU.
Serial Test Method
• Each pin is tested one at a time using the
system PMU
• All other pins are forced to the opposite
power supply rail
• Before the PMU is employed, a preconditioning pattern is run to tri-state the
part
• Usually used where PPMU is not available
Ste PMU Force
p Voltage
1
VLOW
2
VHIGH
Parallel Test Methods
• Pins to be tested are partitioned into
non-adjacent groups
• All pins are tri-stated via a preconditioning pattern
• Pins within a group are tested at the
same time
• Adjacent pins not being tested are
forced to the opposite power supply rail
• This requires that the tester
architecture support per-pin parametric
measurement units (PPMU)
Serial vs Parallel Leakage
Activity!
Serial
Test Time
Failing Input Pin
PMU Requirement (PMU/Per Pin PMU)
TP Flow ( Main Flow/Fail Flow)
Parallel
Leakage Test
Identify!
• Sample Datalog:
• Failing Pin
• IIL : __________
• IIH : __________
Number
150
151
152
153
154
155
156
157
158
159
160
161
Site
0
0
0
0
0
0
0
0
0
0
0
0
Result
FAIL
PASS
PASS
PASS
PASS
PASS
FAIL
PASS
FAIL
PASS
PASS
PASS
Test Name
ppmu_loleak_p2
ppmu_loleak_p2
ppmu_loleak_p2
ppmu_loleak_p2
ppmu_loleak_ctr
ppmu_loleak_ctr
ppmu_hileak_p2
ppmu_hileak_p2
ppmu_hileak_p2
ppmu_hileak_p2
ppmu_hileak_ctr
ppmu_hileak_ctr
Pin
p23
p22
p21
p20
cs
prg
p23
p22
p21
p20
cs
prg
Channel
7
31
23
48
4
30
7
31
23
48
4
30
Low Limit
-10.0000 uA
-10.0000 uA
-10.0000 uA
-10.0000 uA
-10.0000 uA
-10.0000 uA
-10.0000 uA
-10.0000 uA
-10.0000 uA
-10.0000 uA
-10.0000 uA
-10.0000 uA
Measured
-18.2912 uA
875.1700 pA
-5.0839 nA
-5.1774 nA
1.6501 nA
-1.2792 nA
32.7916 uA
10.9652 nA
12.4392 uA
2.3655 nA
26.8562 nA
18.8714 nA
High Limit
10.0000 uA
10.0000 uA
10.0000 uA
10.0000 uA
10.0000 uA
10.0000 uA
10.0000 uA
10.0000 uA
10.0000 uA
10.0000 uA
10.0000 uA
10.0000 uA
Force
0.0000 V
0.0000 V
0.0000 V
0.0000 V
0.0000 V
0.0000 V
5.5000 V
5.5000 V
5.5000 V
5.5000 V
5.5000 V
5.5000 V
Static ICC
• What is static current?
Zzz
Static ICC
• Test Objective:
• Static ICC test is used to screen for manufacturing or process defects which cause elevated
static currents.
• The measurements are made mainly with the tester DPS but occasionally with PMU, due to
ATE resource limitation.
• Several SICC measurements are made and averaged out.
• Prior to any measurement, an appropriate settling period is required to allow
device switching transitions to end.
• Static indicates that the measurement is made when DUT is not active.
• To ensure that the DUT will not consume more current than the available value in
the Specification.  Important for battery operated devices.
Static ICC
• How to conduct Static ICC test:
•
•
•
•
•
•
Apply VDD to Device
Precondition current Clamp on the Voltage source
Precondition Device to the lowest power Consumption state  in pattern
Wait for 5mS to 10mS
Measure current flowing through the VDD pin
Check the limit to see if the current drawn is excessive
Icc (Static)
Amp-meter
Vdd = 5.5V
Pre Condition
Pattern
Voltage Source
Vss, Gnd Pin
BREAK
FYI – Typical Test Flow
Open/Short
DC Parametric Tests
SICC
Bin 10
Bin 11
Bin 12
Functional Test
Bin 13
AC Parametric Test
Bin 14
Bin 1
Input Voltage Tests, VIX
• Test objectives:
• to screen for defects that alter the switching characteristics of the device
input buffers (thus, preventing the buffers from performing as designed)
• The VIX testing verifies that the input buffers can properly translate a
valid input voltage to the correct logic level.
• VIL is the max-voltage applied to an input to represent logic 0, while
• VIH is the min-voltage to represent logic 1
Parameter
Description
VIH
Input High
Voltage
VIL
Input Low
Voltage
Test
conditions
Min
Max
2.2
Units
V
0.8
V
Input Voltage Tests, VIX
What is actually being tested in Input Voltage Tests?
Input Voltage Tests, VIX
• How to conduct VIX Test?
Check the device
specifications !
• This test is performed by applying the specification-defined input levels, and then executing a
functional pattern.
• For the functional pattern, it use the SAMPLE/PRELOAD instruction in boundary scan DFT feature
• Pin data are captured in parallel into boundary scan register and shifted out serially through TDO.
The difference between an
input high voltage test and an
input low voltage test is really
dependent on whether a one
or zero was captured into the
boundary scan register during
CAP-DR state.
Input Voltage Tests, VIX
• How to conduct VIN Test?
1.
2.
3.
4.
Set the input levels as per the spec
Execute the test, relaxing all the parameters/frequency
Monitor output signals during test
Functional pattern will fail if any output level is different from expected
• Note : Input voltage tests do not exercise any core functionality and only exercise boundary scan
logic. It tests whether the input buffers can correctly translate an input voltage as a valid high or
logic level.
VOH Spec
Comparator
Test Levels
PASS Logic One
FAIL
VOL Spec
PASS Logic Zero
Input Voltage Tests, VIX
 With refer to EXTEST Example, we want to test VIX on
chip#2 using SAMPLE/PRELOAD instruction
 Please modify TMS/TDI/TDO sequence for chip#2
with
 IR Register=4 bits, DR Register = 8 bits.
 Assume only has chip#2 during test
 Start with VIL
THINK!
Initialize TAP
TMS
TDI
TDO
Final state
Load Instruction
11111
01100*
Test logic state
Shift-IR
Capture
TMS
TDI
TDO
Final state
110
Run-test/Idle
Scan Out
10
0
Capture-DR
110
Shift-DR
SAMPLE/PRELOAD Example Instructions
Instruction
Run-test/Idle
B3
B2
B1
B0
Register Selected
0
0
0
0
EXTEST
Boundary-Scan Register
0
0
0
1
SAMPLE/PRELOAD
Boundary-Scan Register
0
0
1
0
IDCODE
ID Register
0
1
0
0
HIGHZ
Bypass
0
1
0
1
CLAMP
Bypass
0
1
1
0
ENABLE_ONCE
OnCE Register
0
1
1
1
DEBUG_REQUEST
OnCE Register
1
1
1
1
BYPASS
Bypass
Output Voltage Tests, VOX
• The purpose of output voltage (VOUT) testing
• to screen for manufacturing defects or process shifts that degrade the DC drive
capability of the output buffers.
• Output voltage tests the DC drive capability of both output high and output low voltages with boundary scan.
Parameter
Description
VOH
Output High
Voltage
VOL
Output Low
Voltage
Test
conditions
Min
Max
2.4
Units
V
0.4
V
Output Voltage Tests, VOX
What is actually being tested in Output Voltage Tests?
Output Voltage Tests, VOX
• How to conduct VOX Test?
• This test is performed by applying the specification-defined input levels, and then executing a functional pattern.
• For the functional pattern, it use the EXTEST instruction in boundary scan DFT feature
• Pin data are captured in parallel into boundary scan register and shifted out serially through TDO. Preloaded data are driven
out to output pins during the UPDATEDR or UPDATE-IR state of the EXTEST instruction.
Output Voltage Tests, VOX
• How to conduct VOX Test?
1.
2.
3.
4.
Set the output levels as per the spec
Execute the test
Check the output
Functional pattern will fail if the output level does not meet the
specification
• Note : Output voltage tests do not exercise any core functionality and
only exercise boundary scan logic.
OPENS AND SHORTS TEST
Functional Method
• How to conduct the Functional Test
• Active Load/Functional Comparator can be used to performs Opens/Shorts Test
• Negative/Positive Current will forward biased the Vss/Vdd Protection Diode
• Digital output of each pin will be compared
OPENS AND SHORTS TEST :
Functional Method
Have
Fun!
• How to conduct the Functional Test (Tips below!)
1. Pre-condition the pins
Drive 0.0V at all power pins ( Vdd, Vss, etc) and Input/Output pins
except the Pin Under Test
2.
Set the parameter :
VOL, VOH, Vref, Isrc, Vsrc
Set 𝑉_𝑂𝐻=1.5𝑉 , 𝑉_𝑂𝐿=0.2𝑉; 𝐼𝑠𝑟𝑐= 0.1mA, 𝑉_𝑟𝑒𝑓=3.0𝑉
3.
Define the Pass/Fail(Open,Short) condition when pin under
test
•
•
•
Pass: If the received vector at pin under test is Z (HiImpedance),it passes for Open/Short Test.
Short: If the comparator sense a output low “L” (less than
0.2 V), pin has Short
Open : If the comparator sense a output high “ H” (more
than 1.5V ), pin is Open.
4. Similarly, all other pins of DUT will be tested with the
pattern
Walking Patterns
Walking
Patterns?
?
Summary/Q&A
• Opens and Shorts Test
• VCC Continuity
• Leakage Test
• Standby Current (ISB/SICC)
• DFT – JTAG
• Boundary Scan in IO tests
• Input Voltage Tests
• Output Voltage Tests
I/O Testing, I/O DFT and
I/O Design Verification
(DV) fundamentals
(DAY 3)
Introduction
Communication Protocol
• What is a serial communication protocol?
• It’s a way of transmitting data in a line, one data after the other
Example : Send 198 11000110
Parallel Communication
Send 198 11000110
•
•
•
•
•
TX – RX
Send high pulse for 1, low for 0 in parallel
All bits are send together! Done in 1 clock!
Downside : Use 8 connections + ground reference = 9 cables.
This is for 8 bit, imagine you want to send a 16 bit data
Serial Communication
• Use 1 cable, and send the data serially
• Downside : 16 bits of data, would required 16 clocks to send the data
vs only 1 clock for parallel. 16x slower!
• Serial is slower
• Example : UART , I2C, SPI, JTAG, USB, …..
Serial Communication
Synchronous/Asynchronous
• Synchronous uses the clock to send the data on a specific speed &
time.
• Asynchronous doesn’t have a clock
Serial Comm – Async - UART
• UART - Universal Asynchronous Receiver-Transmitter
• Use 1 TX and RX wire; 1 ground reference
• Transmitter – TX, Receiver – RX
• The transmitter start sending bits whenever it wants
Serial Comm – Async - UART
• Common configurations needed between TX & RX to ensure both
works in the same settings
• Transmission speed
• Data Length
• START and STOP bits
Serial Comm – Async - UART
• Example 198 11000110
• We know the data length : 8 bits  So both TX & RX need to have this
configurations
• Start bit represents by a low pulse  Easy for receiver to detect when the
data start
Serial Comm – Async - UART
• Common is 9600 bauds/second
• Length of the bit = 1/9600 = 104uS
Serial Comm – Sync
I2C Protocol
• Required 2 connections :
• One wire will send the data – SDA
• 2nd wire is the clock –SCL
• Need to know
• Frequency : work up to 400kbits/s
• Method:
• The direction of the transfer is controlled by a special bit called ACK which is inserted
after every 8th transmitted bit.
• After every 8th bit, the receiver (either slave or master) will transmit 0 (ACK) or 1
(NACK) back to the transmitter.
• ACK means the transmission was received successfully, while NACK means the
transmission was not received or the receiver could not process the data.
I2C Protocol
• To start a transmission, SDA is set low while SCL is kept high. This indicates the start of a transmission. Only a master
device can start transmission.
• A 7-bit address is transmitted by the master. This address is used to select the slave device.
• A single R/W bit is transmitted. This is used to determine whether it is write (master-to-slave) or read (slave-to-master).
• The slave replies with a single ACK (or NACK) bit. If ACK bit was received, the transmission can proceed.
• Depending on whether the R/W bit was 0 or 1, the master or slave will start transmitting data. The data is transmitted in
8-bit packets. After every 8th bit, there is a ACK/NACK bit from the receiver.
• Transmission ends when the transmitter drives SDA high when SCL is high.
I2C
Add : 68
•
•
•
•
With I2C, the TX can send all kinds of data but only certain RX will receive the values
We do that with the use of slave address
Each receiver will have a different slave address
So, the transmitter will first send the address
• Eg: Add 68, then it will send the data ( Slave 1 example ) Only the receiver with address 68 will
store the data in its buffer
• The communication is 1:1 communication
• But, I2C can be use for multiple receiver
I2C Bus - Summary
• Inter-Integrated Circuit (I2C) is a 2-wire bus for low-speed communication between IC devices.
• It consists of 2 wires only: SCL and SDA.
• SCL is the clock signal. Basic I2C specification is able to support between 100-400kHz.
• SDA is the data signal. This is a bi-directional wire; both master and slave is able to transmit. The
direction of the transfer is controlled by a special bit called ACK which is inserted after every 8th
transmitted bit.
• After every 8th bit, the receiver (either slave or master) will transmit 0 (ACK) or 1 (NACK) back to
the transmitter. ACK means the transmission was received successfully, while NACK means the
transmission was not received or the receiver could not process the data.
I2C EXAMPLE:
READING DEVICE ID from IDT 8T49N287
• Step 1: Tester start transmission by driving SDA high while SCL is high.
• Step 2: Transmit the device address + RW bit =W.
• Step 3: Transmit the register address. For device ID, register address is 0x0002 – 0x0004. Transmit the
address of the first register. MSB = 0x00, LSB = 0x02.
• Step 4: Issue a repeated start (Sr) by doing the same thing as in Step 1. Repeated start is a special cycle used
when performing a read following a write.
• Step 5: Repeat Step 2, but set RW bit = R, instead of W.
• Step 6: Read the data from device. The first 8 bits (Data 0) should be register 0x0002, second 8 bits register
0x0003, and third 8 bits 0x0004.
• Step 7: Tester end transmission by driving SDA high while SCL is high (same as steps 1 and 4).
SPI Bus – Serial Peripheral Interface
• 4 wires
•
•
•
•
SCLK is the clock signal. This can be from 1-2 MHz, up to over 100MHz
MOSI which is the master output slave input
MISO which is master input, slave output
SS(Slave Select) is driven to 0 when data is transmitted by MOSI/MISO, else set to 1 if no data
transmitted. If multiple slave devices are connected the same SPI Bus, there will be dedicated
SS pins for each slave.
• One master as Transmitter, slave to receive the data, RX
SPI Bus – Serial Peripheral Interface
•
•
•
•
The MOSI wire will send the data to the slave
But the master also can receive data from the slave using MISO wire
In this case, we don’t use the slave address as in the I2C
Instead of that, we have the Save Select(Chip Select)
SPI Bus – Serial Peripheral Interface
• To start a transmission, the Master will put the chip select pin to Low
• Then, we send the clock and the data signal
• If you want to more slave devices, connected, you will need a chip select
connection for each one.
• The transmission speed for SPI is way higher than I2C for wired communication
and at the same time, the power consumption is also lower
SPI Bus - Summary
• Serial Peripheral Interface (SPI) is a 4-wire bus commonly used to program
registers on a device.
• It consists of 4 wires: SCLK, MOSI, MISO and SS.
• SCLK is the clock signal. This can be from 1-2 MHz, up to over 100MHz.
• MOSI (Master-Out-Slave-In) is the data signal from master to slave.
• MISO (Master-In-Slave-Out) is the data signal from slave to master.
• SS (Slave Select) is driven to 0 when data is transmitted by MOSI/MISO,
else set to 1 if no data transmitted. If multiple slave devices are connected
the same SPI Bus, there will be dedicated SS pins for each slave.
SPI timing diagram
SPI Example: WRITE to reg 0 IDT 8v97051
• Step 1: Set SS (nCS) to low to indicate the start of the transmission.
• Step 2: Transmit the data to be written on MOSI (SDI). One bit is
transmitted per clock cycle, from D31 to D0.
• Note; To write to Register 0, bits D2,D1,D0 has to be set to 0.
• Step 3: Set SS to high to indicate the end of the transmission.
Step 3
Step 1
Step 2
UART – I2C - SPI
Break
Importance of I/O Design Validation
I/O DV Parameters
2 main categories:
• DC parameters
• AC parameters
DC Parameters
• DC Tests verifies the device DC current and voltage parameters
• DC Parameters are tested by
• forcing current and measure voltage against limit
• forcing voltage and measure current against limit
• Verify the resistivity of silicon
• Some DC Parameters
• VIL/VIH, VOL/VOH, Impedances
DC – Levels (VIL/VIH)
Familiar?
DC – Levels (VIL/VIH)
DC – Levels (VOL/VOH)
DC – Levels (VOL/VOH)
Characterizing VIX /VOX
• Pattern Requirement
• DC implies ‘steady state components’  so Boundary Scan patterns are
preferred here.
• Functional patterns toggling I/O is not recommended
• Bus speed is kept as low as possible to avoid AC noise arising from other
sources
EXTEST VOH
Characterizing VIX /VOX
• Before starting DV data collection – shmoo the devices across operating ranges (voltage vs frequency )to
make sure pattern is robust and data is repeatable.
• Either Linear or Binary search algorithm can be used in finding VIX/VOX but former is time-consuming.
Shmoo?
Linear Search?
Binary Search?
Info : Shmoo Plots
• Plot : Display result/response of DUT over a range of conditions
• Each box = 1 test point (1 test condition)
• Analyse the operating region
•
•
Red = Fail Region
Green = Passing Region
• Nail down the electrical failures in a circuit under test.
• Types :
• One line shmoo
• 2 dimensional
• 3 dimensional
Shmoo Types (Example)
Normal
Wall Shmoo
Floor Shmoo
Characterizing VIX /VOX
Sporadic holes
* Indicate
Pass
Characterizing VIX /VOX
• Example code
Linear/Binary Search
Linear Search:

Similar to 1 line shmoo

Search from left to right, step by step
Binary Search:

Similar to 1 line shmoo

Search for most left & most right, then middle
of the range. Repeat until found the transition
of pass/fail
Impedance measurement
Impedance Measurement requires PMU
block in TP where boundary scan pattern is
used for pre-conditioning.
After pre-conditioning, specific device pin is
connected to the ATE PMU and
measurement is done through either VSIM
(force voltage measure current) or ISVM
(force current measure voltage).
Impedance Compensation
• Make sure impedance matching is essential for high speed I/O.
• Due to process, voltage and temperature (PVT) variations
Impedance Compensation
• Trim (fuse) comp code to DUT.
• Passive trim
• Active trim
• How would you verify impedance compensation is working on
silicon?
Break
AC Test
• AC Test verifies the AC specifications which includes quality of output signal and signal
timing parameters
• Clocking schemes
• Common Clock (CC)
• Source Synchronous (SS)
• AC Parameters
• Setup/Hold Time
• Propagation delay
• Rise/Fall Time/Frequency/Duty cycle/Pulse width
• Output Signal Quality
• Differential Signal
• Eye diagram & Jitter
AC – Clocking Scheme
• Common Clock (CC)
 1st clock, CLK A : Data out from Transmitter propagate to Receiver
 2nd clock, CLK B : Data latches in at the Receiver
• Example : Data signal TXRX : 2km, CLK A/B trace : 2cm. Think: What happen at the 2nd clock?
AC – Clocking Scheme
Common Clock (CC) Timing
Pro : Each agent knows the state of the bus on a cycle-by-cycle basis
Cons : Limitation on lengths of the transmission lines of the clock signals and the data
signal
AC – Clocking Scheme
• Source Synchronous (SS)
 The transmitter IC sends the DATA signal after some delay, by the clock signal
 The receiver latches the data signal on the edge of the clock signal.
AC – Clocking Scheme
Source Synchronous (SS) Timing
Pro : Latency is removed from the frequency equation.
Cons : Latency increase
AC – Parameters (CC)
CC Timings: Input Timings (Tsetup)
Tsetup = Time that data must be present before rising edge of clock
AC – Parameters (CC)
CC Timings: Input Timings (Thold)
Thold = Time that data must be present and stable after rising edge of
clock
AC – Parameters (CC)
CC Timings: Output Delay Valid
Tcomax = Maximum Tco such that a system will function when device
drives.
AC – Parameters (CC)
CC Timings: Output Delay Valid (Tcomin)
Tcomin = Minimum Tco such that a system will function when device drives.
AC – Parameters (CC example)
AC – Timing
SS Timings: Input and Output Timings
• For SS pins input timings are measured w.r.t SS-clock, which is the
strobe pin’s edge (or cross points of strobe pins).
• Output timings for SS pins are defined relative to the output of strobe
pins:
Pattern Requirement for I/O AC Timing
• Worst Case I/O(WCIO) patterns to test transmitters and receivers.
• Consideration for worst case pattern
• DC Balance
• Settling Time, reach equilibrium
• Pathological Pattern
• Pseudorandom binary sequence (PRBS) is equivalent worst case and
more likely to occur in practice.
• PRBS 7 -> X7+X6+1 (127bits)
1000001100001010001111001000101100111010100111110100001
1100010010011011010110111101100011010010111011100110010
10101111111000000
Differential Signaling
•
•
•
•
Uni-directional - outputs and inputs
Fully-differential signalling, no Vref
A lane is one TX/RX pair = 4 pins
Point-to-point, TX -> RX
Jitter
• The deviation of actual timing compared to ideal timing of an event.
• Deterministic Jitter (DJ)
• Random Jitter (RJ)
• Total Jitter (TJ) TJ = DJ+RJ
Jitter
• Ideal signal vs jittered signal
Jitter
• Motivation to Measure and Separate Jitter
• Improve signal quality
• Achieving an acceptable BER at the receiver
• Bit Error Rate(BER)
•
•
•
•
•
Error bit over total received bits
Measurement of communication channel performance
Jitter contributes to BER
Typically BER, 10e-12
Below example shows 3 error bit at Receiver. BER = 3/10 = 0.3
Transmitter
1 0
1
1
0
0
0
1
1
1
Receiver
1 0
0
1
0
1
0
1
1
0
Jitter
• Why Jitter needed to be minimized?
• Ex :
EYE Diagram
• What makes up an eye diagram?
• Why do want to use it?
Think
Eye Diagram
• Eye Diagram are helpful in testing the physical layer fidelity of signals in clock
signals and serial data
• So what it is? It is a layered view of each of the different bit transition
combinations and there are 8 of those in total.
• So, this provides a composite picture of the overall quality of the physical
characteristics like amplitude variations, timing uncertainties and infrequent
glitches
Eye diagram – The real thing..
Example : NRZ vs PAM 4 signal
• NRZ, Non-return to zero vs PAM4, four-level pulse amplitude
modulation.
• Why does the industry need PAM 4?
177
Test Method
Analogue Signal Test
Method
• Transmitter
• Program transmitter to output signal
• Capture signal with digitizer
• Post process the data to find eye width, height and jitter
• Receiver
• Program receiver to ready state
• Source worst case signal/pattern with arbitrary waveform
generator (AWG)/Digital card
• Shift out data from receiver to compare result.
• Improvement needed when I/O speed increases.
Test Method - Cons
• Limited digitizer/AWG channel per tester.
• Relay introduced. Hence, maintenance cost increases.
• Digitizer/AWG cost increases significantly and not sustainable with
HVM environment.
• Load board path length too long.
• Not testing the actual scenario.
Test Method - Loopback
• Loopback is introduced.
•
•
•
•
•
•
Shift cost from test to design phase.
Transmitter: Add pattern generator.
Receiver: Add pattern comparator.
Relay is removed.
Digitizer/AWG no longer needed.
Load board path is adjustable to actual scenario.
Test Method - Loopback
• Becomes a digital test!
• But the circuit becomes complex and pattern becomes longer.
• Test engineer required to work closely with DFT (Design For Test)
engineer.
•
•
•
•
•
Understand high level circuit.
Understand pattern structure and capture required results.
Post process data if needed.
Search test is done by sweeping though DUT’s register.
Calibrating DUT’s DLL is needed when pattern comparator mismatched.
At the end…
• The primary objective of IO testing and DV is to make sure no
DEFECTIVE units are shipped to customers.
• Other objectives include improving test time, efficiency, and yield.
• Today, SERDES speed is exceeding 28Gbps and 56Gbps is on the
horizon.
• Suggested reading: An Engineer's Guide to Automated Testing of
High-Speed Interfaces, Second Edition by Jose Moreira, Hubert
Werkmann.
Backup
Input Signal
Output Signal
Propagation Delay
• Propagation delay time is the amount of time that it takes for a change in an input signal to produce
a change in the output signal measured at a specific voltage level.
• Propagation delay measurements are made from an input pin to an output pin.
Transition Time
• The time that the output logic take to change from one
state to another is called transition time.
• Transition time has two components…
• Rise time (tr)
• Fall time (tf)
• Rise Time - The time required for an edge to go from (typically) 10% to 90% of its high limit voltage
value
- The time required for an edge to go from (typically)
90% to 10% of its low limit voltage value
• Fall Time