TP44400NM
TP44400NM – 400 mΩ, 650V GaN HEMT With Integrated Driver and Protection
1.0 Features
● 650V HEMT with integrated driver
● 400 mΩ RDSON, zero reverse recovery
● 5V PWM input
● Low quiescent current driver
● UVLO protection
● Dv/Dt immunity without driver supply
● Adjustable turn-on slew rate
● Low propagation delay for up to 2MHz operation
(Top view)
(Bottom View)
Figure 1 Device Image
(22 Pin 5×7×0.85 mm QFN Package)
2.0 Applications
● As switching FET in singles and in pairs as half-bridges
● AC-DC, DC-DC, DC-AC Converters
● PFC application (totem pole and standard)
● High frequency LLC converter
● Mobile chargers and laptop adapters
● LED and motor drives
● Server power supplies
RoHS/REACH/Halogen Free
Compliance
3.0 Description
The TP44400NM is a 400mΩ, 650V GaN HEMT device with
integrated driver on the same die. Monolithic integration of driver
minimizes inductance in the gate loop, enabling safe and clean
switching of GaN HEMT even at high-voltage high-frequency
operation. This makes the application circuit more efficient and
reliable, and reduces the size of the magnetic components. UVLO
function of the device turns-off the HEMT in case VDD voltage droops
below its threshold voltage. A proprietary Dv/Dt protection circuit
protects the HEMT from drain-dvdt induced false turn-on even in the
absence of VDD supply. An external resistance placed between Vreg
and RG allows control of drain slew rate for best EMI performance.
Figure 2 Functional Block Diagram
4.0 Ordering Information
Table 1 Ordering Information
Base Part
Number
Package Type
Form
Qty
Reel
Diameter
Reel
Width
Orderable
Part Number
TP44400NM
22 Pin 5×7×0.8mm
QFN
Tape and Reel
1000
13” (330mm)
18mm
TP44400NMTRPBF
Evaluation Board
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TP44400NM-EVB
Page 1 of 14
TP44400NM
5.0 Pin Description
Table 2 Pin Definition
Pin Number
Pin Name
Pin Type
1, 7~20
NC
2
3
VDD
Vreg
LV-PWR
AO
4
RG
AI
5
PWM
DI
6
GND
GND
21
22 (Back Pad)
Drain
Source
HV-PWR
Description
No connect. Pins 8-20 can be connected to GND for better PCB
layout. Other pins should be left open
Supply for driver. Connect 7.5V with a ≥100nF bypass capacitor
Internally generated supply. Connect a ≥10nF bypass capacitor
Connect a suitable resistor between RG and Vreg for controlling the
drain voltage slew rate during the turn on.
PWM input
Ground pin of the driver (internally Kelvin connected to the source of
the 650V GaN HEMT)
Drain of 650V GaN HEMT
Source of 650V GaN HEMT
Note: The backside ground (thermal) pad of the package must be grounded directly to the ground plane of PCB
with multiple vias to ensure proper operation and thermal management.
6.0 Absolute Maximum Ratings
Table 3 Absolute Maximum Ratings @TA=+25°C Unless Otherwise Specified
Parameter
Symbol
Value
Unit
VDS,max
VTDS,max
IDS,max
IDSpulse,max
IDSpulse,max
VDD
VPWM
VPWM(Transient)
Tst
650
750
4
8
6
8.0
6.5
9.0
-55 to +150
V
V
A
A
A
V
V
V
TJ
+150
°C
°C
2.0
45
260
°C/W
°C/W
°C
Level 1C
Level C3
1000 to <2000
≥1000
V
V
MSL
1
-
Electrical Ratings
Drain to Source Voltage
Transient Drain to Source Voltage
Continuous Drain Current (at Tc = 100 °C)
Pulsed Drain Current (at Tj = 25 °C)
Pulsed Drain Current (at Tj = 125 °C)
VDD Supply Voltage
Input PWM Voltage
Transient Input PWM Voltage
Storage Temperature Range
Maximum Junction Temperature
Thermal Ratings
Thermal Resistance (junction-to-case) – Bottom side
RθJC
Thermal Resistance (junction-to-ambient)
RθJA
Soldering Temperature
TSOLD
ESD Ratings
Human Body Model (HBM)
Charged Device Model (CDM)
Moisture Rating
Moisture Sensitivity Level
Attention:
Maximum ratings are absolute ratings. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability. Exceeding one or a combination of the absolute maximum ratings
may cause permanent and irreversible damage to the device and/or to surrounding circuit.
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TP44400NM
7.0 Electrical Specifications
Table 4 Electrical Specifications @TA=+25°C Unless Otherwise Specified; VDD=+7.5V; RG=0Ω
Parameter
Description
RDSON
Drain to source
resistance
IDSS
Drain to source
leakage current
COSS
Output
capacitance
QOSS
Output charge
QRR
Reverse recovery
charge
VSD
Reverse
conduction voltage
VDD
Iq
Isw0
Supply voltage
Quiescent current
Vreg
VUVLO-High
Regulated voltage
UVLO threshold
while rising
UVLO threshold
while falling
UVLO hysteresis
PWM input
voltage to turn on
PWM input
voltage to turn off
VUVLO-Low
UVLOhyst
VIH
VIL
Switching Current
Condition
650V GaN HEMT
IDS=0.5A DC
IDS=0.5A DC, TJ=+150°C
VDS=650V, VPWM=0
VDS=650V, VPWM=0,
TJ=+150°C
VDS=100V, VPWM=0V
VDS=400V, VPWM=0V
VDS=100V
VDS=400V
Minimum
Typical
Maximum
400
960
0.1
mΩ
μA
10.0
22
8
4.4
8
ISD=1A, VPWM=0V
ISD=3A, VPWM=0V
Driver
pF
nC
0
nC
2.3
3.6
V
7.5
2.0
VDS open, VPWM=0
VDS open,
VPWM switching at 1 MHz
VDS open, VPWM=0
8
6.0
VDD =0V to 7.5V
4.9
VDD=7.5V to 0V
4.3
VDD = 6.5V to 8.0V
V
mA
V
V
V
0.6
VDD = 6.5V to 8.0V
Unit
3
V
V
V
0.7
DVDT Immunity
dv/dtno-VDD
Max drain voltage
dv/dt under no VDD
tr
Rise time
tf
Fall time
tprop-on
tprop-off
Turn on
propagation delay
Turn off
propagation delay
Revision 1.1 - 2020-11-20
VDD =0V
Switching Time
VDS=400V, IDS=2A, RG=0Ω
VDS=400V, IDS=2A,
RG=0Ω, TJ=+150°C
VDS=400V, IDS=2A, RG=0Ω
VDS=400V, IDS=2A,
RG=0Ω, TJ=+150°C
VDS=400V, IDS=2A, RG=0Ω
VDS=400V, IDS=2A,
RG=0Ω, TJ=+150°C
VDS=400V, IDS=2A, RG=0Ω
VDS=400V, IDS=2A,
RG=0Ω, TJ=+150°C
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200
V/ns
14
15
ns
5
8
ns
18
20
ns
25
27
ns
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TP44400NM
8.0 UVLO Function
8.1 Description
UVLO (Under Voltage Lock Out) block controls the driver functionality. When the VDD voltage is not at the
right value, the 650V GaN HEMT can have higher losses and eventually overheat and breakdown.
Hence, for VDD below UVLO threshold, the driver turns off the HEMT device and the PWM signal is
ignored. But, when the VDD voltage is in the safe region as shown in Figure 3, then the driver turns on
and off the device according to the PWM input applied to the driver.
Figure 3 UVLO Timing Block Diagram
8.2 DVDT Immunity Function
Large dv/dt at the drain pin are normal during the operation of converters. Such dv/dt may arise due to
the usual switching actions, or due to the first-time hook-up of the converter system to the main supply
of the power-stage. A positive dv/dt on the drain (with respect to the gate/source) will try to turn on the
HEMT device through the parasitic gate to drain capacitance Cgd. This parasitic turn-on is undesirable,
and might even cause catastrophic amount of shoot-through or crowbar current.
Usually the driver is able to keep the HEMT off in the face of such dv/dt events, but for this to work
properly, the driver requires its own supply to be up and steady. However, in many cases, the driver
supply is derived from the main supply, and hence at the first-time hookup of the main supply, the HEMT
device might parasitically turn on.
The DvDt immunity function of TP44400NM device is a proprietary design which keeps the HEMT
immune to such dv/dt induced parasitic turn-ons. To be noted is that this function works irrespective of
usage of the device either as a low-side FET or a high-side FET.
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TP44400NM
8.3 Adjustable Turn-On Slew Rate Function
An adjustable slew-rate of the drain voltage during turn-on is a useful feature which helps control EMI
and limits the magnitude of ringing on the switch node in a converter. For this feature, TP44400NM uses
an external resistor Rg of user selectable value between the pins RG and Vreg as shown in Error!
Reference source not found.. A typical plot of slew rate versus Rg value has been shown Error!
Reference source not found.. It shall be noted that the switching-time numbers given in Table 4 are for
the default value of Rg = 0 Ω.
9.0 Switching Time Measurement Information
The switching time is measured using the test circuit shown in Error! Reference source not found..
The TP44400NM is connected to a 7.5V DC supply for the driver to operate properly. A resistor of 0 Ω is
connected between RG and Vreg. The drain of 650V HEMT is connected to a 400V DC bus supply with an
inductive load.
When the PWM pin is supplied with a 5V pulse, the device turns on and the drain to source voltage (VDS)
goes down as shown in Error! Reference source not found.. During this time, the inductor current starts
to increase. When the PWM signal goes down, the device turns off and hence VDS starts to increase with
the slew rate depending on the inductor current. The drain to source voltage VDS gets clamped to the DC
bus voltage because of the clamp diode, and the diode will conduct till the inductor current reaches zero.
The rise and fall times, and the propagation delays of PWM are defined as shown in Error! Reference
source not found.. The propagation delay to turn on the device is defined as the time from 50% of PWM
rising edge to VDS falling by 10% of the dc bus voltage at the given current. Similarly, propagation delay
to turn off is defined as the time from 50% of PWM falling edge to VDS rising by 10% of its bus voltage at
the given current.
The rise time tr is defined as the time it takes VDS to go from 10% to 90% of the bus voltage during rising
edge at the given drain current, while the fall time tf is defined as the time it takes VDS to drop from 90%
to 10% of the bus voltage during the falling edge at the given drain current.
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TP44400NM
Figure 4 Switching Time Measurement Circuit
Figure 5 Switching Time Waveform
10.0 Typical Characteristics
Conditions: @TA = +25°C, VDD = +7.5V, Rg = 0Ω, unless otherwise specified.
10
12
9
10
8
7
ISD (A)
IDS (A)
8
6
4
6
5
4
3
2
2
1
0
0
2
4
6
8
0
VDS (V)
2
4
6
8
VSD (V)
Figure 6: Forward Conduction of 650V HEMT IDS vs.
VDS @ VDD=7.5V
Revision 1.1 - 2020-11-20
0
Figure 7: Reverse Conduction of 650V HEMT ISD
vs. VSD @ VDD=7.5V
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TP44400NM
700
1000
650
800
550
Rdson(mΩ)
Rdson (mΩ)
600
500
450
600
400
400
200
350
0
300
0
5
10
15
-50
0
ID (A)
50
100
150
Temperature (C)
Figure 8: RDSON vs. IDS @ VDD=7.5V
Figure 9: RDSON vs. Temperature @ VDD=7.5V
3.50
70
3.00
50
Coss (pF)
VDD current (mA)
60
2.50
40
30
20
2.00
10
1.50
0
0
500
1000
1500
2000
0
200
Frequency (kHz)
600
VDS (V)
Figure 10: Driver Supply Current vs. PWM
Frequency @ VDD=7.5V, VDS=0V
Revision 1.1 - 2020-11-20
400
Figure 11: COSS vs. VDS
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TP44400NM
10
1.8
9
1.6
8
1.4
1.2
6
Eoss (uJ)
Qoss (nC)
7
5
4
1
0.8
0.6
3
2
0.4
1
0.2
0
0
0
200
400
600
0
200
VDS (V)
400
600
VDS (V)
60
Slew Rate (V/ns)
50
40
30
20
10
0
0
100
200
300
400
Rg (Ohm)
Figure 14: Drain slew rate variation with Rg resistor
11.0 Application Information
The TP44400NM can be used in a half bridge configuration as shown in Error! Reference source not
found. for a generic buck or boost converter application. Two chips with integrated driver are used to
create a half bridge. The module requires proper driver bias supplies for its operation.
A regulated 7.5V supply is used for the low-side module, while a bootstrap configuration is used to
generate the boot voltage for the high-side module. The high-side module can also be supplied with a
regulated 7.5V supply derived from an isolated DC-DC converter (not shown here).
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TP44400NM
The PWM input signal to the low-side module can be directly fed from the PWM output of a controller or
a microcontroller (sitting on the low-side device ground), while the PWM for the high-side module can be
supplied through a digital isolator as shown in the figure. The digital isolator shall have sufficient immunity
against the expected high dv/dt rates of the switching node. The bias supplies for the primary and the
secondary sides of the digital isolator can be derived from the 7.5V supplies available on the two sides
using either low cost LDO (not shown here) or Zener diodes as shown in the figure.
Although, in Error! Reference source not found., the RG pin is shorted to the pin Vreg, one can also
use a non-zero valued gate resistor between these pins to control the turn-on switching time.
Figure 15 Buck Converter Application Circuit
12.0 Device Package Information
Figure 16 Device Package Drawing
(All dimensions are in mm)
Table 5 Device Package Dimensions
Dimension (mm)
Value (mm)
Revision 1.1 - 2020-11-20
Tolerance (mm)
Dimension (mm)
http://www.tagoretech.com
Value (mm)
Tolerance (mm)
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TP44400NM
A
b
D
D1
D2
e
E
E1
0.80
0.25
5.00 BSC
3.60
3.60
0.50 BSC
7.00 BSC
0.28
±0.05
+0.05/-0.07
±0.05
±0.05
±0.05
±0.05
±0.05
±0.05
E2
L
S1
S2
S3
S4
S5
-
3.20
0.40
0.625
0.91
0.70
0.425
2.80
-
±0.05
±0.05
±0.05
±0.05
±0.05
±0.05
±0.05
-
Note: Lead finish: Pure Sn without underlayer; Thickness: 7.5μm ~ 20μm (Typical 10μm ~ 12μm)
Attention:
Please refer to application notes TN-001 and TN-002 at http://www.tagoretech.com for PCB and
soldering related guidelines.
13.0 PCB Land Design
Guidelines:
[1] 4 layer PCB is recommended
[2] Via diameter is recommended to be 0.3mm to prevent solder wicking inside the vias
[3] Thermal vias shall only be placed on pad A
[4] The maximum via number for pad A is 6(X)×5(Y)=30
Figure 17 PCB Land Pattern
(Dimensions are in mm)
Non-Solder Mask Defined
(Preferred)
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Solder Mask Defined
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TP44400NM
Figure 18 Solder Mask Pattern
(Dimensions are in mm)
Figure 19 Thermal Via Pattern
(Recommended Values: S≥0.15mm; Y≥0.20mm; d=0.3mm; Plating Thickness t=25μm or 50μm)
14.0 PCB Stencil Design
Guidelines:
[1] Laser-cut, stainless steel stencil is recommended with electro-polished trapezoidal walls to improve
the paste release.
[2] Stencil thickness is recommended to be 125μm.
Figure 20 Stencil Openings
(Dimensions are in mm)
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TP44400NM
Figure 21 Stencil Openings Shall not Cover Via Areas If Possible
(Dimensions are in mm)
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TP44400NM
15.0 Tape and Reel Information
Figure 22 Tape and Reel Drawing
Table 6 Tape and Reel Dimensions
Dimension (mm)
A0
B0
D0
D1
E
F
Value (mm)
5.35
7.35
1.50
1.50
1.75
5.50
Revision 1.1 - 2020-11-20
Tolerance (mm)
±0.10
±0.10
+0.10/-0.00
+0.10/-0.00
±0.10
±0.05
Dimension (mm)
K0
P0
P1
P2
T
W
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Value (mm)
1.10
4.00
8.00
2.00
0.30
12.00
Tolerance (mm)
±0.10
±0.10
±0.10
±0.05
±0.05
±0.30
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TP44400NM
Edition Revision 1.1 - 2020-11-20
Published by
Tagore Technology Inc.
5 East College Drive, Suite 200
Arlington Heights, IL 60004, USA
©2020 All Rights Reserved
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characteristics. Tagore Technology assumes no responsibility for the consequences of the use of this
information, nor for any infringement of patents or of other rights of third parties which may result from
the use of this information. No license is granted by implication or otherwise under any patent or patent
rights of Tagore Technology. The specifications mentioned in this document are subject to change
without notice.
Information
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Technology: support@tagoretech.com.
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