CIT593 Summer 2021
Acceptable CircuitLab Diagram Formats
How to show Wire vs. No Wire of pMOS and nMOS gates:
1) Method 1: Simple wires with labels
a. To demonstrate that the gate is Open/Closed or Wired/Not Wired, make a
dashed square around the wire/lack of wire (note that the closed transistor
only has a vertical line connecting drain to source, and the line does not
connect to the gate). Transistor labels can be created using the Name
Node or Text Element feature.
Correct:
Incorrect:
2) Method 2: Use the modified CircuitLab MOSFET devices
1. Put the MOSFET object in your circuit.
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CIT593 Summer 2021
2. Double-click the object to open its settings; scroll to the bottom and under
DISP, select CMOS. Change the name of the device to its type (pMOS or
nMOS).
3. To show open/closed gates, connect the wire going through the gate and
label the gate as Open/Closed.
Open:
Closed:
As a general rule, however you draw your wired vs. no wired MOSFET gates, consider
what is straight forward for yourself and super clear to a stranger (grader) looking at
your diagram.
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CIT593 Summer 2021
Acceptable pMOS and nMOS gates for transistor-level diagrams:
1) The CircuitLab MOSFET devices or the simplified/modified MOSFET device (as
described in pages 1-2) are acceptable. Make sure to clearly label each
transistor and all input and output lines.
Acceptable transistor diagrams:
Multiple input logic gates:
1) Use a clearly labeled dashed box for any gates with more than 3 inputs.
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CIT593 Summer 2021
Inverters on PLAs:
1) There aren’t the simple circle inverters in CircuitLab like in lecture examples,
instead use the (admittedly clunkier) inverter gates, it’s okay if the inverters
overlap. Make sure to keep the ordering of the AND gates’ inputs consistent (A is
top input to logic gates, B is second input to logic gates, etc.).
•
The DON’Ts: Do NOT create separate inverted input lines in your PLAs and only
implement the rows of the truth table that produce a 1. Do not waste hardware by
adding logic gates that don’t have an output (like the bottom AND gate shown
below).
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CIT593 Summer 2021
Timing Diagrams in CircuitLab:
Because screenshots are not allowed during exams, it’s required that students draw
timing diagrams using standard document editing software (like Microsoft word) or
CircuitLab and export the image.
1) Gray arrows as time markers and wires for solid lines. Double-click on the arrow
to change colors in CircuitLab.
2) Gray dashed rectangle edges as time markers and wires for solid lines. Doubleclick on the dashed rectangle to change colors in CircuitLab.
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CIT593 Fall 2022
Detailed Examples for Acceptable CircuitLab Diagram Formats
If the question is asking to just show: transistor-level diagrams (cMOS gates circuits)
Acceptable Formatting
Using default MOSFET symbols
• clearly label each cMOS identity:
o i.e. pMOS / nMOS, p / n, p-type / n-type
• label input and output lines
• correctly connected wires
Using Modified MOSFET symbols
• clearly label each cMOS identity (i.e. pMOS / nMOS)
• label input and output lines
• correctly connected wires
Incorrect Formatting
Incorrectness: Missing cMOS labeling (need to change the
default text to pMOS/nMOS)
Incorrectness: Using box-symbol (instead of MOSFET symbol) to
represent each cMOS gate
CIT593 Fall 2022
If the question is asking to show:
1. transistor-level diagrams (cMOS gates circuits) and
2. OPEN/CLOSED status of each cMOS gates
Acceptable Formatting
Use Modified cMOS symbols
● Draw connection lines between drain & source
for CLOSED gate
● Label each gate as OPEN/CLOSED
● Label each gate for cMOS identities
● Figure Label (if question ask for more than one
figure)
Use box symbol with wire/no wire to represent
OPEN/CLOSED status
● (no need to relabel each gate as OPEN/CLOSED)
● Label each gate for cMOS
● Figure Label (if question ask for more than one
figure)
Figure Label: 2-input AND gate
Acceptable
Acceptable
Default MOSFET symbols are NOT acceptable choices for representing OPEN/CLOSED status (we don’t accept using it
for answering this type of question)
Incorrect (default MOSFET)
Acceptable (modified MOSFET)
Acceptable (box symbol)
CIT593 Fall 2022
Incorrect Formatting
●
●
●
●
●
•
Missing cMOS labels
Missing input/output lines or missing their labels
For using modified MOSFET symbol: CLOSED-gate doesn’t have Source-Drain Connecting Lines
Hand drawing or drawing another layer of no wire/wire on top of a screenshot of the cMOS circuit drawn from the
previous questions; students should be redrawing the diagrams
In question(s) asking for more than one figure: missing figure labeling
Mixing default MOSFET symbols with box-symbols in •
one figure
Missing boxes at each cMOS gate
CIT593 Fall 2022
Logic Gates with 4+ Inputs
CircuitLab supports logic gates to have at most 3 inputs. However, in some written homework assignments
students will be asked to draw circuits that may use logic gates with more than 3 inputs.
Acceptable Formatting
•
•
•
clearly label the type of each gate
number of inputs for the multi-input gates (i.e. gates
with more than 3 inputs)
Note: numbering gates is optional (ex. AND1, AND2,
AND3, AND4 can be all labelled as AND)
Incorrect Formatting
when wiring the 4th input into the subsequent gate,
make sure that you are connecting the input wire to
the gate and not to another input wire to the same
gate! As this represents a short circuit and you will
lose points on that problem.
CIT593 Fall 2022
If question asking to show: PLA (Programmable Logic Array)
Acceptable Formatting
Correct Features:
• clearly labelled input & output lines, clearly labelled gates
• when crossing over wires, they are not mistakenly connected (notice the little crossing-arches that step over any
underlining wires)
• input wires are not extruding over as free hanging wires at the bottom
Incorrect Formatting
●
●
●
missing the output line
input wires should not extrude out at the bottom
crossing wires are mistakenly connected
●
●
Output lines from AND gates should not be joined into 1 line.
should not use a 3-input-OR gate to handle 6 input lines. (should use
the dashed box)
●
crossing wires are mistakenly connected
●
missing gate labelling, using the wrong gate (NAND)
CIT593 Fall 2022
How to make “Grey Arrow” -- Timing Diagram
Step 1: select an “arrow” out
Step2: “Edit Parameters” à “color”à select grey
Step 3: duplicate the arrow(s) as needed
Step 4:
add label(s) onto the left side to indicate input(s) and
output(s) (ex. S, R, Q, Q’), then use the “wire” to draw signal
changes as solid line(s).
Lastly, if the question askes to identity actions: add a label to
the bottom of each slot.
CIT593 Fall 2022
How to make “Grey Dashed Rectangle”--Timing Diagram
Step 1: add a dash box as a rectangle
Step 2: change the rectangle color to grey
Step 3: duplicate the dashed rectangles
Step 4: add wires to seal the top and bottom boundaries,
and change the color to grey