A Brief Introduction to Ferroelectric Field Effect Transistor
化學所碩二
R09223159
陳重宇
Preface
I’ve been doing researches and conducting experiments on ferroelectrics-semiconductors
heterostructures for its application in photoelectrochemical catalysis as well as the ferroelectric
effects on the dynamics of excited hole-electron pairs as my graduate thesis theme. It was in 2020
that I first heard of ferroelectrics and its application in electronics in solid state physics course. Since
FeFET devices are considered as a promising and inevitable trend in the near future, I decided to dig
deeper in the basic principles buried in FeFET and its advantage over tradition MOSFET. I’ll elaborate
the fundamental physics of ferroelectrics (FE), the negative capacitance effect (NC), the evolution of
FeFET structures, its potential applications in nano-electronics and difficulties to be conquered. The
details of physics in domain wall switching, the transient negative capacitance effect, and the
derivation of analytical I-V characteristic across FE, source, drain, gate will be omitted for volume
reason, only several phenomenal observations will be described qualitatively.
What are Ferroelectrics? -Spontaneous Polarization
Analogous to ferromagnetics, ferroelectric is a not a
material with colligatively aligned magnetic moment but
spontaneous polarization which are quite well-aligned. The
spontaneous polarization arises from the tendency of
lowering the free energy by forming aligned polarization,
which is mainly a consequence of some atomic displacement,
that can be quantitatively described by the Ising model and
Landau’s theory of order parameter (here, the polarization).
The figure on the left2 is the energy landscape of a typical
cubic cell of oxide perovskite showing a character of
spontaneous symmetry breaking from cubic to tetragonal
along with spontaneous polarization. The energy landscape is
temperature dependent that the ferroelectric may
experience several phase changings while the temperature is
altered or reaching its Curie temperature that the energy
profile will become a simple parabolic curve with its global
minimum at zero polarization, just like typical ferromagnetics
does. By periodically stacking these polarized lattice cell, the
charging on the cell-to-cell interface is canceled and finally,
the charges on the bulk boundary remain un-relaxed and
result in a depolarization field across the bulk crystal from its upper to lower interface. The electric
field working on a ferroelectrics is described below in CGS unit:
𝑬𝑬 + 4𝜋𝜋𝑷𝑷
= 1 + 4𝜋𝜋𝝌𝝌
𝑬𝑬
, where ϵ is the relative dielectric constant, 𝑬𝑬 the macroscopic field resulted from the external
ϵ=
field, 4𝜋𝜋𝑷𝑷 the depolarization field, and nominator all together, the displacement field. The
susceptibility 𝝌𝝌 above can be further correlate to dielectric constant by
𝝌𝝌 =
𝑷𝑷 ϵ − 1
=
𝑬𝑬
4𝜋𝜋
The Negative Capacitance Effect-Interfacial Polarization Relaxation
The total energy of the ferroelectric is given by
F = F𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒 + F𝑓𝑓𝑓𝑓𝑓𝑓𝑓𝑓 𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒 + F𝑔𝑔𝑔𝑔𝑔𝑔𝑔𝑔𝑔𝑔𝑔𝑔𝑔𝑔𝑔𝑔
where electronic part of it is the energy caused by the surface charges that will be fully
compensated by stacking metal directly on both side of ferroelectric (FE) since metal has a really
large permittivity; the free energy part is the tendency of intrinsic organization that we described in
the previous section; gradient part is the non-uniformity of intrinsic polarization which arise from
surface relaxation or formation of antiparallel or in-plane-lying domains. Here, we assume the F
gradient to be zero (single domain), i.e., the polarization in the FE layer is uniform laterally and
alone the z-direction.The negative capacitance (NC) effect is a complicated phenomenon when a
ferroelectric is stacked with a high k dielectric as the figure above (Metal-Ferroelectric-DielectricMetal stack, MFIM). For dielectric layer (DE) which is too thin or having a low permittivity, the stack
will behave like a traditional Metal-Ferroelectric-Metal stack (MFM), showing a reduced energy
barrier to store energy but still adequately a ferroelectric capacitor. However, if it’s not the case, in
order to minimize the total energy of the MFIM stack, the energy stored by depolarization field in
DE layer and the free energy released by spontaneous polarization in FE layer encounters a
competition that make the system potentially swing between polarized and relaxed state. If the
energy store by depolarization field in DE layer will be higher than the gain of free energy in FE
polarization, the polarization near the FE-DE interface is than relaxed to zero polarization. But once
an external potential change VA disturb this subtle balance that alters the potential landscape giving
a preference of orientation in polarization. The spontaneous polarization will lead to a significant
depolarization field in DE layer, more than the voltage applied can contribute. This effect is known
as capacitance enhancement effect (j,k in the figure above showing the enhanced capacitance and
interfacial voltage than VA). In MFM stacks, the negative capacitor region is unstable that the
polarization will suddenly be flipped when the coercive voltage is reached, on the contrary, in MFIM
stack the negative capacitance region is reached every time without abrupt polarization flipping and
hysteresis. It’s critical to know that for both MFM and MFIM stack, the whole capacitance of whole
unit is always positive, the negative capacitance only exist when the polarization and the voltage
across the FE layer is in opposite direction.
Types of Domain Wall and I-V Characteristic of Their FeFET device
The abbreviation of “MD” and “SD” in the figure on the right stands for Multi domain and Single
domain. SD is the case we have
discussed in previous section, and
hard/soft MD config of ferroelectric is
hysteric and non-hysteric,
respectively, due to their different
response to external field. (Require to
reach coercive voltage to flip Hard
wall config but soft wall is easily
flipped). The SD type ferroelectric is a
result of limited dimension in three
direction, is relatively difficult to form
on bigger lateral dimension FET (the
scaling of gate must be small enough
to see SD, say, sub 5 nm).
It is obvious that for the SD or
soft wall MD, the drain current to
gate voltage I-V profile shows a
subthreshold swing SS below
60mV/dec. This is because of the NC
effect of FE gate. The SS has the expression below,
SS = ln(10)
𝐶𝐶𝑑𝑑𝑑𝑑𝑑𝑑𝑑𝑑𝑑𝑑𝑑𝑑𝑑𝑑𝑑𝑑𝑑𝑑
𝑘𝑘𝑘𝑘
(1 +
)
𝐶𝐶𝑂𝑂𝑂𝑂𝑂𝑂𝑂𝑂𝑂𝑂
𝑞𝑞
where the constant term in front is dominant by Boltzmann distribution and required to be 60.
However, if the oxide capacitance is negative, the SS will be negative. On the other hand, the drain
induced barrier lowering DIBL is negative, due to the negative output conductance effect (NOC)
a.k.a. negative differential resistance (NDR). The phenomenon is triggered by the enhanced drain
potential that induces the gate FE to experience relaxation or even polarization flipping, refraining
the channel current (figure e above). Both of these low SS and negative DIBL are symbols of good
on/off ratio and energy efficient component.
For the hard wall MD part, the hysteretic I-V profile is clearly shown. Although it has a different
mechanism for its NOC effect, the characteristic is still promising for application for 1T FeRAM due
to its asymmetric I-V profile that allow read/write to work without charge pumping circuit in
wordline. Also, the different current profile with 2 polarized states is a potential candidate for
components for neuron network in machine learning.(these IV characteristic are performed by
simulations and experiment by Saha et.al3,4,5)
Evolution of FeFET Structures and Emerging 2D Ferroelectrics
The FeFET structure gradually evolve from a to d7 in above structure to enhance memory
window10 and avoid domain wall pinning, which the later one is the major reason of FeFET
deteriorating that will be discuss later.
d
e
f
The 6 figures above are the layouts of different FeFET designs from the top gate configuration.
Bottom gate is widely used for research for its simple manufacturing. There is also side gate with
polymer (VDF-TrFE) as FE layer, nanowire as channel, which demonstrate a novel laterally polarized
FE gate8. Figure f shows a double gate with different purpose that working with different voltage,
one sub-coercive and one is above coercive voltage9, designed for neural computing. Another
emerging structure is using ferroelectric 2D material such as In2Se3 as channel material. Since the
gate control of the channel is always an issue and for ferroelectrics material, grains orientation and
sizes are difficult to control in fabrication, 2D materials are used as a solution.
Possible Applications
Besides the reduced power consumption by NC FET that we can expect to be realize in near
future, another promising application of FeFET is working as the synapse or the neuron component.
Figure b above shows that for figure a config, that differential current is made possible by sending a
positive or negative voltage pulse to the gate to poll the polarization state to different extent. The
analog operation is known as Erase-and-Program of the FET, which is a possible strategy of entitle a
single FET with “weight” to perform efficient neuromorphic computing11. For figure c above, is a
novel design (the double gate one in previous section) that when working as a synapse under
different working temperature, which is easily reachable in modern CPU, the post-synaptic current
(PSC) significantly diverges by 2 to 3 order of magnitude that affect the long-term depression (LTD)
and potentiation (LTP) in neuroplasticity. Additionally, FeFET is also a candidate for nonvolatile
memory (NVM) in CPU to fill up the gap between DRAM/SRAM and NAND flash with intermediate
endurance and speed. At last, there are more application such as nonvolatile logic (NVL), in-memory
computing, analog signal processing, frequency multiplication for frequency-shift keying (FSK)12,
random number generation, etc. There are too many potential applications to address here.
The Difficulties Remained to be Conquered
The ferroelectric based application in
electronics had been proposed for quite a
while. Although, Fe-FET structure was first
proposed in 195713, commercializing is hard
because of its short retention time. The two
major reason of this are the gate leakage
current and the depolarization field. The
polarization exerts a depolarization field on
interfacial dielectric and the semiconductor,
resulting a potential drop and the band bending respectively. After a certain amount of read/write
or program/erase actions, these lead to charge trapping at the ferroelectric insulator /
semiconductor interface as well as domain pinning, which stops the pinned domain from flipping
overtime and make the polarization to drop as the above figure depicts14. The figure15 below shows
the potential mechanisms of leaking current and interfacial charging. Apparently, these mechanisms
will lead to unwanted threshold voltage VT shift and destruction of memory states. The
deteriorating mechanisms described above are critical for enhancing the endurance of FeRAM and
FeFET. Currently, FeRAM has an endurance of ~1010 cycles and FeFET has an endurance above 105,
which is still far from the expected endurance of 1015. (Although commercial FeRAM with PZT (lead
zirconium titanate) has an endurance of ~1015, the scaling of this FeRAM is difficult that PZT
deposition is to blame, leading to low memory density. Alternatively, HfO2 based FeRAM/FeFET is
proposed, which is the case mentioned above.) The electronic society has put lots of effort in
improving the endurance by different structure, adding passivation layers or processes, or even has
the channel layer change to conquer these problems. Hopefully, we can probably expect to see
these techniques commercialize in the near future.
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