VLSI Layout Lab
Tutorial -- Virtuoso
Instructor : Prof. Paul C.
2022/10/27
Sensers IC Lab , NYCU ECE
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Outline
Workstation
• Account
• Setting environment
Cadence Virtuoso
• Schematic
• Layout
Task
Software tool
Connect to EDA CLOUD
Circuit design
Schematic and Layout
NX Client
Hspice
Virtuoso OA
Calibre Design Rule Check (DRC)
Layout Versus Schematic (LVS)
Layout Parasitic Extraction (PEX)
waveview
Verification
Waveform observation
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EDA CLOUD account&password
• Account : ex:pzxxxx
The TA will send you
• Password obtained by OTP (Note that the password
is only valid for 30 minutes )
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EDA CLOUD account&password
1. https://www.tsri.org.tw/
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EDA CLOUD account&password
2.Log in your account of tsri
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EDA CLOUD account&password
3. Setting the browser. (Recommended to use IE
browser )
(3)
A. Settings on IE. (Step 1)
(1)
(4)
(2)
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EDA CLOUD account&password
3. Setting the browser. (Recommended to use IE
browser )
A. Settings on IE. (Step 2)
“將未標示成安全的ActiveX 控制
項初始化並執行指令碼” -> 提示
(5)
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EDA CLOUD account&password
B. IE browser settings on Microsoft Edge (Step 1).
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EDA CLOUD account&password
B. IE browser settings on Microsoft Edge (Step 2).
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EDA CLOUD account&password
B. IE browser settings on Microsoft Edge (Step 2).
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EDA CLOUD account&password
B. IE browser settings on Microsoft Edge (Step 3).
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EDA CLOUD account&password
4. Enter your account e-mail to get the password
pzxxxx
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EDA CLOUD account&password
5. Receive the Email to get password.
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Setting Environment (1/3)
1.Install remote software(Note that all files need to
be installed )
(https://www.tsri.org.tw/edacloud/edacloud.jsp)
! 請先安裝主程式再安裝字型安裝檔
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Setting Environment (1/3)
2. Open “NX Connection Wizard.”
You can name it yourself.
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edah.cic.org.tw
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9103
LAN
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Setting Environment (3/3)
3.CDE
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4.Shortcut
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5.Click Configure to modify the connection settings.
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• LOG in your account and
password
• The first time you connect, you
will be asked about the RSA key
authentication consent message,
please click yes.
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Unix Command
• List the folders and files
- <terminal> ls
• Change a directory
- <terminal> cd /File directory
- <terminal> cd ..
• Make a directory
- <terminal> mkdir
• Remove an empty directory
- <terminal> rmdir
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Design Flow of Full-Custom Chip
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Before Designing a Circuit (1/2)
Open the terminal
- <terminal>cp -r /cad/PDK/T18 ~
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Before Designing a Circuit
• Folder : virtuoso
Technology File : rf018.tf
• Folder : model
Library File : rf018.l
• Folder : calibre
Files for DRC, LVS,PEX
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Launch Cadence Virtuoso
• Open TERMINAL in the virtuoso OA folder and then open VIRTUOSO
• <terminal> Rvirtuoso
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Create a New Library (1/3)
Tools -> library Manager ->File ->New->Library
Name the folder and press ok
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Create a New Library (2/3)
Select first one and click ok ->Fill in the file path(/PDK/T18/Virtuoso_OA/techfile.tf)
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Create schematic
Library manager : select the library name you just created. Ex: inv or VLSI.
File New Cell View
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Schematic window
Save
Add instance
Wire
Hot Key
Function
W
Wire for connection
I
Instance
P
Pin
C
Copy
Q
Observe and modify the detail
characteristic of the instance
Shift+Z
Ctrl+Z
Zoom out
Zoom in
Delete
Delete wire, instance, pin…
Esc
Cancel the command
Add pin
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Add instance
Press i and add the new instance ->Browse-> select tsmc18rf->select instances.
Select “nmos2v” & “pmos2v”.
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Add instance
Schematic window
Choose the instance and press the hot key “Q”, you can
modify the parameter of the instance.
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Add pins
Three directions: input, output and inout ,vdd ,gnd
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Connection by Wires (hot key:W)
Example: inverter
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Start to layout
• When the behavior of the circuit you designed is
verified, then you can draw the layout.
• Add layout cell view in library manager.
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Create a Layout Cell View
Launch layout XL and create layout cell view->select “create new”and click ok
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Create a Layout Cell View
You can select your component to call the built-in cell (ex:nmos)
1
2
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Settings for Layout Environment
• Set display options as you launch Virtuoso
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Cadence Virtuoso --- Hot keys for Layout
You can find more functions in “Edit”.
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Hot Key
Function
Hot Key
Function
R
Rectangle
Shift+Z
Ctrl+Z
F
Zoom out
Zoom in
Fit all
K
Shift+k
Ruler
Clear ruler
O
Create contact
S
A
Stretch
Delete
Delete wire,
instance, pin…
C
Copy
Esc
Cancel the
command
M
Move
L
Label, pin
Shift+f
Show/hide
instances
Align
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Layout object
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Layout example: nmos, pmos
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Layout example: inverter
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Design Rule Check (DRC)
• Reserve the space and capability for process
fabrication (refer to the design rule)
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Calibre DRC (Step 1)
• Stream out layout gds file.
• !! Call the Layer Map file.
(/PDK/T18/Virtuoso_OA/tsmc18rf/tsmc18rf.layermap)
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Calibre DRC (Step 2)
• Copy the gds file to “Calibre” folder.
• Open “T18_DRC_rule” and modify layout path & primary.
(1)Layout path: gds file name. (2) Layout primary: layout top cell name.
(2)
(1)
(3)
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Calibre DRC (Step 3)
• Open terminal at “Calibre”.
• Run Calibre DRC. ( <terminal> Qcalibre -drc T18_DRC.rule)
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Calibre DRC (Step 4)
• Open “Calibre”, “Start RVE”.
• Open DRC result at
“/Calibre/CALIBRE_result”
(3)
(2)
(6)
(1)
(4)
(5)
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Calibre DRC (Step 5)
• Check DRC results.
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DRC Ignorable error
T18 process 可允許錯誤
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Ignorable now, but
not for full chip.
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Layout vs. Schematic (LVS)
LVS
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Calibre LVS (Step 1)
• Export netlist form schematic.
(1)
(2)
(3)
(4)
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Calibre LVS (Step 2)
• Check CDL output netlist.
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Calibre LVS (Step 3)
• Copy the .gds & netlist file to “Calibre” folder.
• Open “T18_LVS_rule” and modify layout path, layout
primary.
(1)Source path: netlist file name. (2) Source primary: netlist top cell name.
(2)
(1)
(3)
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Calibre LVS (Step 4)
• Open terminal at “Calibre”.
• Run Calibre LVS. (<terminal> Qcalibre -lvs T18_LVS.rule)
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Calibre LVS (Step 5)
• Open “Calibre”, “Start RVE”.
• Open LVS result at
“/Calibre/CALIBRE_result”
(2)
(3)
(6)
(1)
(4)
(5)
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Calibre LVS (Step 6)
• Check LVS results.
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Calibre PEX (Step 1)
• Open “T18_LPE_rule” and modify layout path, layout
primary.
(1)
(2)
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Calibre PEX (Step 2)
• Open terminal at “Calibre”.
• Run Calibre PEX.
(<terminal> Qcalibre -lpe -rc T18_LPE.rule)
• Copy the three output files.
(2)
(1)
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Post-simulation (Step 1)
• Check the PEX output file “out_netlist”.
• Create testbench.
testbench
Library
Include output_netlist
output_netlist
Netlist of the circuit
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Post-simulation (Step 2)
• Put 3 output netlist file and testbench into a folder for
post-simulation.
• Run post-simulation.
(<terminal> Qhspice -i inv_testbench.sp -o HSPICE -mt 4)
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Post-simulation (Step 3)
• Open Waveview.
(<terminal> Rcx)
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Terminate/suspend EDA Cloud
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Reference Document
TSRI EDA:
https://www.tsri.org.tw/tw/commonPage.jsp?kindId=D0010
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END
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