IET Power Electronics
Research Article
Secondary-side phase-shifted full-bridge
converter with reset winding
ISSN 1755-4535
Received on 26th November 2019
Revised 26th February 2020
Accepted on 16th April 2020
E-First on 19th May 2020
doi: 10.1049/iet-pel.2019.1470
www.ietdl.org
Wei Liu1, Qinglin Zhao1 , Deyu Wang1, Kunlun Li1, Yujie Wang1
1School
of Electrical Engineering, Yanshan University, Qinhuangdao, People's Republic of China
E-mail: powerzql@ysu.edu.cn
Abstract: A resonant inductor and two clamping diodes are introduced into the secondary phase shift full-bridge converter
(SPS-FBC), which can well suppress voltage spike across the rectifiers. However, the resonant inductor and two clamping
diodes will bring some other problems. In this study, an auxiliary winding in series with the resonant inductor is added to the
SPS-FBC to reset the clamp diode current rapidly. The auxiliary winding not only reduces the circulation losses of the switches
and the clamping diodes, but also makes the clamping diodes naturally turn-off and avoids the reverse recovery even when the
output filter inductance and magnetising inductance are relatively large. The principle of operation and performance are
illustrated and verified on a 1.5 kW experimental circuit. In addition, the efficiency and losses of the converters with/without reset
winding are compared and analysed. The efficiency of the converter with reset winding is significantly improved over the entire
operating range and the peak efficiency is 96.60% at full load.
1
Introduction
As global environmental issues are increasingly prominent and the
fossil energy crisis intensifies, the development and promotion of
new energy vehicles is imminent. As an important part of new
energy vehicles, the battery charging system is mainly composed of
the fronted-stage PFC and high-frequency isolated DC–DC
converter [1–3]. To meet the requirements of various on-vehicle
power battery specifications, the study of a wide output voltage
range and high reliability DC/DC converter is very important for
the performance of the entire battery charging system.
The control method, operating characteristics and application
occasion of primary phase-shifted full-bridge converter (PPS-FBC)
and secondary phase shift full-bridge converter (SPS-FBC) are
similar. The characteristics are introduced using PPS-FBC as an
example. As one of the mainstream topologies of isolated DC/DC
circuits, the traditional PPS-FBC has the characteristics of high
efficiency, high power density and high reliability [4–6]. Utilising
the transformer leakage inductance and switch intrinsic
capacitance, it can achieve ZVS without any external passive
components [7–10]. PPS-FBC has been widely used in medium
and high power applications [11–14], but there are some major
problems: (i) limited ZVS range of the lagging-leg switches; (ii)
the circulating energy issue; (iii) the voltage spike of the output
rectifiers; (iv) the severe loss of duty cycle. To overcome the above
shortcomings, experts and scholars have conducted in-depth
research work in recent years. The ZVS range can be extended by
utilising a saturated inductor instead of a common inductor,
meanwhile reducing the loss of duty cycle [15]. However, saturated
inductor brings too much loss. An auxiliary circuit with lagging leg
can improve the soft-switching range [16–18], but the auxiliary
network energy has nothing to do with the load, and the conduction
loss of heavy load is particularly serious. In [19, 20], the energy of
the auxiliary circuit can be adaptively changed with the load.
However, the current stress is relatively large because the auxiliary
circuit is connected in series with the main circuit, which will
decrease the reliability of the converter. On the other hand, the
zero-voltage zero-current switching (ZVZCS) PPS-FBC not only
retains all the advantages of the conventional PPS-FBC but also
reduces the conduction loss of the primary side [21, 22]. In the
ZVZCS full-bridge topology, to reset the primary current during
the freewheeling time, two diodes are added in series with the
lagging leg in [23]. After that, the lagging leg realises ZCS, which
IET Power Electron., 2020, Vol. 13 Iss. 11, pp. 2252-2259
© The Institution of Engineering and Technology 2020
reduces switching loss and circulating current loss. However, the
on-state loss of the diodes is generated. The auxiliary winding of
the transformer is utilised to reset the primary current, however, it
increases the complexity of the transformer design [24]. An energy
recovery buffer circuit was added on the secondary side in [25], but
the control of the converter becomes complicated as the amount of
the devices increases.
Compared with the traditional PPS-FBC, the SPS-FBC has been
developed and reported in [26–28]. The SPS-FBC has the
advantages of wide soft-switching range, no circulating current
loss, and small duty cycle loss. It can effectively solve the
problems of traditional PPS-FBC such as the narrow ZVS range of
the lagging leg and the primary circulating loss. Although the basic
and conceptual research has been reported in [26–28], such as the
analysis on the soft-switching range and the steady-state power
regulation characteristics, the problem that the severe voltage
overshoot and oscillation across the diode rectifier is caused by the
interaction between junction capacitance of the rectifier diode and
leakage inductance of the transformer has not been evaluated indepth in the past relevant work.
To solve the above problem, a resonant inductor and two
clamping diodes can be introduced into the primary side of the
transformer. Then the excess energy of the resonant inductor can be
fed back to the input power, which will suppress the voltage stress
of the rectifiers. However, the conduction loss of the switches and
the clamping diodes will increase, and the clamping diodes are
hard turned-off if the output filter inductance and magnetising
inductance are relatively larger. In this paper, an auxiliary winding
in series with the resonant inductor is added to the SPS-FBC to
reset the clamp diode current rapidly when the clamp diode
conducts. The reset winding not only reduces the conduction
losses, but also makes the diodes naturally turn-off and avoids the
reverse recovery.
This paper is organised as follows: Section 2 analyses the
circuit configuration and the working principle of the circuit in
detail. Section 3 gives the comparisons between the SPS-FBC
with/without reset winding. In Section 4, a 1.5-kW hardware
converter prototype has been designed, fabricated, and tested to
verify the correctness of the theoretical analysis. Finally, the
concluding remarks are drawn in Section 5.
2252
Fig. 1 SPS-PWM full bridge converters
(a) Without reset winding, (b) With reset winding
Fig. 2 Key waveforms of the SPS-PWM full-bridge converters
(a) Without reset winding, (b) With reset winding
2
Circuit description and operation principle
The proposed SPS-FBC with/without reset winding and the key
waveforms for different stages are shown in Figs. 1 and 2,
respectively. Different from [26–28], this paper considers the
junction capacitance of the rectifiers when analysing the reverse
recovery. As shown in Fig. 1, the SPS-FBC converter topology
consists of four MOSFETs S1∼S4, the parasitic capacitances C1–
C4, a series resonant inductor Lr, a tightly coupled transformer T
with an air gap, the clamping diodes Dc1 and Dc2, secondary-side
rectifiers (reverse blocking active switches Q5/Q6 and diodes D7/
D8), LC output filter (Lf and Co), the load R. In this control
strategy, the output voltage is regulated by controlling the phaseshift angle between the primary and secondary switches. Compared
with Fig. 1a, there is an additional auxiliary winding in series with
the resonant inductor in Fig. 1b. As shown in Fig. 2, the clamping
diodes conduct twice in a switching cycle and the voltage of reset
winding can make the current of clamping diodes decay to zero
rapidly. The operation principles of the SPS-FBC with/without
reset winding are similar except during the periods [t4, t6] and [t8,
t9]. Therefore, only the working principle of the SPS-FBC with
reset winding is analysed in this paper.
The converter with reset winding goes through ten stages during
a half-switching cycle in SPS mode. And the analysis is based on
the following assumptions: (i) all switches, diodes, inductors,
IET Power Electron., 2020, Vol. 13 Iss. 11, pp. 2252-2259
© The Institution of Engineering and Technology 2020
capacitors and transformers are ideal devices, except for the
rectifier diodes D5–D8, which is equivalent to an ideal diode and a
paralleled capacitor. (ii) The turns ratio of the transformer T is the
primary winding: the reset winding: the secondary winding =
n1:n3:n2, (iii) the output filter inductor Lf is large enough to be
regarded as a constant current source in one cycle, (iv) the output
capacitors of switches S1–S6 and the junction capacitance of the
rectifiers are expressed as C1–C6 = Coss, CDR5–CDR8 = CDR. The
equivalent circuits of different stages in a half switching cycle are
shown in Figs. 3–6.
Stage 1[t0, t1]: Since the gate signals for S2 and S3 are removed
simultaneously at t0, the primary current ip starts to charge C2/C3
and discharge C1/C4. As the voltage VBA begins to decline, the
voltage across the secondary-side transformer T winding terminals
also begins to decreases. The intrinsic capacitance C5, CDR5 and
CDR8 start to discharge. During this time, stage 1 will end once
VBA reaches zero.
Stage 2[t1, t2]: At t1, the intrinsic capacitance C5, CDR5 and
CDR8 are discharged to zero. When VBA starts to increase reverse,
ip and is decreases rapidly. The voltage across the secondary-side
transformer T winding terminals also becomes zero, and D8 is
naturally forward-biased. Hence, iLf is freewheeled through D7, Q6
and D8.
2253
Fig. 3 Equivalent circuits of different stages in a half switching cycle
(a) Stage 1, (b) Stage 2, (c) Stage 3
Fig. 4 Equivalent circuits of different stages in a half switching cycle
(a) Stage 4, (b) Stage 5, (c) Stage 6
Fig. 5 Equivalent circuits of different stages in a half switching cycle
(a) Stage 7, (b) Stage 8, (c) Stage 9
Fig. 6 Equivalent circuits of different stages in a half switching cycle
(a) Stage 10
Fig. 7 Further equivalent circuits
(a) Stage 5, (b) Stage 10
Stage 3[t2, t3]: At t2, the output capacitors of S2 and S3
continuously are charged up to Vin and that of S1 and S4 are
discharged down to zero. Therefore, the antiparallel diodes of S1
and S4 are conducting. The ZVS of S1 and S4 can be achieved at
this moment. During this interval, the secondary side of
2254
transformer T is always shorted and ip keeps decreasing and
approaching to iLm at t = t3.
Stage 4[t 3, t 4]: At t3, is decreases to zero. The resonance occurs
between Lr, C5 and CDR6, so VCB starts to increase. At t4, CDR6 is
charged to Vinn2/n1, and the potential voltage of point C rise to Vin.
Therefore, DC1 starts to conduct and VCB are clamped at Vin.
Stage 5[t4, t5]: During this stage, the resonant inductor Lr is
shorted, and iLr flows through S1 and DC1 with a constant value. ip
decreases downward to the magnetising current iLm. The voltage of
the reset winding VCD is Vinn3/n1 which acts on Lr to make the iLr
decline rapidly. This stage will end when ip equals iLr at t5. Then
DC1 turns off naturally. The further simplified equivalent circuit of
this mode is shown in Fig. 7a.
Stage 6[t5, t6]: When ip is equal to iLm at t5, the input voltage
Vin acts on Lr and Lm. The primary and secondary sides of T are
disconnected, so iLf is freewheeled through diodes D7 and D8.
Stage 7[t6, t7]: The gate of S5 is supplied at t = t6. Since Q5 and
D7 are on-state simultaneously, the secondary side of transformer T
is shorted again. The secondary side current is starts to increase
linearly and iD7 decreases gradually due to the effect of Lr.
Stage 8[t7, t8]: At t7, iD7 decreases to zero, and is reaches iLf.
The resonance occurs between Lr, CDR6 and CDR7, so the voltage
VCB starts to increase. At t8, CDR6 and CDR7 is charged to Vinn2/n1,
and the voltage of point C rise to Vin. So DC1 conducts again and
VCB is clamped at Vin.
Stage 9[t8, t9]: In this interval, the resonant inductor Lr is
shorted again. iLr flows through S1, DC1, and remains constant. ip
step downward to ip(t8). The voltage of the reset winding VCD is
IET Power Electron., 2020, Vol. 13 Iss. 11, pp. 2252-2259
© The Institution of Engineering and Technology 2020
Vinn3/n1, which acts on Lr to make the iLr decline rapidly. This
stage will end when ip equals iLr at t9. Then DC1 turns off naturally.
Stage 10[t9, t10]: During this stage, ip equals iLr, and the power
is delivered from Vin to the load R. The reset winding n3 is in series
with the primary winding n1, so the input voltage Vin acts on Lr and
Lm. Then, the voltage VDB = Vin(n1 + n3)/n1, and the resonance
occurs between Lr, Lm, CDR6 and CDR7. The further simplified
equivalent circuit of this mode is shown in Fig. 7b. This stage ends
at t10 when S1 and S4 are turned off. Then, the next half switching
cycle starts. Hence, vrect can be expressed as:
vrect t =
3.2 Magnetising inductance
n2LriLm t9 ω22
n2 ω22
sin ω1 t − t9
2 V in −
n1 + n3 ω1
n1 + n3 ω12
2
2
2
1
+
n2
n2 ω
−
V cos ω1 t − t9
n1 n1 + n3 ω in
≃
n2
n
n2
V + 2−
V cos ω1 t − t9
n1 + n3 in
n1 n1 + n3 in
Fig. 8 Primary-side current waveforms without reset winding
(1)
where ω1 = 1/ LeqCeq ω2 = 1/ LrCeq Leq = LmLr /(Lm + Lr)
2
Ceq = 2CossCDR + CDR
/ Coss + CDR n2 / n1 + n3 2
Equation (1) shows that vrect have slight oscillation. In practice,
vrect will finally stay at the average value Vinn2/(n1 + n3) since the
parasitic resistance exists in the main circuit.
According to Fig. 2a, the clamping diodes DC1 and DC2 conduct
during the interval [t4, t5] and [t13, t14] on the SPS-FBC without the
reset winding. Therefore, there are circulation losses of the
switches and the clamping diodes. Furthermore, if the magnetising
inductor Lm is relatively large, the clamping diodes are hard
turned-off, causing significant reverse recovery loss. To solve the
above problems, the value of Lm should be small. The transformer
primary current ip, resonant current iLr and magnetising current iLm
waveforms without reset winding are shown in Fig. 8.
△I1 is the primary current spike caused by the resonance of the
resonant inductor and secondary side parasitic capacitors
△I1 =
3 Analysis of the proposed converter
3.1 Transformer turns ratio
In contrast to [26–28], the reset winding is added to the SPS-FBC.
Therefore, the transformer turns ratio is compared between the
improved converter and the original one in this part.
According to Fig. 2b, the time intervals [t6, t8] and [t10, t11] are
considered to be negligible at a half switching cycle. Therefore, Vo
can be expressed as:
V o ≃ V rectD1 =
V inn2
2 V inn2
t +
t
T s n1 89 n1 + n3 910
C′j = (CDR + Coss)
Before the reset winding is introduced, the voltage conversion ratio
of the SPS-FBC can be given by
Vo
n
= 2D
V in np 1
(4)
where np is the primary turns of the transformer.
Under the same working conditions, the conclusions can be
obtained from (3) and (4):
np = n1 + n3
(5)
It means that the transformer primary winding of the SPS-FBC is
divided into two parts, and one of them is used as the reset winding
in the improved converter.
Lm ≤
n2
np
Lm
diLm
= V in
dt
Imp =
V in T s
Lr + Lm 4
IET Power Electron., 2020, Vol. 13 Iss. 11, pp. 2252-2259
© The Institution of Engineering and Technology 2020
2
(7)
(8)
(9)
In this interval, taking into account the voltage drops on the
clamping diode and the switch, the rise slope of the magnetising
current can be given by
diLr
1
= − [V D + (Imp − △I1)R]
dt
Lr
(10)
where VD is the forward voltage drop of the clamping diode; R is
the sum of the static drain-to-source on-resistance of the switch S1
and parasitic resistance of resonant inductance Lr.
From (6) and (10), Δt1 is the conduction time of the clamping
diode and can be obtained by:
△t1 =
△I1
V in /Lm + V D + (Imp − △I1)R)/Lr
(11)
To avoid reverse recovery of the clamping diode, Δt1 should be
smaller than D2Ts/2. The maximum value of Lm without reset
winding can be obtained by (4), (9), and (11) (see (12)) , where
(V inn2 − V onp)T sLr2
⋅
n2
A2 − 2/V inn22 (V inn2 − V onp)2 T sLr
2
The voltage across the magnetising inductor Lm and the peak value
of the excitation current iLm can be expressed, respectively, as:
If the appropriate turns of the reset winding are chosen, [t8, t9] is
shorter than [t9, t10]. Equation (2) can be further simplified to:
(3)
(6)
Based on the model analysis, C′j can be derived as:
(2)
Vo
n2 t810
n2
≃
=
D
V in n1 + n3 T s /2 n1 + n3 1
V in
Lr /C′j
1
V D − △I1R − 2V inLr△I1n2 /(V inn2 − V onp)T s − A
(12)
2255
A=
diLr
VD
Ion2
V in
= −
−
− Imp −
Δt
dt
Lr
np
Lm 1
(V inn2 − V onp)D2T s
1
V D − △I1R + V in Lr + V inRT s
2V inn2
4
According to (12), Fig. 9 shows the relationship between the
maximum excitation inductance Lm and the input voltage Vin.
During the D2Ts/2 period, the clamping diode can turn off
naturally by reducing the value of the transformer magnetising
inductance Lm. However, the value of Lm is relatively small, so the
magnetising current increases. The conduct loss of the primary
switch and magnetic component is deteriorated, which is harmful
to the improvement of efficiency.
The waveforms of primary current ip, resonant current iLr and
magnetising current iLm with reset winding are shown in Fig. 10. In
contrast to the reset winding voltage, the voltage drops on the
clamping diodes and the switches can be neglected during this
interval. Hence, the rising slope of the resonant inductance Lr can
be given by
diLr V in n3
=
dt
Lr n1
(13)
From (6), (8), (13), the conduction time of the clamping diode can
be obtained by:
Δt1′ =
LmLrΔI1 /V in
n3 /n1 Lm + Lr
(14)
In order to avoid reverse recovery of the clamping diodes, Δt1′
should be smaller than D2Ts/2. Lm is assumed to be large enough to
be infinity. Therefore, (14) can be further simplified to:
9.36n1 V o(n1 + n3)
+
≤1
n3V in
n2V in
(15)
R
Lr
(19)
where Io is the load current. To avoid reverse recovery of the
clamping diode, Δt2 should also be smaller than D1Ts/2. From (16),
(18), (19), The maximum value of Lf without reset winding can be
given by (see (20)) . According to (20), Fig. 11 shows the
relationship between the maximum output filter inductor Lf and
input voltage Vin.
During the D1Ts/2 period, the clamping diode can turn off
naturally by reducing the value of the output filter inductor Lf.
However, the above solution will increase the ripple current of
output filter inductor. Thus, the filter capacitance will increase.
On the transformer with reset winding, the conduction time of
the clamping diodes can be derived based on (13), (18) and is given
by
Δt2′ =
ΔI2LrLf
n3 /n1 V inLf + n2 /np Lr V in n2 /np − V o
(21)
To avoid reverse recovery of the clamping diode, Δt2′ should also
be smaller than D1Ts/2. Lf is assumed to be large enough to be
infinity, so (21) can be further simplified as:
0.03n1n2
≤1
n3(n1 + n3)
(22)
Substituting the converter parameters in this paper, (22) is
permanently established. In other words, regardless of the value of
filter inductor Lf on the SPS-FBC with the reset winding, the
clamping diodes can turn off naturally if chosen the appropriate
turns of the reset winding.
Substituting the converter parameters in this paper, (15) is
permanent established. In other words, regardless of the value of
the magnetising inductance Lm on the transformer with the reset
winding, the clamping diode can turn off naturally. The circulation
losses of the clamping diodes and the switches are greatly reduced.
3.3 Output filter inductance
According to Fig. 2a, due to the reverse recovery of the clamping
diodes D7/D8, the clamping diodes DC1 and DC2 conduct again
during the interval [t6, t7] and [t15, t16] on the SPS-FBC without the
reset winding. If the output filter inductor Lf is relatively larger, Δt2
will be greater than D1Ts/2 which means that the clamping diodes
are hard turned-off. Therefore, it is necessary to analyse the effect
of the value of the output filter inductor Lf on the circuit.
According to Fig. 8, ΔI2 and C′′
j can be expressed, respectively, as:
ΔI2 =
V in
(16)
Lr /C′′j
C′′
j = 2CDR
n2
np
2
Fig. 9 Relationship between the maximum value of Lm and the input
voltage Vin without reset winding
(17)
The slopes of output filter inductor current iLf and resonant
inductor current iLr is described, respectively, as
diLf
1 V inn2
=
− Vo
dt
Lf np
Lf ≤
2256
(18)
Fig. 10 Primary-side current waveforms with reset winding
n2
− V o Lr
np
− 1 − D1 /Lm + 2LrΔI2 /D1T − n2 /np IoR − V D
V in
1/2 V inRT s 1/ 2 Lr + Lm
(20)
IET Power Electron., 2020, Vol. 13 Iss. 11, pp. 2252-2259
© The Institution of Engineering and Technology 2020
Fig. 11 Relationship between the maximum value of Lf and the input voltage Vin without reset winding
Table 1 Circuit parameters and specification of prototypes
Parameter
Value unit
input voltage Vin
360–400 V
output voltage Vo
250 V
output power Po
1.5 kW
switching frequency fs
transformer T
130 kHz
FerroxcubePQ35/35ferrite core; n1:n3:n2 = 19:3:18, Lm = 600 μH
resonant inductor Lr
FerroxcubePQ20/20ferrite core; N = 6; Lr = 12 μH
output inductance Lf
KEDA KS130-075A Sendust core; Lf = 180 μH
output capacitor Co2
Electrolytic capacitor; Co2 = 200 μF
primary/secondary switches S1–S6
rectifiers D5–D8
clamp diodes Dc1–Dc2
Infineon IPW60R070CFD7 650 V, 31 A
Ultrafast recovery diode HFA15TB60 600 V, 15 A
SiC Schottky diode C3D04060E 600 V, 4 A
Fig. 12 Observed waveforms of the converter with reset winding at Po = 1.5 kW
(a) Driving voltages Vg1–Vg6, (b) Driving voltages Vg2 and Vg4, drain-source voltages Vds2 and Vds4
4
Results and discussions
To verify the working principle of the SPS-FBC with/without reset
winding, a 1.5 kW experimental prototype was designed and built.
Furthermore, the circuit parameters are illustrated in Table 1.
Driving voltages Vg1–Vg6 of the converter with reset winding at
Po = 1.5 kW are shown in Fig. 12a. Fig. 12b shows that S2 and S4
both achieve ZVS with the reset winding. Actually, compared with
S2 and S4, S1 and S3 are easier to realise ZVS, so all the primary
side switches achieve ZVS.
Fig. 13 shows the experimental waveforms of VAB, VCB, ip and
iLr without (left)/with (right) reset winding under the full load
condition. It can be seen that each clamping diode conducts twice
in a switching period before the reset winding is introduced. When
the clamping diode is conducting, the resonant inductor Lr is
shorted and iLr remains constant. Hence, the potential voltage of
point C is clamped at 0/Vin. When the clamping diode conducts, iLr
decay rapidly by introduced the reset winding. Therefore, the
clamping diode average current is decreased, leading to a low
circulation loss.
IET Power Electron., 2020, Vol. 13 Iss. 11, pp. 2252-2259
© The Institution of Engineering and Technology 2020
Fig. 14 shows the experimental waveforms of VQ5, is and VD7
without/with reset winding under the full load condition. It can be
seen that the voltage overshoot and oscillation across the rectifiers
are suppressed effectively. After introducing the reset winding, the
secondary-side active switch Q5 can realise ZCS turn-on and ZCS
turn-off. However, the voltage stress of the secondary side power
device increases.
The efficiency with different loads under the input voltage Vin
= 400 V is given in Fig. 15 and the power loss analysis of the SPSFBC with/without reset winding at full load is shown in Fig. 16. It
can be seen that the efficiency of the improved SPS-FBC is higher
than that of the converter without reset winding. That is because
the circulation losses of the clamping diodes, the leading switches
and the resonant inductor are decreased. What is more, the peak
efficiency of SPS-FBC with reset winding is 96.60% and the
efficiency is improved at light load.
5
Conclusion
A secondary-side phase-shifted full-bridge converter with reset
winding is proposed in this paper. The working principle and
2257
Fig. 13 Measured waveforms of VAB, VCB, ip and iLr at Po = 1.5 kW
(a) Without reset winding, (b) With reset winding
Fig. 14 Measured waveforms of VQ5, is and VD7 at Po = 1.5 kW
(a) Without reset winding, (b) With reset winding
circuit characteristics of the converter are analysed in detail. To
verify the correctness of the structure, a 1.5 kW experimental
prototype was built, and comparison of the main experiment results
on the transformer with/without the reset winding was given.
Introduced the reset winding in series with the resonant inductor,
the clamping diodes can turn off naturally without reverse
recovery. Simultaneously, the circulation loss of the auxiliary
network is reduced and the efficiency of converter can be
improved.
6
[1]
[2]
Fig. 15 Efficiency under different load conditions
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10]
Fig. 16 Power loss analysis of the SPS-FBC with/without reset winding at
full load
2258
[11]
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