CASE WESTERN RESERVE UNIVERSITY
Case School of Engineering
Department of Electrical Engineering and Computer Science
EECS 281. Logic Design and Computer Organization (4)
Assignment #5
SOLUTIONS
6.20 (a)
6.27
(A = B) = (A3 ⊕ B3)′⋅ (A2 ⊕ B2)′⋅ (A1 ⊕ B1)′⋅ (A0 ⊕ B0)′
6.29
c1 = x0⋅y0 (Assuming c0 = 0)
c2 = x1⋅y1 + x1⋅c1 + y1⋅c1
= x1⋅y1 + x1⋅(x0⋅y0) + y1⋅(x0⋅y0)
c3 = x2⋅y2 + x2⋅c2 + y2⋅c2
= x2⋅y2 + x2⋅(x1⋅y1 + x1⋅(x0⋅y0) + y1⋅(x0⋅y0)) + y2⋅(x1⋅y1 + x1⋅(x0⋅y0) + y1⋅(x0⋅y0))
s3 = x3 ⊕ y3 ⊕ c3
s3 = x3 ⊕ y3 ⊕ [x2⋅y2 + x2⋅(x1⋅y1 + x1⋅(x0⋅y0) + y1⋅(x0⋅y0)) + y2⋅(x1⋅y1 + x1⋅(x0⋅y0) + y1⋅(x0⋅y0))]
6.37
Decoder:
module Vr3to8decx(G, A, Y);
input G;
input [2:0] A;
output [0:7] Y;
reg [0:7] Y;
always @ (G or A) begin
if (G)
case (A)
0: Y = 8'b10000000;
1: Y = 8'b01000000;
2: Y = 8'b00100000;
3: Y = 8'b00010000;
4: Y = 8'b00001000;
5: Y = 8'b00000100;
6: Y = 8'b00000010;
7: Y = 8'b00000001;
default: Y = 8'b00000000;
endcase
else Y = 8'b00000000;
end
endmodule
Emulating of decoder:
module Vr74x138x(G1, G2A_L, G2B_L, A, Y_L);
input G1, G2A_L, G2B_L;
input [2:0] A;
output [0:7] Y_L;
wire [0:7] Y;
wire G;
assign G = G1 & ~G2A_L & ~G2B_L; // Convert and combine inputs
assign Y_L = ~Y;
// Convert outputs
Vr3to8decx U1 ( .G(G), .A(A), .Y(Y) );
endmodule
The relationship between the modules:
6.44
(a) Note that C, B, and A could be labeled active-low, in which case the order of outputs Y0–Y7 would be reversed.
(b) The circuit is a 3-to-8 decoder with three-state outputs.
A, B, C Select inputs; C is most significant.
G1A_L, G1B_L, G2 Enable inputs. All must be asserted to enable an output.
OE Output enable input. When asserted, outputs are driven, otherwise they are tri-stated.
Y0–Y7_L Decoded outputs. These are driven when OE is asserted, and tri-stated otherwise. When all
enable inputs are asserted, the output selected by the select inputs is asserted.
ENOUT_L Enable output. Asserted when all of the enable inputs are asserted.
(c) See logic symbol in part a.
Part 3: Laboratory
Step 1. Design the hierarchical full adder
Hierarchical full adder using OAO sub-module().
Step 2. Enter the design into Active-HDL
// hierarchical adder module for HW4
module adder(a,b,ci, s,co); // hierarchical full adder
input a,b,ci;
output s,co;
wire aORb, aANDb_, aANDb, y21, y23_, co_; // internal nets
OAO U1(ci,a,b,a, aORb,aANDb_,co); // carry-output module
OAO U2(co_,aORb,ci,aANDb, y21,y23_,s); // sum module
not U3(co_, co); // inverts co to produce co_
not U4(aANDb, aANDb_); // inverts aANDb_ to produce aANDb
endmodule
module OAO(d,e,f,g, y1,y3_,y4); // nand-only OAO module for sum and carry logic
input d,e,f,g;
output y1,y3_,y4;
wire e_, f_, y2_; // internal nets
not U5(e_, e);
not U6(f_, f);
nand U1(y1, e_,f_);
nand U2(y2_, y1,d);
nand U3(y3_, f,g);
nand U4(y4, y2_,y3_);
endmodule
Step 3. Enter the test bench into Active-HDL
// Test Bench for the full adder
`timescale 1 ns / 10 ps
module TestBench;
integer ctr; // counter used to generate inputs
wire a = ctr[2]; // inputs
wire b = ctr[1];
wire ci = ctr[0];
wire s,co; // outputs
adder UUT (a,b,ci, s,co);
initial
begin
ctr = 0; // initialize input register
$display("
TIME | A B CI | S CO"); // setup text display
$monitor($time," %b %b %b %b %b", a,b,ci, s,co);
$dumpfile("adder.vcd");
$dumpvars(1,a,b,ci,s,co);
$dumpflush;
#80 $finish; // specify end time
end
always forever #10 ctr = ctr + 1; // increment every 10 time units
endmodule
Step 4. Run the simulation and view the results