Power Supply Design Seminar
Topic 3 Presentation:
Designing an LLC Resonant Half-Bridge
Power Converter
Reproduced from
2010 Texas Instruments Power Supply Design Seminar
SEM1900, Topic 3
TI Literature Number: SLUP256
© 2010, 2011 Texas Instruments Incorporated
Power Seminar topics and online powertraining modules are available at:
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Topic 3
Designing an LLC Resonant
Half-Bridge Power Converter
Hong Huang
SLUP256
Agenda
1 Introduction
1.
– Brief review
– Advantages
2. Design Prerequisites
–
–
–
–
Configuration
Operation
p
Modeling
Voltage gain function
3 Design
3.
D i
Considerations
C
id ti
–
–
–
–
Voltage gain and switching frequency
Line and load regulation
Zero voltage switching (ZVS)
Steps for designing and a design example
4. Conclusions
Texas Instruments—2010 Power Supply Design Seminar
3-2
SLUP256
Introduction
• Brief review of resonant converters
– Series resonant converter (SRC)
– Parallel resonant converter (PRC)
Lr
Cr
Lr
RL
Cr
SRC
RL
PRC
• Single resonant frequency
• Resonant point changes with load
• Circuit frequency increases
with lighter load
• Large amount of circulating current
Texas Instruments—2010 Power Supply Design Seminar
3-3
SLUP256
Introduction
• Brief review of resonant converters
– Combination of SRC and PRC LCC
• Two resonant frequencies
• Requires three elements
– LLC: alternative LCC
• Lr and Lm integrated in a transformer
• Advantages of LLC
– High efficiency (ZVS)
– Less frequency variation and lower circulating current
– ZVS over operating range
Lr
Cr 1
C r2
LCC
Lr
RL
Texas Instruments—2010 Power Supply Design Seminar
Cr
Lm
LLC
RL
3-4
SLUP256
Design Prerequisites
• Configuration
– Variable-frequency
square-wave
generator
Square-Wave
q
Generator
Resonant
Network
Q1
Vin = +
VD C –
– Divider formed by
resonant network
and RL
Vs q
Q2
Cr
Rectifiers for
DC Output
D1
n:1:1
Lr
Io
+
Ir
Vs o Lm
Co
RL
–
D2
– Rectifier to get DC output
– Changing frequency varies
voltage across RL
– Frequency-modulated
converter instead of PWM
Vo
Cr
+
Ir
Vs q
Texas Instruments—2010 Power Supply Design Seminar
Lr
Vs q
Im
Ios
Lm
RĹ
+
Vs o
Vs o
3-5
SLUP256
Design Prerequisites
• Operation
– fsw switching frequency
– f0 series resonant frequency (Cr and Lr)
– fco circuit resonant frequency (Cr Lr, and Lm, together RL)
Vg_Q1
Vg_Q1
Vg_Q1
Vg_Q2
Vg_Q2
Vg_Q2
Vsq
Vsq
Vsq
0
0
0
Ir
0
Im
Ir
0
Is
Im
Is
D1
D2
D2
D1
0
t1 t2
time,, t
fsw = f0
t3 t4
Im
Is
D1
0
t0
Ir
0
D2
0
t0
t1 t2
time,, t
fsw < f0
Texas Instruments—2010 Power Supply Design Seminar
t3 t4
t0
t1 t2
time,, t
t3 t4
fsw > f0
3-6
SLUP256
Design Prerequisites
• Modeling
M d li
– First harmonic approximation (FHA)
Cr
+
Lr
I m I os
Ir
Vs q
Cr
Lr
+
+
Vs o
Vs q
Ir
Lm
RĹ
R
L
–
Vge
Lm
Re
Im
I oe
+
Voe
–
Vs o
(a)
(b)
• Input and output: Square wave
voltages
• Input and output: Fundamental
components to approximate FHA
• Sinusoidal current in resonant
circuit
• Rectifier and RL equivalent to Re
Texas Instruments—2010 Power Supply Design Seminar
• AC circuit method can be used
3-7
SLUP256
Design Prerequisites
• Voltage gain function
– Expression from
impedance
p
divider
Cr
M g _ DC =
Lr
Ir
+
–
n × Vo
Vso
Voe
M g _DC =
≈ M g _ sw =
≈ M g _ ac =
Vin /2
Vsq
Vge
Vge
Lm
Re
Im
Ioe
+
Voe
–
=
n × Vo
V
≈ oe
Vin /2
Vge
( jωL m ) || R e
( jωL m ) || R e + jωL r +
1
jω C r
where ω = 2πf = 2πfsw and j = −1
Texas Instruments—2010 Power Supply Design Seminar
3-8
SLUP256
Design Prerequisites
• Voltage gain function
M g _DC =
– Expression
((Normalization))
Mg =
Normalized
Gain
Vo
Mg =
Vin /2
Resonant
Frequency
f0 =
1
2π L r C r
n × Vo
V
V
≈ M g _ sw = so ≈ M g _ ac = oe
Vin /2
Vsq
Vge
L n × f n2
[(L n + 1) × f n2 − 1] + j[(f n2 − 1) × f n × Qe × L n ]
Quality Factor
Qe =
L r /Cr
Re
Normalized
Frequency
Inductor
Ratio
fsw
fn =
f0
Lm
Ln =
Lr
Eq. Load R.
8× n2
Re = 2 × RL
π
Texas Instruments—2010 Power Supply Design Seminar
3-9
SLUP256
Design Prerequisites
• Voltage gain function
– Plots of gain magnitude, fixed Ln = 5
– Qe (load current) increases ⇒ peak gain decreases ⇒ curves shrink
2
1.8
1.6
Gain
1.4
1.2
Qe
Mg_pk
Qe = 0.5
1
0.8
Qe = 0.1
Qe = 10
0.6
0.4
0.2
0
0.1
1
Normalized Frequency
Texas Instruments—2010 Power Supply Design Seminar
10
3-10
SLUP256
Design Prerequisites
• Voltage gain function
– Plots of gain magnitude, fixed Qe = 0.5
– Ln decreases ⇒ peak gain increases ⇒ ZVS obtained but conduction
losses increase
2
18
1.8
1.6
Gain
1.4
Ln = 10
Ln = 5
Ln
Ln = 3
Mg_pk
12
1.2
1
0.8
06
0.6
0.4
0.2
0
0.1
1
Normalized Frequency
Texas Instruments—2010 Power Supply Design Seminar
10
3-11
SLUP256
Design Considerations
• Where to base a design?
– In the vicinity of series resonance, fn = 1 ⇒ narrowest frequency variation
⇒ Mg able to = 1, >1, and <1
– Right side of the resonant peak ⇒ ZVS requirement
Frequency in operation
1.6
Qe = 0
Gain, M g
1.4
a3
a2
Q e = max
1.2
a0
1
Qe = 0
0.8
a1
a4
0.6
0.5
1
Normalized Frequency, fn
Texas Instruments—2010 Power Supply Design Seminar
2
3-12
SLUP256
Design Considerations
• Line and load regulation
– Properly set up Mg_max and Mg_min
– Frequency limit set up
1.6
Gain
n, M g
1.4
1.2
a3
3
Qe = 0
Q e = max at full load
a2
M g_
g m a x=
n x Vo_ m a x
Vin_ m in /2
Q e = max
a0
1
Qe = 0
0.8
a1
a4
0.6
f n_min
n min
1
Q e = max
Normalized Frequency, fn
Texas Instruments—2010 Power Supply Design Seminar
M g_ m in =
n x Vo_ m in
Vin_ m a x/2
Q e = 0 at no load
fn_max
n max
3-13
SLUP256
Design Considerations
• Overload
O l d currentt operation
ti
– Qe = max to include and meet the required Mg_max
– Operation still on the right side of resonant peak
Frequency in operation
1.6
Qe = 0
Gain, M g
1.4
1.2
a3
M g_ m a x=
a2
n x Vo_ m a x
Vin_ m in /2
Q e = max
a0
1
Qe = 0
0.8
M g_ m in
i =
a1
a4
0.6
f n_min
1
Q e = max
Normalized Frequency, fn
Texas Instruments—2010 Power Supply Design Seminar
n x Vo_ m in
Vin_ m a x/2
Qe = 0
fn_max
3-14
SLUP256
Design Considerations
• Load short circuit
• Protection options
– Increase fsw rapidly to reduce Mg to zero
– Operation with fn > 1, i.e., fsw > f0 at all times
– Independent protection function
2
1.8
Qe = 0
1.6
Gain, M g
1.4
a3
M g_ m a x =
a2
n x Vo_ m a x
Vin_ m in/2
1.2
a0
1
a1
0.8
a4
0.6
ur
ve
Curve 1
(Qe = 0)
n x Vo_ m in
Vin_ m a x/2
2 (
Qe
Cu
=m
r ve
ax)
3
C urv
e4
0.4
0.2
0
0.1
C
M g_ m in =
f n_ m in
1
f n_ m a x
10
Normalized Frequency, fn
Texas Instruments—2010 Power Supply Design Seminar
3-15
SLUP256
Design Considerations
• Zero voltage switching (ZVS)
– How ZVS is achieved?
Vg_
g Q1
Vg_ Q2
Q1
Vg
Vin
+
–
CD S1
Lr
Vs q
Ir
Q2
Vg
CD S2
Lm
n:1:1
1 1
Q1 Turns Off
Vs q
Vds _ Q2 = 0
0
Ir
Im
Cr
Q2 Turns On
Im
0
Q2: Cds Discharge,
Body Diode
Turns On
t de a d
t0
Texas Instruments—2010 Power Supply Design Seminar
t1 t2
time, t
t3 t4
3-16
SLUP256
Design Considerations
• Zero voltage switching (ZVS)
– Necessary condition
• Input impendence of the resonant network inductive
• Operation
p
on the right
g side of the resonant p
peak
– Sufficient condition
• Enough energy stored in the magnetic field, mainly Lm
• Enough time to discharge the capacitors
capacitors, mainly CDS
Texas Instruments—2010 Power Supply Design Seminar
3-17
SLUP256
Design Considerations
• Why not design on the left side of the resonant peak?
– Capacitive current results
– ZVS lost
Hard switching
Switching losses increase
– Body diode reverse recovery losses
Primary MOSFET failure
– Higher EMI noise
– Reversed frequency relationship to feedback loop
Texas Instruments—2010 Power Supply Design Seminar
3-18
SLUP256
Design Considerations
• Design Steps – How to initially select?
– fsw, switching
it hi ffrequency
– n,
transformer turns ratio
– Ln, inductance ratio
– Qe, series resonant quality factor
Texas Instruments—2010 Power Supply Design Seminar
3-19
SLUP256
Design Considerations
• Design Steps – Switching frequency
– Usually selected for particular applications
• Example in off-line applications: Typical below 150 kHz
– Selecting
g the switching
g frequency
q
y
• f decrease ⇒ Bulkier converter
• f decrease ⇒ Switching losses decrease ⇒ ZVS benefit decrease
• f increase ⇒ ZVS benefits increase vs. hard switching converters
• Very High f :
– Component availability
– Additional
Addi i
l switching
i hi llosses
– Additional concerns due to parasitic effects
Texas Instruments—2010 Power Supply Design Seminar
3-20
SLUP256
Design Considerations
• Design Steps – Transformer turns ratio, n
– Voltage gain can be larger and smaller than unity
– Flexibility in selecting the turns ratio, n
– Turns ratio design with Mg =1, initially, and nominal Vin and Vo
Vin / 2 Vin _ nom / 2
n = Mg ×
=
Vo
Vo_ nom
Texas Instruments—2010 Power Supply Design Seminar
Mg = 1
3-21
SLUP256
Design Considerations
• Design
D i St
Steps – Ln and
d Qe
– Ln and Qe to achieve
Mg_p
g pk > Mg_
g max for maximum
load
– Initial selection
• Ln = 5
• Qe = 0.5
05
– Example: Select Ln and Qe
for Mg_max = 1.2
– To achieve design margin –
Final selection
• Ln - 3.5, Qe = 0.45
Ln = 1.5
Ln = 2.0
Ln = 3.0
Ln = 4.0
Ln = 5.0
Ln = 6.0
60
Ln = 8.0
Ln = 9.0
2.8
Attainable
e Peak Gain, M g_ pk
– Select Ln and Qe from preplotted peak gain curves
3.0
2.6
Ln = 3.0
2.4
Ln = 3.5 by
Interpolation
M g_ pk = 1.56
Qe = 0.45
2.2
2.0
18
1.8
Ln = 1.5
1.6
Ln = 5
M g_ pk = 1.2
Qe = 0
0.5
5
1.4
1.2
1.0
0.15
• 30% margin over
o er
Texas Instruments—2010 Power Supply Design Seminar
0.35
0.55
0.75
0.95
Quality Factor, Qe
1.15
3-22
SLUP256
Design Considerations
• Design Steps – Trade-offs to select Ln and Qe
– Different requirements for different applications
– Fixed Qe, Ln decrease ⇒ peak gain increase ⇒ good for ZVS
and
a
da
avoids
o ds capacitive
capac t e current
cu e t
– But, Ln decrease ⇒ Lm decrease ⇒ conduction losses increase
– Fixed Ln, Qe decrease ⇒ peak gain increase ⇒ frequency
variation increase
– Recommend starting with Ln = 5, and Qe = 0.5 (from design
practice)
Texas Instruments—2010 Power Supply Design Seminar
3-23
SLUP256
Design Considerations
• Resonant circuit design flow
3.0
Ln = 1.5
Ln = 2.0
Ln = 3.0
Ln = 4.0
Ln = 5.0
Ln = 6.0
Ln = 8.0
Ln = 9.0
Atttainable Peak Gain, Mg_ap
2.8
2.6
Ln = 3.0
24
2.4
Ln = 3.5 by
Interpolation
Mg_ap = 1.56
Qe = 0.45
2.2
2.0
1.8
Ln = 5
Mg_ap = 1.2
Qe = 0.5
1.4
1.2
1.0
0.15
0.35
n=
Mg_min =
L n = 1.5
1.6
Converter Specifications
0.55
0.75
0.95
Quality Factor, Qe
1.15
Vin
2Vo
Magnetizing
Inductance
n × Vo _min
Vin_ max / 2
L m = Ln × Lr
Resonant
Inductor
n × Vo_ max
Mg_max =
Vin_ min / 2
Lr =
Ch
Choose
Ln and
d Qe
1 .9
L n = 3 .5
f n_m in = 0 .6 5
Gain, Mg
1 .5
Q e = 0 .4 7
M g_m ax = 1 .3
Check M gand f n
Against Graph
Change
L n and Qe
1 .3
M g_m in = 0 .9 9
1 .1
0 .9
Q e = 0 .5 2
0 .7
0 .5
f n_ m aax = 1 .0 2
0
0 .5
1
1 .5
Are Values
Within
Limits?
Mg_m ax
Mg_m in
i
fn_m ax
fn_m in
Texas Instruments—2010 Power Supply Design Seminar
2
(2 πf sw) × C r
Resonant
Capacitor
Qe = 0
1 .7
1
No
Yes
Cr =
π
1
Calculate R e
2
2
V2
Re = 8 ×2n × R L = 8 ×2n × o
π
π
Pout
3-24
SLUP256
Design Considerations
• Design example
– Specifications
• Rated output power: 300 W
p voltage:
g 375 to 405 VDC
• Input
• Output voltage: 12 VDC
• Rated output current: 25 A
• Efficiency (Vin = 390 VDC and Io = 25 A): >90%
• Switching frequency: 70 kHz to 150 kHz
• Topology: LLC resonant half-bridge converter
Texas Instruments—2010 Power Supply Design Seminar
3-25
SLUP256
Design Considerations
• Design example
– Proposed converter circuit block diagram
DT1
Q1
Lr
Cin
T1
n:1:1
Ir
Vo
Io
Lm
Q2
Co
RL
Cr
ID 1
D1
U1
8
5
7
CB
6
GD1
OC
UCC25600
GD 2
VCC
GND
RT
DT
SS
3
ID 2
D2
Vs
RT1
2
+
R o1
U2
1
RT2
4
C SS
Cf
RD T
Rf1
R o2
U3
Texas Instruments—2010 Power Supply Design Seminar
3-26
SLUP256
Design Considerations
• Design example – UCC25600 Features
– 8-pin SOIC package
– Programmable:
8-pin SOIC (D), Top View
Drive 1
DT
1
8
GD1
• fmin and fmax
RT
2
7
VCC
• soft start time
OC
3
6
GND
SS
4
5
GD2
• dead time
– Protection
• OCP: hiccup and latch-off
Drive 2
• VDD UVLO and OVP
• OTP
– Burst operation
Texas Instruments—2010 Power Supply Design Seminar
3-27
SLUP256
Design Considerations
• Resonant circuit design flow
3.0
Ln = 1.5
Ln = 2.0
Ln = 3.0
Ln = 4.0
Ln = 5.0
50
Ln = 6.0
Ln = 8.0
Ln = 9.0
Atttainable Peak Gain, Mgg_ap
2.8
2.6
Ln = 3.0
2.4
Ln = 3.5 by
Interpolation
Mg_ap = 1.56
Qe = 0.45
2.2
2.0
1.8
L n = 1.5
1.6
1.2
1.0
0.15
0.35
0.55
0.75
0.95
Quality Factor, Qe
1 .9
f n_m in = 0 .6 5
1 .5
Gain, Mg
L n = 3 .5
Qe = 0
1 .7
1.15
M g_m ax = 1 .3
Q e = 0 .4 7
M g_m in = 0 .9 9
n × Vo _min
Vin_ max / 2
Mg_max =
n × Vo_ max
Vin_ min / 2
0 .9
Q e = 0 .5 2
0 .7
0 .5
f n_m ax = 1 .0 2
0
0 .5
1
1 .5
L m = Ln × Lr
Resonant
Inductor
Lr =
Ch
Choose
Ln and
d Qe
Texas Instruments—2010 Power Supply Design Seminar
1
2
(2 πf sw) × C r
Resonant
Capacitor
Check M gand f n
Against Graph
Are Values
Within
Limits?
Mg_m ax
Mg_m
g m in
fn_m ax
fn_m in
Lm = 210 µH
Lr = 60 µH
Cr = 27.3 nF
Magnetizing
Inductance
Mg_min =
Change
L n and
d Qe
1 .3
1 .1
Ln = 3.5
Qe = 0.45
V
n = in
2Vo
Ln = 5
Mg_ap = 1.2
Qe = 0.5
1.4
n = 16
Converter Specifications
No
Yes
Cr =
π
1
Calculate R e
2
2
Vo2
8
×
n
8
×
n
Re =
× RL =
×
π2
π2
Pout
3-28
SLUP256
Design Considerations
• Design check
1.9
Ln = 3.5
Qe = 0
1.7
Gain, Mg
1.5
f n_ m in = 0.65
(80 9 kHz)
(80.9
70 kHz
Q e = 0.47
Mg_ m a x = 1.3
1.3
11
1.1
Q e = 0.52
M g_ m in = 0.99
0.9
0.7
0.5
124.4 kHz
0
fn_
1 02
n m a x = 1.02
(126.9 kHz)
0.5
1
Normalized Frequency, fn
Texas Instruments—2010 Power Supply Design Seminar
150 kHz
1.5
3-29
SLUP256
Design Considerations
• Design
g check
–
–
–
–
–
–
Verification with computer-based circuit simulation
Design reiteration, if needed
Size/select components
Build the board
Verification with bench tests
Re-spin
Re
spin the board/design
board/design, if needed
Texas Instruments—2010 Power Supply Design Seminar
3-30
SLUP256
Design Considerations
• Experiment results (Lm = 280 µH
µH, Lr = 60 µH
µH, Cr = 24 nF)
Efficiency
Efficiency (%)
95
90 mV
405 V
390 V
375 V
75
65
1
5
10
15
Load Current ( A )
VCr
(200 V/div)
Resonant
N
Network
k
Voltages
(full load)
Output Ripple Voltage
(50 mV/div)
Input Voltage,
Vin
85
1
3
4
2
20
25
Time (5 µs/div)
Vgs _ Q2 (20 V/div)
1
Ir
(200 V/div)
VL
(1.2 A/div)
3
r
VL m
(200 V/div)
VC r
(100 V/div)
Vds _ Q2
(500 V/div)
Output
Ripple
Voltage
(full load)
4
2
Time (5 µs/div)
Texas Instruments—2010 Power Supply Design Seminar
Resonant
Network
C
Current
t
and
Voltage
((full load))
Vds _ Q2 (500 V/div)
Time (1 µs/div)
3-31
SLUP256
Test Result versus FHA from the Design
• In the vicinity of f0, FHAbased result very
accurate to the final test
resultlt (Lr = 60 µH
H and
d
Cr = 24 nF)
( 60,
60 1.57
1 57)
1.4
0.6
• Equation
Eq ation (18)
Mg =
=
jX Lm || R e
Voe
=
Vge ( jjX Lm || R e ) + j(X
j( Lr − X Cr )
( jωL m ) || R e
( jωL m ) || R e + jωL r +
( 65, 1.90)
(55, 1.27)
Gain, Mg
ay from
o f0, less
ess
• Away
accuracy from FHAbased result
2.0
Bench Test
Measurements
(80, 1.58)
Plot Based on
E
Equation
ti 18
( 100, 1.21)
(135, 0.99)
(170, 0.87)
( 40, 0.70)
( 30, 0.51)
0.0
10
( 200, 0.78)
( 240, 0.72)
( 400, 0.56)
f 0 = 135 kHz
100
Frequency, fs w (kHz)
1000
1
jω C r
Texas Instruments—2010 Power Supply Design Seminar
3-32
SLUP256
Conclusions
• FHA-based method approximately, while effectively,
converted complicated LLC resonant-converter circuit
to standard AC circuit – greatly simplified its analysis
and design
•M
Method
th d results
lt effective
ff ti ffor LLC converter
t d
design,
i
especially for initial parameters determination
• Design example with comprehensive design
considerations in procedural design steps
g method effectiveness
demonstrating
• Possibility of FHA-based approach for other resonant
converters
Texas Instruments—2010 Power Supply Design Seminar
3-33
SLUP256
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