Flip Flops and Counters
COMPUTER SCIENCE & ENGINEERING
Experiment 4
FLIP FLOPS & COUNTERS
Objectives
After completing this experiment, you will be able to:
-
The operation of flip-flops (JK and D-FFs).
-
Analyse and design asynchronous (up/down) counters using JK-Flip Flops.
-
Analyse and design a synchronous counter using JK-Flip Flops.
Materials Needed
-
2 INPUT-NAND GATE: IC 74LS00.
-
IC 74LS112: 2 JK-FFs.
-
IC 74LS74: 2 D-FFs.
-
IC 74LS47: BCD to 7-Segment Decoder/Driver
-
IC 74LS04: 6 NOT gates.
-
IC 74LS00: 4 NAND gates.
-
IC 74LS86: 4 XOR gates.
-
IC 74LS32: 4 OR gates.
-
IC 74LS02: 4 NOR gates.
For further investigation:
Materials to be determined by student.
Multisim: Assignment (Group # : all procedures)
Procedures
P1. Flip Flops
a. JK-FF (74LS112)
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Flip Flops and Counters
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SW0
K
Q
Q+
0
0
0
1
0
1
0
1
1
0
0
1
1
1
0
1
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
0
1
SW4/PULSE
2
74LS112
5
Q
LED DISPLAY
CLK
K
6
Q
LED DISPLAY
15
SW3
J
CLR
3
SW2
PRE
4
U2A
J
SW1
Figure 1. JK-Flip flop
Table 1. Truth Table of JK-FF
-
Implement the circuit shown in Figure 1
-
Check the active state of the signals PRE and CLR :
PRE
CLR
-
Verify the operation of JK-FF (fulfill the truth table shown in Table 1)
b. D-FF (7474)
SW0
CK
3
D
Q
5
Q
6
Q
0
0
1
0
0
1
1
1
Q+
LED DISPLAY
CLK
CLR
Pulse SW
PRE
4
U19A
2
D
LED DISPLAY
1
74LS74
SW1
Figure 2. D-Flip flop
Table 2. Truth Table of D-FF
-
Implement the circuit shown in Figure 2
-
Check the active state of the signals PRE and CLR :
PRE
CLR
-
Experiment to verify the operation of D-FF (fulfill the truth table shown in Table 2)
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Flip Flops and Counters
COMPUTER SCIENCE & ENGINEERING
P2. Analyse and design asynchronous counters
a. Implement an asynchronous up counter having M = 8 by using IC 74LS112
LED
LED
LED
3
1
CLK
K
4
10
Q
QN
7
2
J
High
PR
QN
12
J
Q
CL
K
6
PR
PR
13
CLK
High
9
QN
5
CLK
K
6
15
2
Q
11
15
High
1
High
5
14
Clock
J
CL
High
3
CL
4
SW1
High
SW2
74LS112
74LS112
74LS112
Figure 5 - Logic diagram
-
Implement the above circuit in figure 5. Control PR (SW1) and CL (SW2) to make the
circuit operate.
-
Observe and explain the results.
- Explanation: the three LEDs represents the three bits of the number from 0 to 7, after a
rising or falling edge of the clock, the LEDs displays the binary representation of x + 1
where x is the representation of the current bit string before exciting the clock.
b. Design an asynchronous up counter having M = 7 (or 6) by using IC 74LS112
-
Show the way to design:
Based on the truth table, we can see that CLR is the function NAND of three
outputs Q1, Q2, Q3. CLR = NAND(Q1, NAND(NAND(Q2, Q3)))
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Flip Flops and Counters
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-
Build the circuit
f(C,B,A) = CBA(1,3,5,6)
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c. Implement an asynchronous 3-bit down counter having M = 8 by using IC 74LS112.
LED
LED
LED
QN
6
12
PR
4
3
1
CLK
K
15
K
Q
7
QN
2
J
PR
CLK
J
Q
CL
13
High
9
QN
5
CLK
K
6
15
2
High
Q
11
CL
Clock
J
5
14
1
PR
High
High
CL
3
10
4
SW1
High
High
SW2
74LS112
74LS112
74LS112
Figure 7 - Asynchronous 3-bit down counter having M=8
-
Implement the above circuit shown in figure 7. The PR (SW1) and CL (SW2) inputs
are in the appropriate states to make the circuit operate:
PR : 1
CL : 1
-
Observe the results and give conclusions: the three LEDs represents the three bits of
the number from 0 to 7, after a rising or falling edge of the clock, the LEDs displays the
binary representation of x - 1 where x is the representation of the current bit string
before exciting the clock.
d. Implement an asynchronous 3-bit counter having M = 8, with a control for up/down
counting
LED
LED
LED
13
2
6
12
74LS86
15
QN
9
3
1
3
CLK
K
4
High
Q
1
2
QN
7
2
74LS86
High
J
PR
3
J
Q
CL
10
1
CLK
K
11
PR
PR
5
QN
5
CLK
K
6
15
2
High
High
Q
14
1
Clock
J
CL
3
High
CL
4
SW1
High
SW2
74LS112
74LS112
74LS112
SW3-Control
Figure 8 – Asynchronous 3-bit up counter having M = 8
-
Implement the above circuit shown in figure 8 (using IC74LS112 and 74LS86). The
PR (SW1) and CL (SW2) inputs are in the appropriate states to make the circuit
operate:
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COMPUTER SCIENCE & ENGINEERING
PR :
CL :
-
Observe the results when C = 0 and C = 1 and give conclusions: When SW3 is high, all
the clocks in 3 JK-FFs becomes the complement of the output from the previous JK-FF,
i.e. CLK = Q’, which is the same as the down counter from P2.c. Otherwise, CLK = Q,
which is the up counter from P2.a.
P3. Analyse and design synchronous counters
SW
12
74LS112
9
3
74LS08
1
CK
K
4
2
/Q
7
2
J
Q2
PR
/Q
6
Q
3
Q1
Q
CL
10
13
J
Q1
/Q
5
Q2
CLK
K
74LS112
6
74LS112
15
K
11
PR
5
CL
Q
Q0
CLK
15
2
Q0
14
1
J
CL
3
PR
4
1
SW
Clock
Figure 9
-
Implement the circuit shown in figure 9. The K inputs of FF0 and FF2 are connected to
High level. The PR (SW1) and CL (SW2) inputs are in the appropriate states to make
the circuit operate.
-
When the clock is active:
-
Write the excitation (trigger) input equations of all flip-flops:
J0 = …………………...............; K0 = ….……………...............
J1 = …………………...............; K1 = ….……………...............
J2 = …………………...............; K2 = ….……………...............
-
Draw the state diagram of the counter in Figure 10:
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