Lecture 1:Sequential circuit:
Edge-triggered D flip flop:
A D Flip Flop is the basic memory element in logic circuits. The output of a D FlipFlop tracks the input, making transitions which match those of the input. The D in D FlipFlop stands for Data. It can be thought of as a basic memory cell.. The output of the FlipFlop may be clocked. If the output is clocked then the D Flip-Flop is synchronous D FlipFlop. Synchronous D Flip-Flop, thus, has output which is synchronized with the either
the rising edge or the falling edge of the input clock pulse. The block diagram of synchronous
D Flip-Flop, which is clocked to the rising edge of input clock and its truth table are shown
below.
VHDL code for D flip flop:
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY flipflop IS
PORT ( D, Clock : IN STD_LOGIC ;
Q,QB: OUT STD_LOGIC) ;
END flipflop ;
ARCHITECTURE Behavior OF flipflop IS
BEGIN
PROCESS ( Clock )
BEGIN
IF Clock'EVENT AND Clock = '1' THEN
Q <= D ;
QB<= not D;
END IF ;
END PROCESS ;
END Behavior ;
–- rising edge of clock
Alternate Methode( Process without sensitivity list):
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY flipflop IS
PORT ( D, Clock : IN STD_LOGIC ;
Q,QB: OUT STD_LOGIC) ;
END flipflop ;
ARCHITECTURE Behavior OF flipflop IS
BEGIN
PROCESS
BEGIN
wait until Clock'EVENT AND Clock = '1';
Q <= D ;
QB<= not D;
END PROCESS ;
END Behavior ;
The description contains a synthesizable entity and architecture representing a D flipflop. The entity contains the clock, D, Q, QB ports needed for a D flip-flop, while the
architecture contains a single process statement with a single WAIT statement. When the
clock signal has a rising edge occur, the contents of D are assigned to Q. Effectively, this is
how a D flip-flop operates.
Note:
• clk’event is an “attribute” of signal clk
• clk’event = TRUE if an event has occurred on clk at the current simulation time and false if
no event on clk at the current simulation time
• clk‘stable is a complementary attribute (TRUE of no event at this time)
• There is a special functions in package std_logic_1164 for std_logic types called
rising_edge(clk) .
rising_edge(clk) is TRUE when clk changes its value from 0 to 1 or low to high.
• Similarly falling_edge(clk) is TRUE when clk changes its value from 1 to 0.
Example:
signal clk: std_logic;
begin
process (clk) -- trigger process on clk event
begin
if rising_edge(clk) then -- detect rising edge of clk
Q <= D ; -- Q and QB change on rising edge
QB <= not D;
end if;
end process;
D flip flop with reset :
Figure below shows the truth table of synchronous D Flip-Flop which is clocked to the rising edge of
input clock. The inputs to the D Flip-Flop are data-bit D, and control lines reset and clock. There are
two outputs Q and Q'.
library ieee;
use ieee.std_logic_1164.all;
entity DFF is
port(
D : in std_logic;
CLocK : in std_logic;
Reset : in std_logic;
Q, QB : out std_logic
);
end DFF;
architecture behavior of DFF is
begin
process(CLocK, Reset)
begin
if Reset = '0' then
Q <= '0';
QB<='1';
elsif rising_edge(Clock)then
Q <= D;
QB<= not D;
end if;
end process;
end behavior;
The ENTITY statement now has an extra input, the reset port, which is used to
asynchronously reset the D flip-flop. Notice that reset and clock are in the process sensitivity
list and cause the process to be evaluated.
If an event occurs on signals clock or reset, the statements inside the process are
executed. First, signal reset is tested to see if it has an active value (‘1’). If active, the output
of the flip-flop is reset to ‘0’. If reset is not active (‘0’), then the clock signal is tested for a
rising edge. If signal clock has a rising edge, then input din is assigned as the new flip-flop
output. The fact that the reset signal is tested first in the IF statement gives the reset signal a
higher priority than the clock signal. Also, because the reset signal is tested outside of the
test for a clock edge, the reset signal is asynchronous to the clock.
.