Topology Selection
By the Numbers – Part Two
By Ernie Wittenbreder, Chief Engineer, Technical Witts,
Flagstaff, Ariz.
In this second part of a three-part series, we
consider some of the alternatives to the bucks
and boosts discussed in part one for nonisolated
stepup and stepdown conversion for situations
in which there may be better choices.
I
n part one of this article series, we found that total component stress factors (CSFs)—a new analysis method
that enables the comparison of different power conversion topologies—for buck and boost converters were
the same for fixed-line voltage where the stepdown ratio
of the buck converter was equal to the stepup ratio of the
boost converter. In this second part, we focus on nonisolated
applications with limited line-voltage range.
Buck and boost converters are part of the same canonical
cell where the differences between the buck circuit and the
boost circuit are the line and load connections. We illustrate
this relationship in Fig. 1 where the circuit operates as a buck
converter for power flow from left to right and as a boost
converter for power flow from right to left.
Instead of treating the stepup and stepdown problems
separately, we recognize that a stepup converter is a stepdown
converter that operates with power flow reversed. Therefore,
any of the circuits in this second part of the article series
can be operated either as stepup or stepdown. In every case,
power flow from left to right will correspond to stepdown
conversion, and power flow from right to left will correspond
to stepup conversion.
In part one, we found that the lowest CSFs for the buck
converter occurred for stepdown ratios near 1 and that the
lowest CSFs for the boost converter occurred for stepup ratios near 1. We will consider the problem where the stepup
or stepdown ratio is near but not equal to 1, as well as some
alternatives to simple bucks and boosts.
Fig. 2 illustrates a tapped-inductor buck or boost, which
is an attractive candidate for small stepup and stepdown
ratios. The only difference between this converter and the
simple buck and boost of Fig. 1 is the second winding of the
choke placed in series with the lower MOSFET (MLOWER).
MUPPER
L
CIN/OUT +
–
To line/load
MLOWER
+ COUT/IN
–
To load/line
Fig. 1. The same canonical cell used for a buck converter for power flow
from left to right may be used for a boost converter for power flow
from right to left.
MUPPER
MUPPER
LUPPER
LUPPER
To line/load
CIN/OUT +
–
LLOWER
MLOWER
+ COUT/IN
–
To load/line
To line/load
CIN/OUT +
–
MLOWER
LLOWER
CMIDDLE +
–
+ COUT/IN
–
To load/line
MRESET
Fig. 2. A tapped-inductor boost or buck power converter topology suits
small line/load step ratios.
Power Electronics Technology April 2006
Fig. 3. In a minimum-voltage tapped-inductor converter, none of the
switching devices sees voltages greater than the line/load voltages.
28
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POWER TOPOLOGY
The circuit in Fig. 1 is contained
Figs. 1 and 2
Fig. 2
Fig. 2
Fig. 3
in the Fig. 2 circuit and represents
Turns
Turns
Turns
Turns
ratio = 0
ratio = 17.9
ratio = 1
ratio = 11.1
the case in which the turns ratio of
LLOWER to LUPPER is zero.
MUPPER SCSF
1.29
0.04
0.4
0.036
For Fig. 2, there will be a dif- M
SCSF
0.3
0.038
0.12
0.019
LOWER
ferent set of CSFs for each turns
MRESET SCSF
0
0
0
0.021
ratio, and the turns ratio can be
1.59
0.078
0.52
0.076
varied to achieve different results. Total SCSF
We will consider the case where the LUPPER WCSF
0
0.01
0.01
0.007
load/line at the right side of the cir- L
WCSF
0.01
0.009
0.002
0.005
LOWER
cuit is 380 V and the line/load at the
Total WCSF
0.01
0.019
0.012
0.012
left side of the circuit is 400 V at a
0.053
1.89
0.16
3.01
power level of 400 W. We also will CIN/OUT CCSF
consider the minimum-voltage COUT/IN CCSF
0
1.7
0.07
2.76
tapped-inductor converter[1], shown C
CCSF
0
0
0
0.15
MIDDLE
in Fig. 3, for the small ratio-converTotal CCSF
0.053
3.59
0.23
5.92
sion problem.
The Fig. 3 circuit is of minimum Table 1. Optimal CSF values for small step-ratio converters.
voltage in the sense that none of the
Figs. 1 and 5
Fig. 4
Fig. 5
Fig. 5
Fig. 6
transistors has voltage stress higher
Turns
Turns
Turns
Turns
Turns
than the load/line voltages. Refer
ratio=0
ratio=5
ratio=9.14
ratio=3
ratio=5
to part one of this article series for M
SCSF
40
1.61
13.4
13.7
6.4
UPPER
information on how to calculate
120
2.96
12.6
20.6
11.8
the CSF for each component. Table MLOWER SCSF
M
SCSF
0
1.64
0
0
6.5
1 summarizes optimized results for
RESET
Figs. 1, 2 and 3.
Total SCSF
160
24.8
26.1
34.3
24.8
For the Fig. 2 circuit, if we L
WCSF
0
0.4
2.9
1.7
1.6
UPPER
optimize component weights for
3.24
0.56
3
3.4
2.24
minimum total semiconductor LLOWER WCSF
Total
WCSF
3.24
3.84
5.9
5.1
3.84
component stress factor (SCSF),
we find that the optimal turns ratio CIN/OUT CCSF
9
0.39
1.7
2.9
2.3
is 17.9 and we achieve a 20 times C
CCSF
0
0.48
1.5
0.9
2.9
OUT/IN
reduction in total semiconductor
CMIDDLE CCSF
0
0.48
0
0
2.9
stress but at a cost. With a 17.9
9
1.35
3.3
3.8
8.1
turns ratio, the total winding com- Total CCSF
ponent stress factor (WCSF) has Table 2. Optimal CSF values for large step-ratio converters.
almost doubled and the capacitor
load/line voltage to line/load voltage differential is high.
component stress factor (CCSF) has increased by almost two
One way to solve this problem is by keeping MUPPER in its
orders of magnitude.
conducting state during the high differential voltage transiIn many applications, this may be a good tradeoff since
tion. All of the tapped-inductor power converters in this
the input capacitor requirement may be driven by an elecarticle achieve efficiency improvements by using MOSFETs
tromagnetic interference filter requirement or an interface
with lower voltage ratings than the peak dc voltages present
stability issue, such as Middlebrooke’s rule, and the output
in the circuit. One must consider the potential for the apcapacitor requirement may be driven by a load transient or
plication of voltages higher than the steady-state voltages to
ripple voltage requirement.
low-voltage MOSFETs during voltage transients, and impleTable 2 also illustrates a compromise case where the
ment necessary avoidance or protection mechanisms. Often,
turns ratio is selected to be 1-to-1. With a 1-to-1 turns ratio,
a single zener diode can eliminate the problem.
a substantial improvement in total SCSF is realized with
For a topology that has superior total SCSF and superior
more modest degradations in total WCSF and total CCSF.
total WCSF, a high CCSF can be dealt with by employing
The lower semiconductor component stresses are achieved
an interleaved multiphase configuration. Paralleling multiby using a low-voltage MOSFET for MUPPER.
phase subconverters has no effect on total SCSF or total
With a 17.9 turns ratio, MUPPER has a voltage stress of just
WCSF, but multiphasing reduces total CCSF by a factor
slightly greater than 40 V. The voltage stress on MUPPER can be
equal to or greater than the square of the number of parallel
large during a startup transition in the buck implementation
subconverters (Fig. 4).
and during a shutdown transition in the boost implementaIn the Fig. 3 circuit, MRESET operates in synchronization
tion, without some mechanism to protect MUPPER while the
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29
Power Electronics Technology April 2006
POWER TOPOLOGY
+ –
CMIDDLE
CIN/OUT +
–
To line/load
LUPPER1
LLOWER1
MUPPER1
MRESET1
MLOWER1
LUPPER2
LUPPER
+ COUT/IN
–
To load/line
CIN/OUT +
–
To line/load
Fig. 5. This tapped-inductor power converter topology suits large line/
load step ratios.
MLOWER2
be a candidate for small step ratios is the isolated flyback
converter with the secondary circuit connected to line and
load but not to ground.
Another problem where candidate topologies exist that
compete well with simple bucks and boosts is the problem
of large step ratios. We consider the problem of stepping
from 100 V to 1000 V and from 1000 V to 100 V in a 100W converter. We will not consider the effects of wide linevoltage variations at this time. The candidate topologies that
we will consider are the buck and boost of Fig. 1, the tappedinductor buck and boost for large step changes (Fig. 5),
the minimum-voltage tapped-inductor buck and boost
for large step changes (Fig. 6) and a multiphase implementation of the Fig. 6 circuit in which two parallel subconverters share the same set of three capacitors, illustrated
in Fig. 4.
Table 2 illustrates the results achieved. The simple buck
and boost converters of Fig. 1 have high SCSFs because the
switches have both high voltage stress and high current stress.
In the Fig. 5 circuit optimized for minimum total SCSF,
MUPPER has high voltage stress (slightly less than 2 kV) but
low current stress, and MLOWER has high current stress but
low voltage stress (slightly less than 200 V). The circuit in
Fig. 5 achieves a 6-to-1 reduction in total SCSF compared
to that in Fig. 1. The Fig. 5 circuit also achieves a reduction in total CCSF, but total WCSF increases by almost a
factor of 2.
The Fig. 6 circuit achieves slightly lower total SCSF than
the Fig. 5 circuit and significantly lower WCSF, only about
20% higher than the simple buck and boost, but the total
CCSF is only slightly lower than the Fig. 1 circuit and significantly higher than the tapped-inductor circuit of Fig. 5.
In the Fig. 6 circuit, the voltage stresses of MUPPER, MLOWER
and MRESET are 1000 V, 167 V and 833 V, respectively. We address the issue of high CCSF by implementing a two-phase
converter based on the Fig. 6 circuit in which the capacitors
are shared between the two subconverters.
We use the rules presented in part one of this article series to calculate the total SCSF and total WCSF for the dual
subconverter combination. Since we only have one set of
capacitors, we must calculate CCSFs for each capacitor again,
considering that the capacitor currents are a combination
of currents from the two subconverters. Fortunately, the
Fig. 4. In multiphase minimum-voltage tapped-inductor converters for
large line/load step ratios, each capacitor is equally shared by each phase.
with MUPPER. CMIDDLE is charged during the time that MLOWER
conducts and is discharged when MUPPER and MRESET are on.
Results for the Fig. 3 circuit indicate that it provides SCSF
improvements that are slightly better than those achieved by
the Fig. 2 circuit, but with much lower total WCSF and an
even greater increase in total CCSF. There are practical zerovoltage switching (ZVS) variations for each of the figures
illustrated, but the Fig. 3 circuit requires no additional active
switches to accomplish ZVS. Another topology that might
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Power Electronics Technology April 2006
MLOWER
+ COUT/IN
–
To load/line
LLOWER2
MUPPER2
MRESET2
LLOWER
MUPPER
30
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POWER TOPOLOGY
capacitor currents from the two subconverters cancel each
other to a large extent due to the fact that the subconverters
are operated 180° out of phase. For the MOSFET MUPPER1 the
peak voltage stress is 1000 V, the on-state current is 0.0835
A and the duty cycle is 0.599. The root-mean-square (RMS)
current in MUPPER1 is:
+ –
CMIDDLE
2
By optimizing for minimum total SCSF, we find that the
optimal weight for MUPPER1 is 0.992 and the sum of the semiconductor weights is 3.822. The SCSF for MUPPER1 is:
SCSFMUPPER 1 =
∑
WI
MLOWER
The RMS current in LLOWER2 is given by:
WMUPPER 1
2
(PTOTA
TOTAL
L)
MRESET
+ COUT/IN
–
To load-line
Fig. 6. A minimum-voltage tapped-inductor converter for large line/load
step ratios keeps all switching device voltages within line/load values.
SEMICONDUCTORS
2
(VPE
)2
PEAK
AK MUPPER 1 ) (I RMSMU
UPPE
PPER 1
LLOWER
MUPPER
CIN/OUT +
–
To line-load
IRMS = DI
DI = (0.599)(0.0835 A) = 0.0646 A.
2
LUPPER
IRMS =
3.822
=
0.992
∑D I
2
I I
=
I
(0.599)(0.0835 A)2 + (0.401)(1.122 A)2 = 0.714 A.
The weight assigned to LLOWER2 is 1.4 and the sum of the
winding weights is 2.4. The CSF for LLOWER2 is:
(1000 V)2 (0.0646 A)2
= 1.6611.
(100 W)2
For MLOWER1 the SCSF is 2.96 and for MRESET1 the SCSF is
1.64, so that the total subconverter SCSF is 6.2. Since the
second subconverter is identical to the first except for operating phase, its total subconverter SCSF is also 6.2. For the
total SCSF for a combination of subconverters in part one
of this article series, we defined:
∑ WJ
SEMICONDUCTORS
Totall SCSF=
(Total
Total SCSFI ),
∑
WI
SUBCONVERTERS
WCSFLLOWER 2 =
∑
WINDINGS
Wi (V
2
2
L LOWER 2 ) (I R
RMS
MSLLOWER 2 )
2
(PTTOTA
OTAL )
WLLOWER 2
=
2.4 (80.2 V)2 (0.714 A)2
= 0.56
56.
1.4
(100 W)2
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where WI is the semiconductor subconverter weight
∑ WJ is the sum of
for subconverter I, SEMICONDUCTORS
semiconductor weights and Total SCSFI is the total SCSF
for subconverter I. We want the two subconverters in a
multiphase arrangement to be equal in every respect except
phasing, so we will assign a semiconductor subconverter
weight of 1 to each subconverter.
In this case:
∑ WJ = 1 + 1 = 2.
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For the combination of subconverters the total SCSF is:
2
2
Total SCSF= 6.2 + 6.2 = 24.8,
1
1
which is the same result we had for Fig. 6. We would
expect there to be no advantage or disadvantage to breaking
the converter into two parallel subconverters—each operating at half power—and the calculated total SCSF confirms
that fact.
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VLLOWER 2 = ∑ DI VI = (0.599)(66.9 V)+
I
(0.401)(100 V)=80.2 V.
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Power Electronics Technology April 2006
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POWER TOPOLOGY
For LUPPER2 the WCSF is 0.40 and the total WCSF for the subconverter is 0.96.
We assign a winding subconverter weight of 1 to each subconverter so that the
sum of the winding subconverter weights is 2. For the combined system:
∑
∑
Total WCSF=
SUBCONVERTERS
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Power Electronics Technology April 2006
WJ
WINDINGS
WI
×
2
2
(Total
Total WCSFI ) = 0.96 + 0.96
96 = 3.84,
1
1
which is identical to the total WCSF obtained for the single-phase circuit, as
expected.
Finding the total CCSF for the Fig. 4 circuit presents a different problem,
because the three capacitors shown in Fig. 4 are shared by two subconverters.
We calculate each CCSF considering that the capacitor currents are formed by
algebraic sums of currents from the two subconverters. We assume that subconverter 1 is beginning its operating cycle and subconverter 2 is halfway through
its operating cycle.
The average line/load current is P/VLINE/LOAD , or 0.1 A. For CIN/OUT the capacitor
current is the difference between the average line/load current and the sum of
currents in MUPPER1 and MUPPER2. At the beginning of an operating cycle for a duty
cycle of (0.599 - 0.500) = 0.099, both MUPPER1 and MUPPER2 conduct so that the
CIN/OUT net current is 0.0835 A  0.0835 A  0.1 A = 0.067 A. In the subsequent
phase of the operating cycle, MUPPER2 turns off and the net current is 0.0835 A 
0.1 A = - 0.0165 A. The duty cycle for the second phase is 0.401.
During the next phase of the operating cycle, with duty cycle equal to 0.099,
MUPPER2 is on again and the net CIN/OUT current is 0.067 A. During the last phase,
MUPPER1 is off, the duty cycle is 0.401 and the current is -0.0165 A. The RMS current
in CIN/OUT is 0.033 A. To achieve optimal (minimal) total CCSF, a weight of 0.964
is assigned to CIN/OUT . The sum of capacitor component weights is 3.364. We can
now calculate a CCSF for CIN/OUT :
CCSF
FCIN / OUT =
∑
CAPACITORS
WI (V
2
2
C IN / OUT ) (I R
RMS
MSCIN / OUT )
WCIN / OUT
(PTOTAL )2
=
3.364 (1000 V)2 (0
(0.033 A)2
= 0.386.
0.964
(100 W)2
For COUT/IN and CMIDDLE the CCSF is 0.48, and the total CCSF for Fig. 4 is 1.346.
Among the many benefits of parallel multiphase converters is much-reduced capacitor component stress, which translates directly into higher efficiency. Compared
to Fig. 6, Fig. 4 has improved total CCSF by a factor of 6. In general, multiphasing
improves total CCSF by a factor equal to or greater than the square of the number
of subconverters, if the topology enables capacitor sharing. Comparing Fig. 4 with
Fig. 1, we achieve much-improved total SCSF and total CCSF, for a 20% increase
in total WCSF, but with a much larger component count.
With sets of operating equations for candidate circuit topologies and a spreadsheet or other mathematical computation program, one can readily generate
a set of numbers for numerical topological comparison using the CSF method.
An Excel spreadsheet illustrating the calculations in this article is available at
www.TechnicalWitts.com. Next month, in the third and final part of this article
series, we will compare isolated topologies and consider the effects of wide linevoltage range on power converters.
PETech
References
1. Wittenbreder, E.H., “Tapped Inductor Power Conversion Networks,” U.S.
Patent Application 60/757561. Available online at www.technicalwitts.com.
32
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