iD6309
Li+ Charger Protection IC with Integrated PMOS
General Description
Features
The iD6309 provides complete Li+ charger protection
„
Input Over-Voltage Protection
against input over-voltage, input over-current, and
„
Input Over-Current Protection
battery over-voltage. When any of the monitored
„
Battery Over-Voltage Protection
parameters are over the threshold, the IC removes the
„
High Immunity of False Triggering
power from the charging system by turning off an
„
High Accuracy Protection Threshold
internal switch. All protections also have deglitch time
„
Thermal Shutdown Protection
against false triggering due to current transients or
„
A Built-In P-MOSFET
voltage spike.
„
Available in a TDFN2x2-8 Package
The iD6309 integrates a power PMOS with body
„
Lead Free and Green Devices Available
diode leakage protection to replace the external
(RoHS Compliant)
PMOS and Schottky diode for the charger function of
cell phone’s PMIC. When CHRIN drops below VBAT
Applications
+20mV, the internal detector will activate the leakage
„
protection mechanism to prevent leakage current from
Mobile Phones
battery back to CHRIN.
The iD6309 provides complete Li+ charger protections
and saves external PMOS and Schottky diode for the
charger function of cell phone’s PMIC. The above
feature and small package make iD6309 an ideal part
for cell phone application.
Ordering Information
Apr. 2011
1
Rev 0.7
iD6309
Typical Application Circuit
Absolute Maximum Ratings
Recommended Operating Conditions
ACIN Input Voltage VACIN
30V
CHRIN Voltage VCHRIN
7V
GATDRV Voltage VGATDRV
7V
VBAT Voltage VBAT
7V
OUT Voltage VOUT
7V
OUT Output Current IOUT
1.5A
Power Dissipation, PD @ TA=25°C
TDFN-8
1.25W
Thermal Resistance, θja
TDFN-8
80°C/W
Lead Temperature
260 °C
Storage Temperature
-65°C to 150°C
ESD Susceptibility
HBM (Human Body Mode)
2kV
MM (Machine Mode)
200V
Compliance to IEC61000-4-2(Level 4)
± 8kV (Contact Discharge)
± 15kV (Air Discharge)
ACIN Input Voltage VACIN
Output Current IOUT
Junction Temperature Range
Ambient Operating Temperature
4.5V to 5.5V
0~700mA
-40°C to 125°C
-40°C to 85°C
Pin Configurations
(Top View)
TDFN-8L
Apr. 2011
2
Rev 0.7
iD6309
Pin Function
Pin No.
Pin Name
I/O
Pin Function
1
ACIN
I
2
ACIN
I
3
GND
–
Ground Terminal.
Power Supply Input. Connect this pin to external DC supply. Bypass to GND with a
1μF (minimum) ceramic capacitor.
4
VBAT
I
Battery Voltage Sense Input. Connect this pin to pack positive terminal through a
resistor.
5
GATDRV
I
Internal P-MOSFET Gate Input.
6
CHRIN
O
CHRIN Output Pin. This pin provides supply voltage to the PMIC input. Bypass to
GND with a 1μF (minimum) ceramic capacitor.
7
OUT
O
8
OUT
O
Output Pins. These pins provide supply source current in series with a resistor to
battery.
–
EP
–
Exposed Thermal Pad. Must be electrically connected to the GND pin.
Function Block Diagram
Apr. 2011
3
Rev 0.7
iD6309
Electrical Characteristics (Unless otherwise specified, these specifications apply over VACIN=5V, VBAT=3.8V
and TA= -40 ~ 85°C. Typical values are at TA=25°C.)
Parameter
Symbol
Test Condition
Min
Typ
Max
Units
450
550
μA
2.8
V
300
mV
ACIN INPUT CURRENT AND POWER-ON-RESET (POR)
ACIN Supply Current
IACIN
IOUT=0A, ICHRIN=0A
ACIN POR Threshold
VACIN
VACIN rising
2.4
ACIN POR Hysteresis
ACIN Power-On Blanking Time
200
TB(ACIN)
250
8
ms
0.5
Ω
500
Ω
INTERNAL SWITCH ON RESISTANCE
ACIN to OUT On Resistance
IOUT=0.7A
CHRIN Discharge On Resistance
INPUT OVER-VOLTAGE PROTECTION (OVP)
Input OVP Threshold
VOVP
VACIN rising
iD6309A
6
6.17
6.35
iD6309B
6.6
6.8
7
Input OVP Hysteresis
300
Input OVP Propagation Delay
Input OVP Recovery Time
mV
1
TON(OVP)
V
μs
8
ms
IOCP
1.3
A
OCP Blanking Time
TB(OCP)
176
μs
OCP Recovery Time
TON(OCP)
64
ms
OVER CURRENT PROTECTION (OCP)
OCP Threshold
BATTERY OVER VOLTAGE PROTECTION
Battery OVP Threshold
VBOVP
VBAT rising
Battery OVP Hysteresis
4.32
4.35
4.38
270
VBAT Pin Leakage Current
IVBAT
Battery OVP Blanking Time
TB(BOVP)
VBAT = 4.4V
mV
20
nA
μs
176
INTERNAL P-MOSFET (CHRIN, OUT AND GATDRV PINS)
VCHRIN from low to high, P-MOSFET is
controlled by GATDRV
VCHRIN-VBAT Lockout Threshold
VCHRIN from high to low, P-MOSFET is
off
OUT Input Current
VCHRIN=0V, VOUT=4.2V, GATDRV=GND
V
150
mV
20
1
μA
GATDRV Leakage Current
VACIN=VCHRIN= VOUT=5V, VGATDRV=0V
1
μA
OUT Leakage Current
VACIN=VCHRIN= VGATDRV =5V, VOUT=0V
1
μA
P-MOSFET Input Capacitance
200
pF
GATDRV Input Resistance
15
Ω
160
°C
40
°C
OVER-TEMPERATURE PROTECTION (OTP)
Over-Temperature Threshold
TOTP
TJ rising
Over-Temperature Hysteresis
Apr. 2011
4
Rev 0.7
iD6309
Typical Operation Characteristics (V
ACIN
= 5.0V, VBAT = 3.8V, CACIN = 1μF (X5R ceramics), CCHRIN = 1μF (X5R
ceramics), RBAT = 200kΩ (SMD Type), ROUT = 0.2Ω (SMD Type), TA = 25℃.)
OCP vs. Temperature
7.2
1.60
7
1.50
OCP Threshold (A)
ACIN OVP Threshold (V)
ACIN OVP vs. Temperature
6.8
6.6
6.4
Increasing
6.2
1.30
1.20
1.10
Decreasing
6
1.00
-25
0
25
50
75
100
125
-50
50
75
100
125
ACIN to OUT Resistance vs. Temperature
4.2
4.1
4.0
Increasing
3.9
Decreasing
3.8
-25
0
25
50
75
100
125
0.9
0.8
0.7
0.6
0.5
0.4
0.3
IOUT = 500mA
0.2
-50
-25
0
25
50
75
100
125
Junction Temperature (℃)
Junction Temperature (℃)
ACIN Supply Current vs. Temperature
ACIN POR vs. Temperature
475
2.8
ACIN POR Threshold (V)
450
ACIN Supply Current (μA)
25
Battery OVP vs. Temperature
4.3
425
400
375
350
325
2.6
2.4
2.2
2
1.8
Increasing
Dncreasing
1.6
300
-50
-25
0
25
50
75
100
-50
125
-25
0
25
50
75
100
125
Junction Temperature (℃)
Junction Temperature (℃)
Apr. 2011
0
Junction Temperature (℃)
4.4
-50
-25
Junction Temperature (℃)
ACIN to OUT Resistance RDS(ON) (Ω)
-50
Battery OVP Threshold (V)
1.40
5
Rev 0.7
iD6309
Operating Waveforms
(VACIN = 5.0V, VBAT = 3.8V, CACIN = 1μF (X5R ceramics), CCHRIN = 1μF (X5R ceramics), RBAT = 200kΩ
(SMD Type), ROUT = 0.2Ω (SMD Type), TA = 25℃.)
Normal Power On
OVP at Power On
VACIN (DC)
(5.00V/Div)
VACIN (DC)
(10.0V/Div)
VCHRIN (DC)
(2.00V/Div)
VOUT (DC)
(2.00V/Div)
VCHRIN (DC)
(2.00V/Div)
IOUT (DC)
(200mA/Div)
VOUT (DC)
(2.00V/Div)
VGATDRV = VCHRIN
VACIN = 0 to 12V, VGATDRV = VCHRIN
Time (2.00ms/Div)
Time (2.00ms/Div)
ACIN Over-Voltage Protection
Recovery from Input OVP
VACIN (DC)
VACIN (DC)
(5.00V/Div)
(5.00V/Div)
VCHRIN (DC)
VCHRIN (DC)
(2.00V/Div)
(2.00V/Div)
VACIN=5V to 12V
VACIN=12V to 5V
Time (20.0μs/Div)
Time (10.0ms/Div)
Battery Over-Voltage Protection
Battery Over-Voltage Protection
VBAT (DC)
VBAT (DC)
(1.00V/Div)
(1.00V/Div)
VCHRIN (DC)
VCHRIN (DC)
(2.00V/Div)
(2.00V/Div)
VBAT = 3.6V to 4.4V to 3.6V
Time (100ms/Div)
Apr. 2011
VBAT = 3.6V to 4.4V
Time (400μs/Div)
6
Rev 0.7
iD6309
Over-Current Protection
Over-Current Protection
VACIN (DC)
(5.00V/Div)
VOUT (DC)
(5.00V/Div)
VCHRIN (DC)
(2.00V/Div)
VCHRIN (DC)
(5.00V/Div)
IOUT (DC)
(1.00A/Div)
VOUT (DC)
(2.00V/Div)
IOUT (DC)
(1.00A/Div)
VBAT = VGATDRV = 0V, ROUT = 2.5Ω
Time (100μs/Div)
Time (200ms/Div)
Apr. 2011
VBAT = VGATDRV = 0V, ROUT = 10Ω to 2.4Ω
7
Rev 0.7
iD6309
Function Description
battery OVP fault reaches 16, the FET is turned off
ACIN Power-On-Reset (POR)
permanently, requiring a VACIN POR again to restart.
The iD6309 has a built-in power-on-reset circuit to keep
Over-Temperature Protection
the output shutting off until internal circuitry is operating
When the junction temperature exceeds 160°C., the
properly. The POR circuit has hysteresis and a deglitch
internal thermal sense circuit turns off the power FET and
feature so that it will typically ignore undershoot transients
allows the device to cool down. When the device’s
on the input. When input voltage exceeds the POR
junction temperature cools by 40°C., the internal thermal
threshold and after 8ms blanking time, the output voltage
sense circuit will enable the device, resulting in a pulsed
starts a soft-start to reduce the inrush current.
output during continuous thermal protection. Thermal
ACIN Over-Voltage Protection (OVP)
protection is designed to protect the IC in the event of
The input voltage is monitored by the internal OVP circuit.
over temperature conditions. For normal operation, the
When the input voltage rises above the input OVP
junction temperature cannot exceed TJ=+125°C..
threshold, the internal FET will be turned off within 1ms to
Internal P-MOSFET
protect connected system on OUT pin. When the input
The iD6309 integrates a P-channel MOSFET with the
voltage returns below the input OVP threshold minus the
body diode reverse protection to replace the external
hysteresis, the FET is turned on again after 8ms recovery
PMOSFET and Schottky diode for cell phone’s PMIC. The
time. The input OVP circuit has a 300mV hysteresis and a
body diode reverse protection prevents a reverse current
recovery time of TON(OVP) to provide noise immunity
flowing from the battery back to CHRIN pin. During
against transient conditions.
power-on, when CHRIN voltage rises above the VBAT
Over-Current Protection (OCP)
voltage by more than 150mV, the body diode of the P-
The output current is monitored by the internal OCP
channel MOSFET is forward biased from OUT to CHRIN,
circuit.
and PMOSFET is controlled by the external GATDRV
When the output current reaches the OCP
threshold, the device limits the output current at OCP
voltage.
threshold level. If the OCP condition continues for a
When the CHRIN voltage drops below VBAT +20mV, the
blanking time of TB(OCP), the internal power FET is turned
body diode of the P-channel MOSFET is forward biased
off. After the recovery time of TON(OCP), the FET will be
from CHRIN to OUT and P-channel MOSFET is turned off.
turned on again. The iD6309 has a built-in counter. When
When any of input OVP, OCP, battery OVP, is detected,
the total count of OCP fault reaches 16, the FET is turned
the internal P-channel MOSFET is also turned off.
off permanently, requiring a VACIN POR again to restart.
Thermal Considerations
Battery Over-Voltage Protection
For continuous operation, do not exceed the maximum
The iD6309 monitors the VBAT pin voltage for battery
operation junction temperature 125°C. The maximum
over-voltage protection. The battery OVP threshold is
power dissipation depends on the thermal resistance of IC
internally set to 4.35V. When the VBAT pin voltage
package, PCB layout, the rate of surroundings airflow and
exceeds the battery OVP threshold for a blanking time of
temperature difference between junctions to ambient. The
TB(BOVP), the internal power FET is turned off. When the
maximum power dissipation can be calculated by
VBAT voltage returns below the battery OVP threshold
following formula:
minus the hysteresis, the FET is turned on again. The
PD (MAX ) =
iD6309 has a built-in counter. When the total count of
Apr. 2011
8
(T (
J MAX )
− TA )
θ JA
Rev 0.7
iD6309
Where
TJ(MAX)
junction
the Figure 1 of de-rating curves allows the designer to see
temperature 125°C, TA is the ambient temperature and
the effect of rising ambient temperature on the maximum
the θJA is the junction to ambient thermal resistance. For
power allowed.
recommended
iD6309
where
is
the
operating
TJ(MAX)
maximum
operation
conditions
is
the
specification
maximum
of
Maximum Power Dissipation
junction
1.50
temperature of the die (125°C) and TA is the maximum
1.25
Power Dissipation (W)
ambient temperature. The junction to ambient thermal
resistance θJA is layout dependent. For TDFN-8L
packages, the thermal resistance θJA is 80°C/W on the
standard JEDEC 51-7 four-layers thermal test board. The
maximum power dissipation at TA = 25°C can be
calculated by following formula:
1.00
0.75
0.50
0.25
PD(MAX) = (125°C − 25°C) / (80°C/W) = 1.25W
0.00
0
for TDFN-8L packages. The maximum power dissipation
25
50
75
100
125
Ambient Temperature (°C)
depends on operating ambient temperature for fixed
Figure 1: Maximum Power Dissipation
TJ(MAX) and thermal resistance θJA. For iD6309 packages,
Layout Considerations
In some failure modes, a high voltage may be applied to the device. Make sure the clearance constraint of the PCB
layout must satisfy the design rule for high voltage. The exposed pad of the TDFN2x2-8 performs the function of
channeling heat away. It is recommended that connect the exposed pad to a large copper ground plane on the backside
of the circuit board through several thermal vias to improve heat dissipation. The input and output capacitors should be
placed close to the IC. The high current traces like input trace and output trace must be wide and short.
The ACIN capacitors
should be close to the IC.
ACIN trace must be
wide and short.
Battery
0.2Ω
ACIN 1
ACIN 2
CACIN
+
8
OUT
7
OUT
6
CHRIN
OUT trace must
be wide and short.
EP
GND 3
CCHRIN
VBAT 4
5 GATDRV
The CHRIN capacitors
should be close to the IC.
RBAT
Exposed thermal pad must be electrically connected to GND pin. It's recommended
that connect the exposed pad to a large copper ground plane on the backside of the
circuit board through several thermal vias to improve heat dissipation.
Apr. 2011
9
Rev 0.7
iD6309
Figure 1. OVP Timing Diagram
Figure 2. OCP Timing Diagram
Apr. 2011
10
Rev 0.7
iD6309
Figure 3. Battery OVP Timing Diagram
Apr. 2011
11
Rev 0.7
iD6309
Packaging
TDFN-8L(2X2)
SYMBOLS
A
A1
A3
b
D
D1
E
E1
e
L
Apr. 2011
DIMENSIONS IN MILLIMETERS
MIN
0.70
0.00
--0.15
1.95
--1.95
----0.30
NOM
0.75
0.01
0.20 REF
0.20
2.00
1.6BSC
2.00
0.9BSC
0.50BSC
0.35
MAX
0.80
0.03
--0.25
2.03
--2.03
----0.40
12
DIMENSIONS IN INCH
MIN
0.0276
0.000
--0.006
0.077
--0.077
----0.012
NOM
0.0295
0.0004
0.0078REF
0.0079
0.079
0.063BSC
0.079
0.035BSC
0.02BSC
0.0138
MAX
0.0315
0.0012
--0.0098
0.080
--0.080
----0.016
Rev 0.7
iD6309
Footprint
TDFN-8L(2X2)
Package
Number of PIN
TDFN-8L 2x2
8
Apr. 2011
Footprint Dimension (mm)
P
A
B
C
D
Sx
Sy
M
050
2.80
1.20
0.80
0.30
1.30
0.70
1.80
13
Tolerance
±0.030
Rev 0.7