Master the latest MIPI and (LP)DDR4 Test Challenges
Jacky Yu
Application Enginner
掌握行動運算及記憶體科技，克服MIPI與(LP)DDR4測試挑戰
Jan 12-13, 2016
MIPI Physical and Protocol Layer Testing
Agenda
MIPI Overview and Standards Update
• MIPI PHY Roadmap
• Other developments
UFSA Compliance Program Overview
Measurement Applications and Solutions Update and Roadmap
• TX Testing
• RX Testing
• Protocol Testing
Page 2
MIPI = Mobile Industry Processor Interface Goals
– Structure the intestines of mobile
devices ranging from smartphones
to wireless-enabled tablets and
netbooks
– Benefit the entire mobile industry by
establishing standards for hardware
and software interfaces
– Enabling reuse and compatibility
making system integration less
burdensome
– The distinctive requirements of
mobile terminals drive the
development of MIPI Specifications
• Power saving / battery life
• Bandwidth on demand
MIPI M-PHY Receiver Test Webinar
Page 3August 2013
MIPI’s Layered Approach for Application Standards
Page 4
Page 4
MIPI – Mobile Influenced
Automotive
– “Smart Car”
• Advanced Driver Assistance
Systems (ADAS)
• Cameras (MIPI CSI) / Displays
(MIPI DSI)
• In-Vehicle Infotainment (IVI)
• Sensors (MIPI I3C)
Page 5
Agenda
MIPI Overview and Standards Update
• MIPI PHY Roadmap
• Other developments
UFSA Compliance Program Overview
Measurement Applications and Solutions Update and Roadmap
• TX Testing
• RX Testing
• Protocol Testing
Page 6
Key Features of PHY-Layer Standards
Vers. Max HS Symbol
Rate (GSym/s)
D-PHY
C-PHY
M-PHY
1.0, 1.1
1.5, continous
1.2
2.5, continous
2.0
4.5, continous
1.0
2.5, continous
1.1
3.0, continuous
1.0, 2.0
1.5/2.9 discrete
3.0
5.8, discrete
4.0
11.6, discrete
Data format
LP
nondiff.
“RZ“
(type II:
NRZ)
Clock
Recovery
Forward Source
Synchronous
(DDR)
NA
HS
diff.
NRZ,
3-phase
3-level
diff.
type I:
PWM
Clocking
embedded
RX de-skew
Logical
EQ
None
None
TX
None
TX
None
diff.
NRZ
embedded
PLL-based
TX
TX & RX
Page 7
MIPI M-PHY Spec Roadmap
– V4.0 adopted August 2015
– V4.1 Spec goals
• Tighten spec/conformance of digital interface (RMMI)
• Protocol/PHY optimizations
• No activity in subgroup after lead from Intel has been assigned to other
tasks.
– Items in discussion for next Gen M-PHY:
•
•
•
•
•
Advanced encoding and scrambling
Optional data rate granularity
Short channel reach applications (<20dB loss channel)
Change jitter BER from 1e-10 to 1e-12
Power efficiency optimations
Page 8
M-PHY Link Example
LINK
SUB-LINK
MIPI M-PHY
M-PORT
LANE
PINs
TXDP
M-TX PIF
LINE
RXDP
M-TX
TXDN
M-RX
M-RX PIF
M-RX
M-RX PIF
M-TX
M-TX PIF
RXDN
PINs
TXDP
M-TX PIF
LINE
RXDP
M-TX
TXDN
RXDN
PINs
RXDP
M-RX PIF
LINE
PINs
TXDP
M-RX
RXDN
LANE MANAGEMENT
LANE MANAGEMENT
PINs
•
•
•
•
Lanes are unidirectional
Signaling: differential
8B/10B coded
Transmisssion may
appear in burst
• Embedded clock
• PLL type CDR, needs to
synch at the beginning
of every burst
TXDN
PINs
LANE
M-PORT
SUB-LINK
LINK
MIPI M-PHY options
– High speed and (lower speed) low power mode (same as in D-PHY)
– High and low voltage swing operation can be commonly selected for both modes
– Terminated (100 Ohm) or not terminated operation (for power saving purposes) can
individually be selected per mode
9
Page 9
Low Power Modes
High Speed Modes
MIPI M-PHY Data Rates and Module Types
fref = 19.2, 26, 38.4 or 52 MHz
NT = Not Terminated
RT = Resistively terminated
• High Speed Gears / data rates valid for both module types
• Type II module only used for Dig_RF_v4
1010
10
Page 10
Type-I RX State Machine
DIF-P for 9 to 20 UIHS + TPWM_PREPARE. Ready for LINE-CFG within that period (with respect to maximum allowed data rate in configured PWM-GEAR)
HS-MODE
All transitions initiated
by TX signalling
and commands
DIF-N
– Hibern8: “deepest” power saving
state
DIF-N to DIF-P
Transition
STALL
HS-BURST
RCT
DIF-N for 9 to 20 UIHS
RCT
• Transition into “Sleep”or
“Stall” signaled by driving a
DIF-N (= logical “0”) No direct
transition to data transfer
9 PWM-b1
DIF-P to DIF-N
Transition at
Completion of
MODE-LCC
RCT
DIF-Z
to DIF-N
Transition
LINE-CFG
DIF-N
DIF-N to DIF-P
Transition
SLEEP
PWM-BURST
(> 9 PWM-b0) + PWM-b1
RCT
LS-MODE
Update of INLINE configuration
settings during SLEEP or STALL
after Re-Configuration Trigger (RCT)
= State
= State with sub-FSM
HIBERN8
DIF-P to DIF-N
Transition
DIF-Z
= Global State
= Power Saving (SAVE) State
= LS-MODE State (PWM)
A
LINE-RESET
= Special State
UNPOWERED
11
DIF-P
RESET
Power
Supply
Off
DIF-P for TLINE-RESET-DETECT
POWERED
• transition into low power
PWM burst mode signaled by
DIF-P
(= logical “1”)
– “Stall: line is driven DIF-N
= NRZ-LINE Condition
= PWM-LINE Condition
Power
Supply
On
– “Sleep”: line is driven DIF-N
= HS-MODE State
RESET
Completion
DISABLED
• data line kept open and no
signal is driven (DIF-Z)
= CONFIG Condition
= Extra CONFIG Option
(without MC)
• transition into high speed
NRZ burst mode signaled by
DIF-P
ACTIVATED
1110
MIPI M-PHY Receiver Test Webinar
Page 11
August 2013
ADAPT State
SAVE state:
STALL or SLEEP
LINE state: DIF-N;
Unconstrained length
PREPARE
LINE state: DIF-P;
Function: request for BURST
SYNC
Any 8b10b data symbols with
7/10 edge density. Optional for
PWM-G6 and PWM-G7.
Function: clock/bit
synchronization
Duration: 0 to 15 SI or 24+P SI
By default extended until MK0
First MARKER0 for
symbol synchronization,
RD initialization,
and start of PAYLOAD
PAYLOAD symbols:
DATA & MK0, MKn;
FLR for Idling if no
TX data available
TAIL-OF-BURST
Function: Run length
violation indicating a
change of state
ADAPT
Function: HS-RX equalizer
adaptation and clock/bit
synchronization
Duration: 650*(n+1) or 650*2n bits
HS-BURST
ADAPT
STALL
PREPARE
DIF-N
DIF-P
SYNC
MK0
FLR
8b10b Encoded
DATA
TAIL-OF-BURST
MK0
PWM/SYS-BURST
SLEEP
PREPARE
DIF-N
DIF-P
MKn
xxx
= SAVE State
xxx
= 8b10b Encoded Symbol
= BURST (sub-)State
xxx
= Symbol for M-RX
= Optional State Transition
xxx
= Symbol for M-RX
= Symbol for M-RX
xxx
= Symbol for Protocol
Page 12
MIPI D-PHY Spec Roadmap
D-PHY 2.0 (2015)
– High Frequency Clock(DDR) forwarded architecture targeted at max data rate of
4.5Gbps.
– Spread Spectrum Clocking (SSC) support on clock to mitigate emissions
concerning EMI compliance.
– Scrambling support at the controller level to reduce data interference with the
radio frequencies.
– Channel Support: 14inch(@4.5Gbps), 21inch(@2.5Gbps)
– Eye Diagram Conformance for Tx/Rx. Jitter decomposition into DJ/RJ
– Support 4K Display with Chip on Glass implementation.
– Test Mode. Informative chapter.
D-PHY 2.1
– In discussion: Alternate LP mode
Page 13
D-PHY Universal Lane Module Functions
– Lane consisting of 2 wires, Dp and Dn
– TXs and Rxs: Bidirectional
PPI
– Contention Detection (LP only)
LP-TX
(appendix)
– Two set‘s of TXs / RXs (HS & LP)
TX
HS-TX
Clock
Data
Lane
Control
and
Interface
Logic
Dp
Dn
HS-RX
RT
R
RX
LP-RX
Ctrl
LP-CD
CD
Protocol Side
– HS-mode:
• Small Amplitude, terminated
(option)
• Data format: NRZ
• Signaling: differential
– LP-mode:
• Large Amplitude, unterminated
• Data format: RZ
• Signaling: non-differential
Line Side
Page 14
D-PHY Two Data Lane Phy Configuration
Clock
Multiplier
Unit
Ref Clock
Controls
I
APPI = Abstracted PHY-Protocol Interface (complete PHY, all Lanes)
PPI = PHY Protocol Interface (per Lane, some signals can be shared with multiple Lanes)
Q
PPI
APPI
PHY
Adapter
Layer
PPI
PPI
D-PHY
Master Clock Lane Module
D-PHY
Slave Clock Lane Module
PPI
D-PHY
Master Data Lane Module
D-PHY
Slave Data Lane Module
PPI
D-PHY
D-PHY
PPI
Master Data Lane Module
Slave Data Lane Module
PHY
PHY
Master Side
Slave Side
APPI
PHY
Adapter
Layer
– Source synchronous forwarded double data rate clocking
– Data-rate completely agile, no discrete operating frequencies, continous range
– RX testing is basically stressing set-up- and hold- time conditions
(eye closure mainly due to DDJ and skew between Data and Clock)
15
Page 15
D-PHY Physical Layer Timing Diagram
Transition LP to HS mode, HS_clk active earlier / longer
High speed mode,
Differential signaling, 100 ohm termination, source synchronous DDR clocking
Low power mode
Unterminated, not differential, clock embedded within data
Page 16
MIPI C-PHY Spec Roadmap
C-PHY 1.0 (adopted October 2014)
– 2.5Gsps
– Effective data rate up to 5.7Gbps
C-PHY 1.1 in adoption
– Up to 3Gsps
– TX Deemphasis
Page 17
C-PHY Universal Lane Module Functions
PPI
(appendix)
Data In
Data Out
TX Ctrl Logic
Data
IF
logic
– TXs and RXs: Bidirectional
LP-TX
– Contention Detection (LP only)
A
B
C
Esc Encoder
TX
Mapper
HS-Serialize
Encoder
HS-TX
Sequences
Clocks-in
DeMapper
Clocks-out
HSDeserialize
Decoder
Data
Sampler
HS-RX
RT
RX
LP-RX
Data Out
Protocol
Side
Ctrl Decoder
Ctrl
IF
logic
State Machine
(incl Enables, Selects
and System ctrl)
– HS-mode:
• Small Amplitude, always 50
W “star-type“ termination
• Data format: 3-phase / 3-level
• Signaling: 3 wires forming a
HS-lane
– LP-mode:
• Large Amplitude, unterminated
• Data format: RZ
• Signaling non-differential
Esc Decoder
Data In
– Two set‘s of TXs / RXs (HS & LP)
LP-CD
Error detect
CD
Line Side
Page 18
3 Phase Encoding Concept for C-PHY (HS-mode)
– A data encoding technique utilyzing
trios rather than pairs of wires
• 50 Ohm “star-type“ termination
• Utilyzes differential receivers,
rejecting common mode noise
• Drivers work similar to D-PHY but
control 3 instead of 2 outputs
– Both clock and data are encoded
and transported together in a single
trio
• Always a transition at every
symbol boundary, which simplifies
clock recovery and allows data
rate to be completely agile
19
Master side
+V
PU_A
“B” to “A” (-x state)
“A”
Z0=50
+
50
+V
PD_A
PU_B
-V/2
Rx_AB
“0”
Rx_BC
“1”
Rx_CA
“1”
50
“B”
Z0=50
ZID/2=50
+
PD_B
+V/4
+V
PU_TC
Slave side
ZID/2=50
100
100
“C”
Z0=50
ZID/2=50
+
+V/4
-
A
B
C
Page 19
3-phase Signal Example
HS signal only
A
B
C
A B C
•
Clean HS signal no jitter no skew
•
separated (offset-shifted, left) and overlaid (same offset, right)
note: for each UI each voltage level appears exactly once!
Page 20
C-PHY Block diagram
Positive Polarity States
“A” to “B” (+x state)
+V
PU_A
“A”
50
Z0=50
+V/2
+V
+V
PU_A
+
Rx_AB
“1”
“B”
Z0=50
-V/4
Rx_BC
“C”
Z0=50
100
PD_TC
50
-V/4
Rx_CA
“B”
+V/4
“C”
100
Z0=50
+V
PU_TA
100
PD_TA
100
+V
PU_B
“B” to “C” (+y state)
“A”
Z0=50
+
100
“0”
+V/4
+
“0”
PU_TA
100
PD_TA
100
+V
50
“B”
+V/2
+V
Rx_BC
“1”
“C”
Z0=50
+
50
-V/4
+
+V/4
Rx_CA
“B”
Z0=50
+V
PU_A
“C” to “A” (+z state)
“A”
Z0=50
+
-V/2
+
“C”
50
Z0=50
100 “B”
PD_TB
100
Z0=50
PU_C
+
-V/4
+V
Rx_AB
Rx_BC
50
“C”
Z0=50
“0”
-
Rx_CA
“A”
50
Z0=50
Rx_CA
“1”
“1”
+V/4
+V
Rx_AB
“1”
Rx_BC
“1”
Rx_CA
“0”
-
PU_TB
100 “B”
PD_TB
100
Z0=50
ZID/2=50
+
+V/4
+V
PD_C
Slave side
ZID/2=50
PD_A
-
PU_C
ZID/2=50
+V/2
“A” to “C” (-z state)
+
“0”
+
PD_C
Master side
Slave side
ZID/2=50
+V
“0”
ZID/2=50
+V/4
-
PU_TB
Rx_BC
-
PD_C
PU_A
-V/4
“1”
-
ZID/2=50
50
+V
PD_A
Rx_AB
ZID/2=50
+
“0”
Slave side
-
-
Master side
“1”
ZID/2=50
+V
PU_C
ZID/2=50
Z0=50
50
PD_B
-
PU_C
“A”
PU_B
+
PD_C
PD_TC
Rx_AB
+V
ZID/2=50
PD_B
“C” to “B” (-y state)
Master side
Slave side
Z0=50
Rx_CA
-
ZID/2=50
-V/4
“1”
ZID/2=50
-
Master side
Rx_BC
-
PU_TC
+
“0”
+
ZID/2=50
Rx_AB
ZID/2=50
+V
100
-V/2
Z0=50
PD_B
“0”
Slave side
ZID/2=50
+
PU_B
+
50
Z0=50
50
+V
PD_A
ZID/2=50
+V
PU_TC
“A”
-
PU_B
PD_B
Slave side
ZID/2=50
PD_A
Negative Polarity States
“B” to “A” (-x state)
Master side
Master side
“C”
50
Z0=50
ZID/2=50
+
-V/2
-
– Coding rules and possible
wire states:
• 27 possible wires states
• 6 allowed wire states
(+x, -x, +y, -y, +z, -z)
only those states with
different voltage on each
wire
• From one symbol to the
next symbol only 5 wire
states are possible,
because a transition is
required for CR
• Theoretical coding gain:
log2(5) = 2.32
• Practically usable gain is
2.28 by sending 16 bits in
7 symbols
Drawing showing T2 Driver type w/ active mid-level
21
Page 21
C-PHY Block diagram
Positive Polarity States
“A” to “B” (+x state)
+V
PU_A
“A”
50
Z0=50
+V/2
+V
+V
PU_A
+
Rx_AB
“1”
“B”
Z0=50
-V/4
Rx_BC
“C”
Z0=50
PU_A
100
PD_TC
-V/4
Rx_CA
+V
PU_TA
100
PD_TA
100
+V
PU_B
“B” to “C” (+y state)
“A”
Z0=50
“C”
100
Z0=50
+
-V/4
50
“B”
Z0=50
100
PD_TA
100
+V
+
+V/2
+V
Rx_BC
“C”
Z0=50
+
50
-V/4
Rx_CA
“0”
+V
PU_A
“C” to “A” (+z state)
“A”
Z0=50
“C”
50
PD_C
-V/4
100 “B”
PD_TB
100
Z0=50
+
-V/4
Rx_BC
“0”
50
“C”
Z0=50
+
+V/2
-
Rx_CA
“1”
Z0=50
+
Rx_AB
-V/4
“1”
-V/2
“C”
Rx_BC
“0”
Rx_CA
“1”
Z0=50
-
+
+V/4
PD_TB
100
Z0=50
Rx_AB
“1”
+
Rx_BC
“1”
Rx_CA
“0”
-
50
Rx_CA
“0”
Slave side
ZID/2=50
+V/4
Z0=50
-V/4
ZID/2=50
+V
“C”
“0”
-
100 “B”
Rx_BC
ZID/2=50
+
-
Z0=50
“1”
ZID/2=50
ZID/2=50
100
Rx_AB
+
Z0=50
+V/2
“1”
ZID/2=50
+V/4
PU_TB
PD_C
ZID/2=50
-
+V
PU_C
ZID/2=50
Slave side
-
50+V/4 +
PD_A
-
Z0=50
-
+
“0”
ZID/2=50
+V
PD_C
Rx_AB
Rx_CA
+V/4
“A” to “C” (-z state)
“A”
50
-
PU_TB
PU_C
PU_A
+
50
+V
PD_A
+V
Slave side
“1”
ZID/2=50
100
PD_TC
Master side
ZID/2=50
+V
Z0=50
PU_TC
-
Master side
Z0=50
50
+V
PU_C
ZID/2=50
Rx_BC
+
+
PD_B
“B”
PD_B
“1”
-
PU_C
“A”
PU_B
ZID/2=50
+
Slave side
+V
PU_TA
-
PD_B
PD_C
PD_TC
“0”
“A”
+V/4
“C”PU_B
to “B” (-y state)
“B”
Master side
Rx_AB
“0”
ZID/2=50
+V
Slave side
Rx_AB
ZID/2=50
PD_A
100
“0”
ZID/2=50
“A” to “B” (+x state)
-
50
-
Master side
+
-V/2
Slave side
-
PU_TC
ZID/2=50
+
“B”
+V
100
50
Z0=50
PD_B
“0”
ZID/2=50
+V
PU_B
+
50
Z0=50
Master side
50
+V
PD_A
ZID/2=50
+V
PU_TC
“A”
-
PU_B
PD_B
Slave side
ZID/2=50
PD_A
Negative Polarity States
“B” to “A” (-x state)
Master side
Master side
ZID/2=50
+
-V/2
-
midpoint voltage is stable
at +V/2
(except for asymmetries
during transitions (to be
filtered by capacitor))
Drawing showing T2 Driver type w/ active mid-level
22
Page 22
C-PHY Block diagram
Positive Polarity States
“A” to “B” (+x state)
+V
“A”
50
Z0=50
+V/2
+V
+V
PU_A
+
Rx_AB
“1”
“B”
Z0=50
-V/4
Rx_BC
“C”
Z0=50
PU_A
100
PD_TC
-V/4
Rx_CA
+V
PU_TA
100
PD_TA
100
+V
PU_B
“B” to “C” (+y state)
“A”
Z0=50
“C”
100
Z0=50
+
-V/4
50
“B”
Z0=50
100
PD_TA
100
+V
+
+V/2
+V
Rx_BC
“C”
Z0=50
+
50
-V/4
Rx_CA
“0”
+V
PU_A
“C” to “A” (+z state)
“A”
Z0=50
“C”
50
PD_C
PU_TB
-V/4
Z0=50
100
-V/4
50
“C”
Z0=50
“0”
+V/2
-
Rx_CA
Z0=50
“1”
Rx_BC
“0”
-V/2
“C”
Rx_BC
“0”
Rx_CA
“1”
Z0=50
-
Rx_CA
“0”
ZID/2=50
+
+V/4
+
-V/4
-
Slave side
ZID/2=50
Rx_AB
“1”
ZID/2=50
+
+V/4
+V
PD_C
-V/4
“1”
Z0=50
“1”
ZID/2=50
+
Rx_AB
-
100
PD_TB
Z0=50
ZID/2=50
100
Rx_AB
+
Z0=50
+V/2
“1”
ZID/2=50
+V/4
100 “B”
Rx_BC
“1”
Rx_CA
“0”
100W
-
PU_C
ZID/2=50
+
PD_C
Rx_BC
ZID/2=50
-
+V
-
Slave side
-
50+V/4 +
PD_A
PU_TB
+
Z0=50
-
+
“0”
ZID/2=50
+V
PU_C
Rx_AB
Rx_CA
+V/4
“A” to “C” (-z state)
“A”
50
100 “B”
PD_TB
PU_A
+
50
+V
PD_A
+V
Slave side
“1”
ZID/2=50
100
PD_TC
Master side
ZID/2=50
+V
Z0=50
PU_TC
-
Master side
Z0=50
50
+V
PU_C
ZID/2=50
Rx_BC
+
+
PD_B
“B”
PD_B
“1”
-
PU_C
“A”
PU_B
ZID/2=50
+
Slave side
+V
PU_TA
-
PD_B
PD_C
PD_TC
“0”
“A”
+V/4
“C”PU_B
to “B” (-y state)
“B”
Master side
Rx_AB
“0”
ZID/2=50
+V
Slave side
Rx_AB
ZID/2=50
PD_A
100
“0”
ZID/2=50
“A” to “B” (+x state)
-
50
-
Master side
+
-V/2
Slave side
-
PU_TC
ZID/2=50
+
“B”
+V
100
50
Z0=50
PD_B
“0”
ZID/2=50
+V
PU_B
+
50
Z0=50
Master side
50
+V
PD_A
ZID/2=50
+V
PU_TC
“A”
-
PU_B
PD_B
Slave side
ZID/2=50
PD_A
Negative Polarity States
“B” to “A” (-x state)
Master side
Master side
PU_A
50W
“C”
50
Z0=50
ZID/2=50
+
-V/2
-
Drawing showing T2 Driver type w/ active mid-level
23
Page 23
C-PHY Block diagram
Positive Polarity States
“A” to “B” (+x state)
+V
“A”
50
Z0=50
+V/2
+V
+V
Rx_AB
“1”
“B”
Z0=50
PU_B
+
50
-V/4
Rx_BC
“C”
100
Z0=50
+
-V/4
Rx_CA
+V
PU_TA
100
PD_TA
100
+V
PU_B
“B” to “C” (+y state)
“A”
Z0=50
+
-V/4
50
“B”
100
PD_TA
100
+V
+
Rx_BC
“C”
Z0=50
+
50
-V/4
Rx_CA
+V
PU_A
“C” to “A” (+z state)
“A”
Z0=50
50
+V
PD_A
PU_TB
Z0=50
100
PD_TB
PU_C
Rx_BC
“0”
50
“C”
Z0=50
+V/2
-
Rx_CA
“1”
“1”
Z0=50
+V
ZID/2=50
+
+
ZID/2=50
50
+
+V/2
Rx_BC
Rx_BC
“1”
“C”
Rx_CA
“0”
“0”
+V/4
Rx_CA
Z0=50
ZID/2=50
+
“1”
-
-V/4
-
Slave side
ZID/2=50
Rx_AB
“1”
Z0=50
“0”
ZID/2=50
“1”
-
Z0=50
Rx_AB
-
ZID/2=50
-V/2
Z0=50
-V/4
-
+V/4
100 “B”
ZID/2=50
+
100
PD_TB
Rx_AB
+V/4
+V
+V/4
+V
PD_C
Slave side
ZID/2=50
“A” to “C” (-z state)
“A”
50
Rx_BC
“1”
Rx_CA
“0”
50W
-
PU_C
ZID/2=50
Rx_BC
ZID/2=50
PD_A
+
PD_C
+V
PU_TB
-V/4
+V
+
+
“0”
ZID/2=50
+
“C”
Master side
100 “B”
Z0=50
PD_C
Slave side
Rx_AB
“A”
+V/4
+
50
PU_A
-V/4
Z0=50
PD_C
ZID/2=50
+
Z0=50
50
-
Master side
100
+
“0”
“0”
ZID/2=50
PU_C
+V
PU_C
ZID/2=50
Rx_AB
-
PD_B
“B”
PD_B
“1”
-
PU_C
“A”
PU_B
+V/2
+V
PD_C
PD_TC
+V
PU_TA
ZID/2=50
PD_B
“B” to “C” (+y state)
+
100
Rx_CA
+V/4
“1”
+V
“C”
to “B” (-y state)
PU_B
50 “B”Slave side Z0=50
Master side
“0”
+
-V/2
Slave side
PD_TA
Z0=50
“C”
100
100
Slave side
Rx_AB
Z0=50
ZID/2=50
-
“0”
ZID/2=50
+V
PU_TA
-
Master side
“B”
Z0=50
+V
PU_TC
ZID/2=50
100
50
PD_B
“0”
-
PD_TC
50
+V
PD_A
ZID/2=50
+V
PU_TC
“A”
-
PU_B
Master side
PU_A
+
PD_B
Slave side
ZID/2=50
PD_A
Negative Polarity States
“B” to “A” (-x state)
Master side
Master side
PU_A
100W
“C”
50
Z0=50
ZID/2=50
+
-V/2
-
Drawing showing T2 Driver type w/ active mid-level
24
Page 24
Layers: Words, Symbols, Wire States
– Mapper converts 16-bit word into 7 symbols (21 bits), 16/7  2.285 bits/symbol
– In a group of 7 UI’s, total of 57=78,125 permutations
• To send 16-bit word requires only 216 = 65,536 states
– Parallel-to-Serial sends each symbol to the Encoder one at a time.
– Encoder creates present wire state based on previous wire state and the 3-bit Symbol
• Each 3-bit symbol has a Flip, Rotation and Polarity.
– Wire state in each UI has 1 of 6 values, next state can be one of the 5 other values.
• Requiring a transition is how the clock is encoded in each symbol.
21 = 7 symbols,
3 bits each.
3 bits define one
of 5 state transitions
Page 25
t0
t1
t2
t3
t4
t5
t6
ws0 ws1 ws2 ws3 ws4 ws5 ws6
A
B
C
3-Wire
Receiver,
(3)
Symbol
Decoder
Each Wire State has
6 possible states.
Tx_Flip,
Tx_Rotation,
Tx_Polarity
The change on ABC from one Unit Interval
to the next defines the symbol value.
Symboln = f(wsn, wsn-1)
7-symbol
to 16-bit
(21)
(16)
DeMapper
Rx_Flip,
Rx_Rotation,
Rx_Polarity
Page 25
Rx_Data[15:0]
A
B
C
16-bit word, output
Symbol
Encoder,
(3)
3-Wire
Driver
Receive 7 symbols, output 16 bits
Seven 3-phase-encoded wire
states for each 16-bit word
Serial-to-Parallel
16-bit to
(16) 7-symbol (21)
Mapper
Parallel-to-Serial
16-bit word, input
Tx_Data[15:0]
Take in 16 bits, generate 7 symbols
Flip, Rotate, Polarity, SN = f(wsN, wsN-1)
-y
W
011
100
00
0
01
0
10
0
B to A
+z
C to A
0
10
-x
010
000
011
001
011
001
010
000
Negative Polarity
Page 26
001 1
01
+x
A to B
Positive
Polarity
000
010
001
B to C
000
010
+y
001
011
00
1
011
00
0
01
0
CC
CW
C to B
-z
A to C
Symbol decoding:
Symbol value is a function
of the change between
the previous and present
Wire State.
Page 26
Document Status and Outlook
D-PHY
C-PHY
M-PHY
Vers.
Max HS Symbol Rate
(Gsym/s) / Gear
1.0, 1.1
1.5
1.2
2.5
2.0
4.5
1.0
2.5
1.1
3.0
1.0, 2.0
1.5/2.9 / G1, G2
3.0, 3.1
5.8, / G1, G2, G3
4.0
11.6, / G1, G2, G3, G4
Specification
Board approved
CTS
Board approved
v1.2r11, work in progress
WG voting
work in progress
Board approved
v1.0r11, work in progress
WG approved
work in progress
v1.0, board approved
Board approved
v3.0r18, work in progress
work in progress
Page 27
Agenda
MIPI Overview and Standards Update
• MIPI PHY Roadmap
• Other developments
UFSA Compliance Program Overview
Measurement Applications and Solutions Update and Roadmap
• TX Testing
• RX Testing
• Protocol Testing
Page 28
UFS Compliance Test Elements
Device Test
Test Executive
Host Test
System Interop Test
HCI Compliance Test
Executive
Interop Test
Executive
Test Driver
Operating System
UFS HCI
File System
Emulated UFS Host
UFS Device
Driver Stack
Emulated UFS
Device
UFS HCI
UFS Device
Verifies compliance with key elements of
the UFS, UniPro and M-PHY specifications.
Verifies overall system integrity and
covers elements that might be missed
by device and host tests.
Certification of instrumentation and independent 3rd party test centers
Page 29
UFS Certification Process
Plugfests &
Accredited Labs
Adopter Member
Products
Compliance
Committee
UFS
Compliance
Test Spec
Compliance
Certificate
Board of
Directors
Logo
License
UFS Test
UFS
Test Spec
Procedures
M-PHY/UniPro
Test Procedures
logo assures user that
all compliance tests passed
* JEDEC, MIPI Alliance and UFSA logos are the property of their respective organizations
Page 30
UFS Compliance Test Specification
Developed by the
Reduce test
redundancy
Compliance Committee
Test only the modes
used by UFS
Golden Hosts
Golden Devices
UFS Compliance Test Matrix
for host and device testing
Device DUTs
Host DUTs
Interoperability test
configurations
Page 31
Agenda
MIPI Overview and Standards Update
• MIPI PHY Roadmap
• Other developments
UFSA Compliance Program Overview
Measurement Applications and Solutions Update and Roadmap
• TX Testing
• RX Testing
• Protocol Testing
Page 32
Test & Measurement Applications
– Electrical Layer
• TX & RX Conformance
• Impedance & S-Parameters
• BringUp & Debug
– Protocol & Application Layer
• Protocol Conformance
• BringUp & Debug
• Device Emulation
• Performance Validation
• Interoperability
Page 33
Keysight MIPI Total Solution Coverage
Transmitter
Characterization
Receiver
Characterization
Impedance/Return
Loss Validation
Protocol Stimulus and
Analysis
DSAQ93204A Infiniium
N4903B/M8020A JBERT
E5071C ENA Option TDR
U4421A D-PHY CSI-2 / DSI
Analyzer and Exerciser
U4431A M-PHY Analyzer (UFS,
UniPro, CSI-3, SSIC, M-PCIe)
M8190 AWG
U7238B D-PHY, U7249B
M-PHY, N5467B C-PHY UDA
InfiniiMax Probes
DCA 86100D Wideband
sampling oscilloscope
81250A ParBERT
Scope Protocol Decoder
Switch matrix
N5465A InfiniiSim
N2809A PrecisionProbe
N1055A
TDR/TDT
N5990A Automated
characterization
N8802A CSI-2 / DSI
N8807A DigRF v4
N8808A UniPro
N8818A UFS
N8809A LLI
N8819A SSIC
N8820A CSI-3
N8824A RFFE
54754A
TDR/TDT
Industry’s highest analog
bandwidth, lowest noise
floor/sensitivity, jitter
measurement floor with
unique cable/probe correction
Highest precision jitter lab
source with automated
compliance software for
accurate, efficient, and
consistent measurement
Precision impedance
measurements and
S-Parameter capability
Fast upload and display,
accurate capture, intuitive
GUI and customizable
hardware. Correlate physical
and protocol layer.
Page 34
Agilent / Keysight Solutions for MIPI RX PHY-test
2016 and beyond: M8085A w/ M8195A rev. 2
M8000 family of
BER test solutions...
M-PHY
J-BERT N4903B
N5990A-165
J-BERT M8020A
N5990A-165,-365

C-PHY
AWG M8190A
M8085A-CT1,-CTA

D-PHY
ParBERT 81250
N5990A-165
2013
AWG M8195A rev. 2
M8085A-xT1,-xTA
2015
2016
Page 35
Master the latest MIPI and (LP)DDR4 Test Challenges
掌握行動運算及記憶體科技，克服MIPI與(LP)DDR4測試挑戰
Jan 12-13, 2016
DDR4/LPDDR4 Scopes
Agenda
– Roadmap update
– Introduce new LPDDR4/DDR4 debug tool
– Demo
Page 37
Roadmap Update
Work in Progress
Planned but not staffed
Investigation phase
2015
Oct
Nov
2016
Dec
Oct 16th :
LP/DDR4
debug tool with
eye diagram
Jan
Feb
Mar
Feb 3rd :
HMC
compliance
app
Mar 15th :
5.60
release
with BER
contour
capability
Nov 1st :
QuickSilver
framework
release
Mar 1st :
QuickSilver
2.0 release
Apr
May
Jun
Jul
Aug
Sep
Jun 1st :
BER contour
support in
LP/DDR4
app
Jun 1st :
Multiscope
support
Jun 1st :
LP/DDR4
app to adopt
QuickSilver
framework
3D XPoint Technology
Page 38
Why use the Debug Tool?
DDR Validation Test Flow
1. Understand
signal behavior
•
•
2. Read and
write separation
methods
3. Measurement
method
5. Debug
4. Compliance
test and
simulation
I need an easy way to
debug my DDR test
failures.
I need a fast way to get
to the root cause of the
problem.
Page 39
DDR4/LPDDR4 Debug Tool
What is it?
• Identify read and write bursts.
• Make pre and post compliance
measurement on saved traces.
• Collect statistical result with multi
burst measurement.
• Navigate to measurement and
read/write burst.
• Draw eye diagrams on saved
read/write data.
• Display multiple eye diagrams.
Page 40
Identify read/write burst
• Reports number
of read/write
bursts.
• Marks start and
end of read/write
burst.
Read burst
Write burst
Page 41
Navigation
Read and Write Bursts
•
Write
Write
Navigate to
each read
and write
burst to check
if start and
end of a burst
is identified
correctly.
Write
Page 42
Pre and Post Compliance Measurement
Statistical Result
•
•
Report timing
and electrical
measurement
results – min,
max, mean.
No auto-scaling
done on saved
traces to speed
up
measurement
time.
Page 43
Navigation
Measurement
•
•
•
•
•
Max
Specify number
of bursts to
measure.
Marks all valid
measurements
in the trace.
Report number
of measurement.
Navigate to the
measurement.
Mark min and
max
measurement
Min
Page 44
Measurement
• Mark
measurement
thresholds
Measurement threshold
• DQS at 0V
• DQ at VIH/VIL
Page 45
Eye diagram
Offline view of data eye diagram
– View read/write eye diagram
with offline waveform files from
the scope or ADS simulation
tool.
– View multiple data eye
diagrams to pin point data lane
of concern.
– View both read and write eye
diagrams at the same time.
– View before and after probe
correction with InfiniiSim data
eye diagrams.
Page 46
Eye diagram
Multiple read/write eye diagrams
After
InfiniiSim
After
InfiniiSim
Before
InfiniiSim
Before
InfiniiSim
View multiple data lane eye diagrams to pin
point small data eye for further testing.
Page 47
HMC Compliance App
HMC Compliance app plan:
 Supports all Transmitter tests listed in Hybrid Memory Cube Specification 2.0.
 A PRBS pattern is usually used to generate test sequences
• PRBS15 for Transmitter testing
• PRBS31 for Receiver testing – TBD (waiting for response from PL24)
 Supports De-embedding feature - InfiniiSim
– Assuming a 3rd harmonic requirement: 45Ghz BW Scope
Page 48
QUESTIONS
Page 49