Materials Science and Engineering B 135 (2006) 242–249
High performance germanium MOSFETs
Krishna Saraswat ∗ , Chi On Chui, Tejas Krishnamohan, Donghyun Kim,
Ammar Nayfeh, Abhijit Pethe
Department of Electrical Engineering, Stanford University, Stanford, CA 94305, USA
Abstract
Ge is a very promising material as future channel materials for nanoscale MOSFETs due to its high mobility and thus a higher source injection
velocity, which translates into higher drive current and smaller gate delay. However, for Ge to become main-stream, surface passivation and
heterogeneous integration of crystalline Ge layers on Si must be achieved. We have demonstrated growth of fully relaxed smooth single crystal
Ge layers on Si using a novel multi-step growth and hydrogen anneal process without any graded buffer SiGe layer. Surface passivation of Ge
has been achieved with its native oxynitride (GeOx Ny ) and high-permittivity (high-k) metal oxides of Al, Zr and Hf. High mobility MOSFETs
have been demonstrated in bulk Ge with high-k gate dielectrics and metal gates. However, due to their smaller bandgap and higher dielectric
constant, most high mobility materials suffer from large band-to-band tunneling (BTBT) leakage currents and worse short channel effects. We
present novel, Si and Ge based heterostructure MOSFETs, which can significantly reduce the BTBT leakage currents while retaining high channel
mobility, making them suitable for scaling into the sub-15 nm regime. Through full band Monte-Carlo, Poisson-Schrodinger and detailed BTBT
simulations we show a dramatic reduction in BTBT and excellent electrostatic control of the channel, while maintaining very high drive currents
in these highly scaled heterostructure DGFETs. Heterostructure MOSFETs with varying strained-Ge or SiGe thickness, Si cap thickness and Ge
percentage were fabricated on bulk Si and SOI substrates. The ultra-thin (∼2 nm) strained-Ge channel heterostructure MOSFETs exhibited >4×
mobility enhancements over bulk Si devices and >10× BTBT reduction over surface channel strained SiGe devices.
© 2006 Elsevier B.V. All rights reserved.
Keywords: Germanium; MOSFET; Heterostructure; Mobility; Leakage
1. Introduction
It is believed that continued scaling of the conventional silicon
(Si) CMOS will take the industry down to the 45 nm technology node. It is also well accepted that below the 45 nm node
although the conventional Si CMOS can be scaled, however,
without appreciable performance gains. There are several technical issues that make proper device scaling increasingly difficult.
The drive current is far from that required at the power-supply
voltage of the sub-45 nm nodes. Suppressing the short-channel
effect and the subthreshold leakage current requires tight control
of intricate vertical and lateral channel doping profiles involving
heavy doping, very shallow source/drain junctions and ultrathin
gate dielectrics. Some of these approaches directly conflict with
the goal of obtaining high carrier mobility, high subthreshold
slope, low series resistance, large drive current and low leakage current at low operating voltage. Therefore to continue the
∗
Corresponding author. Tel.: +1 650 725 3610; fax: +1 650 723 4659.
E-mail address: saraswat@stanford.edu (K. Saraswat).
0921-5107/$ – see front matter © 2006 Elsevier B.V. All rights reserved.
doi:10.1016/j.mseb.2006.08.014
scaling of Si CMOS in the sub-45 nm regime, innovative device
structures and new materials have to be created in order to continue the historic progress in integrated electronics.
Germanium (Ge) offers several attractive physical properties
over Si. In Ge, the lower electron transverse and light hole (and
heavy) effective masses are primarily responsible, respectively,
for the higher electron and hole drift mobility. This property
is the most advantageous over Si for deeply scaled MOSFET
applications. Historically, Ge had been one of the most important semiconductors in the past as the first MOSFET and the
integrated circuit were fabricated in Ge. However, Ge has several practical problems and as a result it gave way to Si. The
common surface Ge oxides (e.g. GeO and GeO2 etc.) are either
water soluble or volatile, they are easily rinsed off or sublime
during the fabrication process. Ge substrates are not easy to handle and not readily available. Ge also has a much smaller direct
band gap compared to Si which may gives rise to higher leakage. For Ge to become a mainstream, heterogeneous integration
of crystalline Ge layers on Si, Ge surface passivation and innovative heterostructure MOSFETs to overcome leakage must be
achieved.
K. Saraswat et al. / Materials Science and Engineering B 135 (2006) 242–249
243
Fig. 1. (a) Conduction subband edge versus position from the source to the drain of a nanoscale MOSFET under high gate and drain bias. Also shown are the thermal
injection fluxes from the source and drain. (b) Illustration of carrier backscattering in a MOSFET under high drain bias. If a carrier backscatters beyond the critical
distance l from the beginning of the channel, then it is likely to exit from the drain and unlikely to return to the source.
2. Need for high mobility channel
The saturation of bulk Si MOSFET drive current (IDsat ) upon
dimension shrinkage is limiting the prospect of future scaling. To
understand this saturation phenomenon, numerous theoretical
and experimental analyses were carried out [2–6]. First of all, the
IDsat (and transconductance) in very short-channel MOSFETs is
believed to be limited by carrier injection from the source into
the channel [2–4]. In order words, the source injection velocity
(vsrc ) saturates during scaling and that its limit is set by thermal
injection velocity [4] (vinj ) as depicted in Fig. 1 (a). Also, the
carrier density at the top of the source to channel barrier is fixed
by MOS electrostatics and the scattering in a short region near
the beginning of the channel limits the IDsat (Fig. 1(b)).
By corroborating measured velocity and mobility dependencies on deeply scaled MOSFETs, the carrier velocity was
shown to have a direct proportionality with the low-field effective inversion-layer mobility [5]. Unfortunately, mobility is not
a well-defined quantity in a nanoscale MOSFET under high
drain bias where off-equilibrium transport dominates; however
in Ref. [3], it was demonstrated that the drain current of a
nanoscale MOSFET is directly related to the near-equilibrium
mean-free-path for backscattering, which can be deduced from
measurements on a corresponding long-channel MOSFET for
which the mobility is well defined. In brief, these results suggested that mobility continues to be of crucial importance to
saturated transconductance and IDsat as channel lengths decrease
below ∼100 nm [6].
Moreover, the common performance metrics, MOSFET drive
current and logic gate delay, when expressed in terms of vinj [7],
respectively reveals a direct and indirect proportionality:
IDsat = W × Qinv × vinj and
CLOAD VDD
L × VDD
=
IDsat
(VDD − Vth ) × vinj
where W is the MOSFET channel width, Qinv is the inversion
charge density, CLOAD is the load capacitance, VDD is the supply
voltage, L is the MOSFET gate length, and Vth is the threshold
voltage. Therefore, by coupling these simple relationships with
the above theoretical and experimental analyses, one can easily
identify the advantage of incorporating an alternative MOSFET
channel material with higher carrier mobility (and vinj ) to allow
further improvements on MOSFET IDsat versus technology scaling.
3. Ge MOSFET technology
Ge offers several attractive physical properties over Si. In
Ge, the lower electron transverse and light hole (and heavy)
effective masses are primarily responsible, respectively, for the
higher electron and hole drift mobility. This property is the most
advantageous over Si for deeply scaled MOSFET applications
as previously discussed regardless of the higher Si saturation
velocity. The more symmetric electron and hole mobility in Ge
would not only reduce the real estate of p-MOSFETs, but would
permit more CMOS logic gates as well. Furthermore, its lower
melting point reflects a possibility to fabricate Ge MOSFETs
with much lower thermal budget processes. In our opinion Ge
all by itself will never be the main material to fabricate ICs.
It will have to be heterogeneously integrated with Si. In most
cases Si devices will be fabricated first and then Ge will be
integrated, e.g., Ge PMOS on Si NMOS, in a 3D configuration
or for integration of optical devices on CMOS. In such cases
thermal budget available for Ge is limited. Furthermore, most
high-k dielectrics and metal gates are not generally compatible
with high temperature processing. This makes their integration
with Ge easier than with Si.
The inferior properties of germanium oxides as compared to
SiO2 make this dielectric unsuitable for Ge MOSFET gate insulation and field isolation, which has therefore obstructed very
large-scale integration (VLSI) realization in Ge for decades.
Furthermore, for Ge to become mainstream, heterogeneous integration of crystalline Ge layers on Si must be achieved.
In this work we demonstrate heterogeneous integration of
crystalline Ge layers on Si, Ge surface passivation with high-k
dielectrics and innovative heterostructure MOSFETs to overcome BTBT leakage.
3.1. Heteroepitaxial growth of thick relaxed Ge on Si
Heteroepitaxial growth of Ge on Si is not straightforward
because of the large lattice mismatch (4%) between Ge and Si,
which limits the quality of the grown material. First, above the
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Fig. 2. Cross-sectional TEM image of a heteroepitaxial-Ge layer on Si grown
by the MHAH method.
critical thickness, the layer will have many misfit dislocations
making it unusable for any practical applications. Second, the
growth of Ge on Si results in island morphology, or the so-called
“Stranski–Krastanow” (S–K) growth. Such growth is associated
with large surface roughness, causing difficulties in process integration, such as bonding for Ge-on-insulator (GOI). This can
lead to degradation in device properties.
We have developed a novel technique to achieve high quality heteroepitaxial Ge layers on Si [8,9]. The technique involves
CVD growth of Ge on Si, followed by in situ hydrogen annealing
with subsequent growth and anneal steps and hence the name
multiple hydrogen annealing for heteroepitaxy (MHAH). Following the first Ge growth and hydrogen anneal, the Ge surface
roughness from “islanding” is reduced by 90%. An additional
CVD Ge layer is grown on the low roughness Ge layer followed by the final hydrogen annealing. From cross sectional
transmission electron microscopy (TEM), misfit dislocations are
confined to the Ge/Si interface or bend parallel to this interface,
rather than threading to the surface as expected in this 4% lattice mismatched heteroepitaxial system (Fig. 2). The resulting
Ge layer is single crystal with a very low threading dislocation
density around 107 cm−2 . AFM indicates the final layer surface
roughness is reduced to device quality, while XRD confirms the
Ge layer is fully relaxed and single crystal. The results can be
explained in terms of reduction in the Ge diffusion barrier during
hydrogen anneal, thermal stress, silicon diffusion, lattice matching, and re-crystallization. This heteroepitaxial growth technique, MHAH, can be used to fabricate Ge based MOS devices,
GOI substrates, or for the eventual integration of GaAs/Ge/Si
for optoelectronics.
3.2. Dielectrics for Ge passivation
The poor quality Ge native dielectrics for gate insulator and
field isolation have been one of the classic problems that obstruct
VLSI CMOS device realization in Ge. Efforts to use materials
like SiO2 on a thin Si cap, Ge3 N4 , GeOx Ny , etc. have been
only marginally successful. Inspired by the recent successes of
the high-k dielectrics on Si, we investigated the possibility of
applying these materials to Ge. Volatility of Ge surface oxides or
sub-oxides makes surface cleaning easier for high-k gate dielectric stack free of the performance limiting, lower-k, interfacial
GeOx layer.
Surface passivation of Ge has been achieved with its
native oxynitride (GeOx Ny ) and high-permittivity (high-k) metal
oxides of Al, Zr and Hf. Three different techniques were stud-
Fig. 3. Cross-sectional HR-TEM the optimum dielectric stack attained by (a)
W/GeON/Ge gate stack formed by rapid thermal nitridation, (b) Pt/ZrO2 /Ge
gate stack formed by direct UV ozone oxidation of Zr, (c) RTN of CHF Ge at
600 ◦ C followed by HfO2 ALD.
ied for surface passivation: (1) thermal growth of Ge oxynitride
[10] (2) oxidation in ozone of metals deposited on Ge [11,12],
and (3) atomic layer deposition (ALD) of high-k metal oxides
[12,13].
The oxynitride (Fig. 3 (a)) formation was studied by an initial
rapid thermal oxidation (RTO) in dry O2 at 500–600 ◦ C followed
by in situ RTN at 500–700 ◦ C in NH3 ambient to convert the
Ge oxides into GeOx Ny [10]. Optimum process temperature for
both RTO and RTN was found to be 600 ◦ C. The degree of
nitridation in GeOx Ny should be optimized for best results. Over-
K. Saraswat et al. / Materials Science and Engineering B 135 (2006) 242–249
Fig. 4. Gate leakage measured at VFB + 1 V vs. EOT for various dielectrics.
nitridation led to excessive carrier generations near the nitrided
GeOx Ny /Ge interface, increased interfacial charge trapping and
positive oxide fixed charge generation, which may ultimately
degrade channel mobility. This technique gave excellent C–V
characteristics and therefore was employed to passivate the Ge
surface prior to the deposition of SiO2 for field isolation.
The second technique involved UHV sputtering of ∼22–30 Å
Zr films on the Ge surface followed by in situ UV ozone oxidation at room temperature [11,12]. Ge/ZrO2 interface was found
to be free of any significant interfacial Ge oxide (Fig. 3b) with
excellent C–V characteristics with EOT in the range of 6–10 Å.
In the third technique HfO2 or ZrO2 were deposited in a
cold-wall high vacuum atomic-layer deposition (ALD) system
at 300 ◦ C, using alternating surface-saturating reactions of metal
tetrachloride and H2 O precursors [12,13]. ALD of ZrO2 films
on Ge exhibited local epitaxial growth without a distinct interfacial layer. However, C–V measurements showed significant C–V
hysteresis and frequency dispersion, possibly due to metal diffusion in Ge and surface defects. To study the effect of different
surface preparations prior to high-k ALD, gate leakage currents,
EOTs and hysteresis from the corresponding MOSCAPs were
measured. Among them cyclic rinsing between HF and H2 O
(CHF) for cleaning Ge and rapid thermal nitridation (RTN) in
NH3 gave the best results. The optimum dielectric stack (Fig. 3c)
could be attained by RTN of CHF Ge at 600 ◦ C followed by high␬ ALD. Excellent C–V curves were obtained from MOSCAPs
for all three techniques. Leakage data for a variety of dielectrics
on Ge is shown in Fig. 4. It is evident that low leakage can be
obtained with appropriate high-k dielectric.
Using ultrathin GeOx Ny , ZrO2 and HfO2 gate dielectric pchannel MOSFETs were fabricated exhibiting enhanced hole
mobility over similar Si p-MOSFETs (Fig. 5) [7,9,11]. Conventional self-aligned process requires high temperatures for dopant
activation, imposing a thermal stability requirement on the highk gate stack.
245
Fig. 5. Experimental hole mobility in bulk Ge p-MOSFETs.
20 nm regime is the exponential growth in the leakage current as
discussed earlier. Most high mobility materials like Ge also have
a significantly lower bandgap compared to Si. Due to the increasing E-fields in the channel and the smaller bandgap in these
high mobility materials, the BTBT leakage current becomes
excessive and may ultimately limit the scalability of these high
mobility materials. We require a combination of good electrostatic control, excellent transport and low BTBT leakage in
order to enhance device performance. We present novel, Si and
Ge based heterostructure MOSFETs, which can significantly
reduce the BTBT leakage currents while retaining high channel
mobility, making them suitable for scaling into the sub-15 nm
regime [14–17]. The schematic of the heterostructure MOSFET
is shown in Fig. 6. It consists of a high mobility, narrow bandgap
material sandwiched between two layers of a wider bandgap
material. The goal is to make the device conduct through the high
mobility Ge region in the center in the ON state and leak through
the larger bandgap Si region at the surface. This combines the
advantage of the transport properties of the high mobility material with the leakage immunity of the larger bandgap material.
For this heterostructure, the tradeoffs between higher mobility (smaller bandgap) channel and lower band-to-band-tunneling
(BTBT) leakage have been investigated through detailed simulations. 1D Poisson Schrodinger simulations verify that carriers
are quantum mechanically confined to a very low E-field region
in the center of the DG structure, leading to very high channel mobility. Full-band Monte Carlo simulations show a ∼50%
increase in drive currents and ∼2× increase in switching speeds
at lower capacitance compared to conventional Si DGFETs. The
3.3. Si/Ge heterostructure FET
Further improvement in the transistor performance can be
obtained by straining the channel material. One of the biggest
concerns as we continue to scale MOS devices into the sub-
Fig. 6. Schematic of MOSFET device structure incorporating Si/Ge heterostructure on bulk Si substrate.
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K. Saraswat et al. / Materials Science and Engineering B 135 (2006) 242–249
Fig. 7. TEM of islanding and defect formation in epitaxial films with high germanium concentration.
theoretical values of cut-off frequencies for these devices are in
the terahertz regime, making them also well suited for analog
applications also. The details of the results of simulations can
be found in [16].
For this structure to be viable SiGe (or pure Ge) should be
sandwiched between Si. By definition SiGe will be strained in
this configuration. However, the growth of defect-free strained
SiGe alloys with very high Ge concentrations (>0.5) is far
more challenging because the dislocation generation is preceded
by the formation of coherently strained Ge islands and consequently, the layer has a very rough surface (Fig. 7). For higher Ge
concentrations, the 3-D island formation due to stress driven surface diffusion can be mitigated by depositions done at fairly low
temperatures (<400 ◦ C) to achieve good planarity. To date, most
strained-Ge growth on Si has been done on MBE or UHVCVD
systems because of the challenges in achieving low impurity
concentrations at low temperatures in LPCVD systems.
However, as seen in Fig. 8, we have successfully demonstrated LPCVD growth of defect-free ultra-thin (∼2 nm),
strained-Ge on Si [15,17] using germane as the source gas
by optimizing growth parameters. Strained Ge was epitaxially
grown on lightly doped n-type bulk Si substrate and capped
with a thin Si layer. The cross-sectional TEM in Fig. 8 shows
the different defect-free layers. The Si cap was then oxidized
at a relatively lower temperature (800 ◦ C) to prevent relaxation
of the strained Ge film. In order to study the design space thoroughly, several splits by varying the Si capping layer thickness,
Ge percentage in channel and the strained Ge thickness were
fabricated. The resulting optimal structure obtained was an ultrathin, defect free, 2 nm fully strained Ge epi channel on relaxed
Si, with a 4 nm Si cap layer.
Fig. 6 shows the schematic of the device structure that was
fabricated [15,17] and Fig. 9 shows the band diagram of the
heterostructure MOSFET. In the heterostructure MOSFET the
large valence band offset between strained-SiGe and Si creates
a quantum well, which confines the holes in it. A combination of
Fig. 8. TEM of defect free ultra-thin strained Ge on relaxed Si.
carrier confinement and strain in Ge leads to a higher mobility
channel. Furthermore, the holes in the quantum well are kept
away from the dielectric/Si interface and hence reducing surface
scattering. This further enhances the mobility.
Fig. 10 shows the mobility of the heterostructure MOSFET as
a function of Ge layer thickness. All heterostructure MOSFETs
show improvement over bulk Si devices with best results for the
2 nm Ge device, a >3.5× mobility enhancement over surface
channel Si devices. Fig. 9 also shows BTBT leakage of these
devices. The 2 nm Ge device shows a >10× BTBT reduction
over 4 nm strained Ge and surface channel 50% strained SiGe
devices. Fig. 11 explains the reduction in BTBT leakage, which
can be attributed to (1) reduction in vertical E-field in Ge as most
Fig. 9. Band diagrams of the heterostructure MOSFET.
K. Saraswat et al. / Materials Science and Engineering B 135 (2006) 242–249
247
Fig. 12. Device structure for the heterostructure Si/strained-SiGe on SOI substrate.
Fig. 10. Experimental hole mobility and BTBT current vs. Ge channel layer
thickness (TGe ) showing 2 nm is optimum.
of the potential is dropped in Si and (2) increase in bandgap of
Ge due to quantum confinement [16]. The device can be very
easily integrated into a conventional CMOS process, making it a
promising candidate for future scaled high performance devices.
Further improvement in the device performance can be done
by incorporating the heterostructure in the double gate configuration [17]. We have demonstrated this concept by fabricating the
heterostructure on a SOI substrate. Fig. 12 shows the schematic
of the strained-SiGe on SOI device structure that was fabricated.
Highly strained SiGe (80%) was epitaxially grown on 9 nm SOI
wafers and capped with a thin (3 nm) Si layer. In order to study
the design space thoroughly, several splits by varying the TSicap ,
Ge% and the TGe were fabricated. The different design splits
are shown in Table 1. The TSicap was varied from 0 to 3 nm, the
TGe was varied from 6 to 3 nm and two types of devices with
Fig. 11. Lower E-field and quantization effects in the ultrathin Ge channel reduce
the BTBT leakage in the heterostructure FET. Maximum electric field is around
the depletion layer near the surface at the drain/gate edge in Si, while it is low
in Ge.
60% and 80% Ge fractions were fabricated. The devices were
benchmarked against bulk Si, SOI and 20% SSDOI controls.
The hole mobilities for the different devices are shown in
Fig. 13. The 3 nm, 80% strained SiGe on SOI device exhibits
a very high mobility of >4× compared to the Si controls and
>2.5× higher than the control 20% SSDOI wafer. The SSDOI
itself Exhibits 40% higher mobility compared to the Si controls,
but only at low E-field. The 60% strained-SiGe on bulk devices
also show high mobility enhancements (∼2×) even at high Ninv.
By going to thinner TSicap , the mobility in the 60% bulk devices
shows a reduction at low E-fields, due to the increasing number
of Dit . However, at higher E-fields, there is a cross over in the
mobility because the coulombic scattering sites are screened and
more carriers populate the high mobility strained-SiGe layer for
a thin TSicap . Since the 60%, 6 nm strained-SiGe layer is close
to the critical thickness, it may partially relax during thermal
processing, leading to lower mobility and defect formation in
the Ge channel.
Our results show that having a larger Eg,eff significantly
reduces the BTBT probability and the available density of states,
leading to lower leakage. A thin TGe (lower than the critical
thickness) also leads to a defect-free layer, which further reduces
the trap assisted tunneling and Generation–Recombination
(G–R) currents. The Id –Vg characteristics for the strained-SiGe
on SOI device are in Fig. 14 heterostructure Si/strained-SiGe on
Fig. 13. Experimental mobility vs. Ninv for the devices described in Table 1.
Peak mobility enhancement was 4× for the heterostructure Si/strained-SiGe on
SOI substrate.
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K. Saraswat et al. / Materials Science and Engineering B 135 (2006) 242–249
Table 1
Table showing different strained SiGe device splits fabricated on SOI, SSDOI and bulk substrates
Device
Type
Layer specification
Ge(%)
Si strain
1
2
3
4
5
6
7
SiGe on SOI
SSDOI
SOI
SiGe on bulk
SiGe on bulk
SiGe on bulk
Bulk
TSicap = 3 nm, TGe = 3 nm, TSOI = 9 nm
9 nm Strained Si
9 nm SOI
TSicap = 3 nm, TGe = 6 nm
Tsicap = 2 nm, TGe = 6 nm
Tsicap = 0 nm, TGe = 6 nm
–
80
–
–
60
60
60
–
Relaxed
20%
Relaxed
Relaxed
Relaxed
Relaxed
Relaxed
SOI substrate. The currents are significantly enhanced (∼7×)
higher compared to the bulk SOI control due to the higher mobility and reduced Vth caused by the valence band offsets. In order
to improve the device performance it is essential to understand
the different leakage mechanisms in the Strained-SiGe on SOI
device. As discussed in [17], a thicker TSicap reduces the peak
vertical E-field in the strained-SiGe (smaller Eg ) region at the
expense of a marginal increase in the E-field at the Si surface
(larger Eg ). This enables us to effectively, use TSicap as a knob
to lower the BTBT leakage. However, the effect of the lateral
field is also very important in the case of SOI or Double-Gate
FETs. Going to ultra-thin SOI decreases the vertical E-field at
the expense of a growing lateral field. The total field remains
roughly the same. Thus, the E-field vector rotates from a dominant vertical vector in thicker SOI or bulk, to a dominant lateral
vector for UT-SOI, which may lead to increased susceptibility to
tunneling leakage through the narrow Eg strained-SiGe channel.
The leakage, sub-threshold slope (SS) and electrostatic control
for the ultra-thin (3 nm) strained-SiGe on SOI device are significantly better than the bulk strained-SiGe FETs but are still
worse than the control Si FETs. This may be due to the interface
states caused by some Ge diffusion to the SiO2 interface during
thermal processing.
Fig. 14. Experimental Id –Vg characteristics of the SiGe SOI device at Vd = −1 V.
The strained SiGe on SOI PMOS exhibits lower leakage than the strained SiGe
on bulk. The device has a degraded sub-threshold slope due to the thicker oxide
(∼35 nm) and the Ge-related defects at the interface but exhibits good electrostatic control and low tunneling leakage (<0.3 nA).
3.4. Ge NMOS
We demonstrated for the first time Ge n-MOSFETs with both
HfO2 and ZrO2 and metal gates using a simple self-aligned
gate-last process [7]. However, the electron mobility in n-MOS
transistors was very low, lower than what is normally obtained
in Si n-MOS. Similar results have been reported by several other
groups. Possible reasons for low Ge n-MOS ION can be attributed
to relatively low electrically active solubility limit of n-type
impurities [18] and low electron mobility in the channel. Low
electron mobility in the channel may be caused by high density
of interface traps in the upper half of the bandgap [10,19].
3.5. Drive currents/intrinsic delay simulations
To assess the ultimate performance of Ge based MOSFETs the tradeoffs between drive current (ION ), intrinsic delay
(τ), band-to-band tunneling (BTBT) leakage and short channel
effects (SCE) have been systematically compared in futuristic high mobility channel materials, like strained-Si (0–100%),
strained-SiGe (0–100%) and relaxed-Ge [20–22]. The optimal channel materials and device structures for nanoscale pMOSFETs are analyzed through detailed BTBT (including band
structure and quantum effects), full-band Monte-Carlo, 1-D
Poisson-Schrodinger simulations and experiments on ultra-thin
(<10 nm) SOI FETs. A common terminology used in this paper
is a channel material (x, y) where, x denotes the Ge content in
the channel material and y denotes the Ge content in an imaginary relaxed (r) substrate to which the channel is strained (s).
For example (0.3,0) is a s-SiGe (with 30% Ge content) channel
strained to an underlying Si substrate. (0,0.6) is a s-Si channel
strained to a r-SiGe (60% Ge content) substrate. s-Si was varied
from (0,0) r-Si to (0,1) s-Si (100%) and the s-SiGe was varied
from (1,1) r-Ge to (1,0) s-Ge (100%). (1,0) s-Ge exhibits the
highest ION due to its dramatically reduced transport mass. Due
to the lower capacitance and worse SCE, the heterostructures
show a slightly lower drive compared to the surface channel
MOSFET. Ultimately, device performance is determined by
intrinsic gate delay (CV/I). Due to its lower capacitance and high
drive current, the optimal delay is obtained in a heterostructure
FET with TGe ∼2 nm. A plot of the switching frequency versus
the minimum standby leakage achievable is a good benchmark
to compare different device structures and channel materials. In
Fig. 15, we find the performance of (0,0.6) s-Si and (0.6,0) sSiGe p-MOSFETs are very comparable. However, as we scale
K. Saraswat et al. / Materials Science and Engineering B 135 (2006) 242–249
249
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Acknowledgements
This work was supported by MARCO, DARPA, Stanford
Center for Integrated Systems and Intel.
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