Topics
FPGA Design
EECE 277
“Nothing harder than being given your chance. At least,
that's what I hear.”
– Uncle Joe
from Great Expectations (1998)
Implementation Technology Part 2
• Administrative stuff
– Office hours cancelled today
– Laboratory Assignment #1 (due Friday, February 4)
Dr. William H. Robinson
January 26, 2005
• ASICs
• Programming technologies
http://eecs.vanderbilt.edu/courses/eece277/
• FPGA Architecture
1
Guest Lecture
2
Laboratory Assignment #1
• Quartus II Software
• Dr. Robinson will be on travel
– Any installation issues?
– Friday, January 28, 2005
• UP2 Design Laboratory Kits
– All teams are assigned
• Presentations on current FPGA research
– Jason Scott
• Laboratory Report
• Embedded System Design Tools and Xilinx FPGAs
– Great Expectations
– Philippe Adell
• Implementing a Rad-Hard digital power controller with an FPGA
• Potential Lab Session
– Tuesday?
Potential Final Project Ideas!!!
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4
1
Programmable Logic Devices (PLDs)
Taxonomy
PLDs
Logic gates
and
programmable
switches
Inputs
(logic variables)
Outputs
(logic functions)
SPLDs
PROMs
CPLDs
PLAs
PALs
GALs
etc.
• General-purpose chip for implementing logic circuitry
• Customizable “black box” with gates and switches
Fundamentals of Digital Logic: Chapter 3
Copyright  2005 McGraw-Hill
The Design Warrior’s Guide to FPGAs
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
5
Programming Technologies
Technology
Symbol
SPLDs
Antifuse
FPGAs
EPROM
SPLDs and CPLDs
E2 PROM/
FLASH
SPLDs and CPLDs
(some FPGAs)
SRAM
SRAM
Taxonomy
Predominantly
associated with ...
Fusible-link
ASICs
Gate
Arrays
Structured
ASICs
Standard
Cell
Full
Custom
Increasing complexity
FPGAs (some CPLDs)
The Design Warrior’s Guide to FPGAs
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
6
Figure 3-12
7
The Design Warrior’s Guide to FPGAs
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
8
2
Gate Array
Complete Gates
• Part of the chip is prefabricated, part of the chip is
custom fabricated to user specification
• All logic cells are identical
• Amortize cost of chip fabrication
9
Copyright  2005 McGraw-Hill
Fundamentals of Digital Logic: Chapter 3
CMOS NAND Gate
Structured Computer Organization: Chapter 3
f1
The logic function
T2
f1 = x2x3+x1x3
Vf
Vx
Vx
T3
1
T4
2
(a) Circuit
Fundamentals of Digital Logic: Chapter 3
10
Customizing a Gate Array
V DD
T1
Copyright  1999 Prentice Hall
x1
x2
in the gate array
x1 x2
T1 T2 T3 T4
f
0
1
0
1
on on off off
on off off on
off on on off
1
1
1
0
0
0
1
1
off off on on
x3
• The custom design includes the wiring
connections of the gates in the array
(b) Truth table and transistor states
Copyright  2005 McGraw-Hill
11
Fundamentals of Digital Logic: Chapter 3
Copyright  2005 McGraw-Hill
12
3
Standard Cell
FPGAs Fill the Gap
PLDs
ASICs
f2
x1
The
GAP
SPLDs
x2
x3
Gate Arrays
CPLDs
f1
Structured ASICs*
Standard Cell
Full Custom
• Library of gates designed with common pitch
• Cells are wired together through routing channels
using multiple layers of wires
Fundamentals of Digital Logic: Chapter 3
Copyright  2005 McGraw-Hill
*Not available circa early 1980s
The Design Warrior’s Guide to FPGAs
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
13
Programming Technologies
Programming Technologies for FPGAs
SRAM
Antifuse
E2PROM /
FLASH
Technology node
State-of-the-art
One or more
generations behind
One or more
generations behind
Reprogrammable
Yes
(in system)
No
Yes (in-system
or offline)
Reprogramming
speed (inc.
erasing)
Fast
----
3x slower
than SRAM
Volatile (must
be programmed
on power-up)
Yes
No
No
(but can be if required)
Requires external
configuration file
Yes
No
No
Good for
prototyping
Yes
(very good)
No
Yes
(reasonable)
Feature
• SRAM
– Can be programmed many times
– Must be programmed at power-up
• Antifuse
– Programmed once
• Flash
– Similar to SRAM but using flash memory
Table 4-1
FPGA-Based System Design: Chapter 3
Copyright  2004 Prentice Hall PTR
14
15
Instant-on
No
IP Security
(especially when using
bitstream encryption)
Yes
Yes
Very Good
Very Good
Size of
configuration cell
Large
(six transistors)
Very small
Medium-small
(two transistors)
Pow er
consumption
Medium
Low
Medium
Rad Hard
No
Yes
Not really
Acceptable
The Design Warrior’s Guide to FPGAs
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
16
4
FPGA Fabric (Architecture)
Terminology
• Configuration:
• Logic
– Bits that determine logic function + interconnect.
• CLB:
• Interconnect
– Combinational Logic Block = Logic Element (LE).
• LUT:
• I/O pins
– Lookup table = SRAM used for truth table.
• I/O block (IOB):
– I/O pin + associated logic and electronics.
Fundamentals of Digital Logic: Chapter 3
Copyright  2005 McGraw-Hill
17
FPGA-Based System Design: Chapter 3
Logic Element
Copyright  2004 Prentice Hall PTR
18
Programmable Logic Block
• Programmable
– Input connections
– Internal function
a
b
c
d
• Coarser-grained than logic gates
– Typically 4 inputs
e
• Generally includes register
4-input
LUT
y
mux
flip-flop
q
clock
• May provide specialized logic
– Adder carry chain
FPGA-Based System Design: Chapter 3
Copyright  2004 Prentice Hall PTR
19
The Design Warrior’s Guide to FPGAs
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
20
5
Example: Logic Element
Logic Synthesis
• Lookup table:
a
b
0010
memory
out
1001
a
b
0
0
0
1
1
1
• How do we break the function into logic
elements?
out
0
1
0
0
0
1
0
1
0
1
Copyright  2004 Prentice Hall PTR
FPGA-Based System Design: Chapter 3
• How do we implement an operation within a
logic element?
21
Placement
Copyright  2004 Prentice Hall PTR
22
Programmable Wiring
• Where do we put each piece of logic in the
array of logic elements?
LE
LE
LE
LE
LE
…
LE
LE
LE
LE
FPGA-Based System Design: Chapter 3
FPGA-Based System Design: Chapter 3
Copyright  2004 Prentice Hall PTR
• Organized into channels
– Many wires per channel
• Connections between wires made at
programmable interconnection points
• Must choose:
– Channels from source to destination
– Wires within the channels
23
FPGA-Based System Design: Chapter 3
Copyright  2004 Prentice Hall PTR
24
6
Programmable Interconnection Point
x1 0
0
0
x2
1
Vf
f1
Programmable wiring paths
1
VA
1
0
0
SRAM
SRAM
SRAM
(to other wires)
Figure 3.68. Pass-transistor switches in FPGAs.
Fundamentals of Digital Logic: Chapter 3
Copyright  2005 McGraw-Hill
25
Choosing a path
FPGA-Based System Design: Chapter 3
Copyright  2004 Prentice Hall PTR
26
Routing Problems
• Global routing:
– Which combination of channels?
LE
• Local routing:
– Which wire in each channel?
• Routing metrics:
– Net length
– Delay
LE
FPGA-Based System Design: Chapter 3
Copyright  2004 Prentice Hall PTR
27
FPGA-Based System Design: Chapter 3
Copyright  2004 Prentice Hall PTR
28
7
I/O Blocks
Configuration
• Fundamental selection
• Must set control bits for
– Input, output, tri-state
– LE
– Interconnect
– I/O blocks
• Additional features
– Register
– Voltage levels
– Slew rate
• Usually configured off-line
– Separate burn-in step (antifuse)
– At power-up (SRAM)
FPGA-Based System Design: Chapter 3
Copyright  2004 Prentice Hall PTR
29
Configuration vs. Programming
• FPGA configuration:
Copyright  2004 Prentice Hall PTR
30
Reconfiguration
• CPU programming:
– Bits stay at the device
they program
– A configuration bit
controls a switch or a
logic bit
FPGA-Based System Design: Chapter 3
• Some FPGAs are designed for fast
configuration
– Instructions are fetched
from a memory
– Instructions select
complex operations
– A few clock cycles, not thousands of clock cycles
• Allows hardware to be changed on-the-fly
add r1, r2
addIR
r1, r2
memory
CPU
FPGA-Based System Design: Chapter 3
Copyright  2004 Prentice Hall PTR
31
FPGA-Based System Design: Chapter 3
Copyright  2004 Prentice Hall PTR
32
8
FPGA Fabric Questions
Logic Element Questions
• How many inputs?
• Given limited area budget
– How many logic elements?
– How much interconnect?
– How many I/O blocks?
• How many functions?
– All functions of n inputs or eliminate some
combinations?
– What inputs go to what pieces of the function?
• Any specialized logic?
– Adder, etc.
• What register features?
FPGA-Based System Design: Chapter 3
Copyright  2004 Prentice Hall PTR
33
Interconnect Questions
34
• How many pins?
– Maximum number of pins determined by package
type.
• Uniform distribution of wiring?
• How should wires be segmented?
• Are pins programmed individually or in
groups?
• How rich is interconnect between channels?
• Can all pins perform all functions?
• How long is the average wire?
• How many logic families do we support?
• How much buffering do we add to wires?
Copyright  2004 Prentice Hall PTR
Copyright  2004 Prentice Hall PTR
I/O Block Questions
• How many wires in each channel?
FPGA-Based System Design: Chapter 3
FPGA-Based System Design: Chapter 3
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FPGA-Based System Design: Chapter 3
Copyright  2004 Prentice Hall PTR
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