Novel SiC Diode
Solves PFC Challenges
By Jon Mark Hancock, Applications Engineering Manager,
Infineon Technologies NA, San Jose, Calif.
A merged-structure device combining pn junction and Schottky operating modes in one diode
addresses design challenges in single-phase
boost converters while reducing component
and system costs.
W
ide-input-range power factor correction
(PFC) converters present some of the
most difficult component challenges in
ac-dc power electronics. With an operating
input-voltage range that can extend from
265 Vac down to as low as 75 Vac, the range of operating
conditions is relatively extreme—even more so considering
the current operating range and duty-cycle demands. This
places high stress on both diodes and MOSFETs. Even in a
moderate-power 600-W converter, where maximum output
power at brownout recovery is 750 W and average rectified
output current from the boost converter is about 2.5 A, the
peak input current for the ac waveform can be in the range of
16 A to 20 A. Furthermore, diode and switch ripple current
will be 25% to 40% higher, depending on design parameters
for the boost inductor.
To understand the design requirements for the boost
rectifier, we’ll analyze the operating conditions, including
current, voltage and dV/dt encountered in the popular
IL
Boost rectifier
single-phase boost converter topology. This analysis will
encompass low-line and startup conditions with marginal
soft-start functionality. Then, we will examine how a new
merged-structure device combining pn junction and Schottky operating modes in one diode meets these challenges
while reducing component and system costs compared with
earlier high-performance solutions.
The commonly used converter topology for moderatepower switched-mode power supplies (SMPS) is the singlephase boost converter (Fig. 1). When this converter is operating in continuous conduction mode (CCM) under moderate
to full load, the current in the boost inductor is continuous.
This configuration is more practical for higher power levels
because the ripple current, which must be filtered by the EMI
filter, is a much lower level than in the critical or discontinuous mode boost.
However, CCM presents other problems, because the
boost rectifier must be commutated while carrying high
forward current. The reverse recovered charge (QRR) causes
the diode to look like a short to the boost MOSFET until the
charge is cleared from the diode and voltage can rise across
the diode. This is a large source of switching loss in the CCM
PFC converter, and this loss is dependent also on the peak
operating current and diode temperature for pn diodes.
IDC
VDC OUT
Boost
inductor
Bus
cap
Load
VIN
Boost Diode Calculations
First, let’s estimate the peak input current and RMS input
current for the boost PFC stage based on the required output
power (POUT) target efficiency (η) and the RMS input voltage
( VINRMS = 85 Vac ):
D
IF
IINRMS =
, IINPK =
2POUT
(Eq. 1)
.
ηVINRMS
ηVINRMS 2
The chosen inductor value for a PFC converter is based
on the duty cycle and on time relationships for the peak of
the ac waveform at low line. The inductance is also based
Diode QRR Source of switching loss
Fig. 1. In the basic single-phase boost PFC converter, the boost rectifier’s
QRR produces significant switching losses.
Power Electronics Technology June 2006
2POUT
28
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SIC DIODE
PWM POUT PFC POUT
LP at
100 kHz
FL/NL
LP at
250 kHz
FL/NL
ID
RMS
ID peak
7.41 A
350 W
385 W
417 µH/
692 µH
167 µH/
278 µH
1.18 A
500 W
550 W
303 µH/
503 µH
122 µH/
203 µH
1.68 A 10.54 A
750 W
825 W
202 µH/
336 µH
81 µH/
135 µH
2.53 A 15.81 A
1000 W
1100 W
152 µH/
253 µH
61 µH/
102 µH
3.37 A 21.07 A
LP =
With current design practices for high-density power
supplies, this estimate will be the minimum inductor
value at low line considering safe permeability droop for
powdered-core inductors using materials like MPP, Kool Mu
and other materials with a soft BH curve. This is reflected
in the values shown in the table, which include full load at
low-line inductance values as well as no-load values. The
latter values reflect the expected inductance at higher line
voltage and lower inductor current.
To calculate the current operating conditions for the
boost diode in detail, we’ll have to consider the highfrequency switching behavior with the boost inductor, as well
as the low-frequency ac mains waveform. To address this,
the operating ripple current and pulse-by-pulse operation
is calculated using MathCAD. The input voltage and current
determine the operating points for the boost diode over
one complete ac cycle at the specified input voltage—low
line in this case.
First, functions specifying the ac operating period and the
input voltage, as well as an indexed variable for the period,
are defined:
1
(Eq. 3)
TMAIN =
, ω = 2π × f MAIN
f MAIN
Table. Calculated current and inductor values for multiple output
power categories (assumptions: 85 Vac, 40% permeability droop for
inductor and ~90% PWM efficiency).
on the ripple-current level that can be tolerated, which
is typically in the range of 20% to 30%. From the inputto-output duty cycle of the boost converter, VOUT /VIN =
1/(1-D), the duty cycle for 85 VacIN and 400-V bulk bus is
derived:
IINRMS =
2POUT
ηVINRMS 2
, IINPK =
2POUT
ηVINRMS
.
VINPK t ON
.
0.3IINPK
(Eq. 2)
From this, a working value is estimated for the boost
inductor (LP):
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Power Electronics Technology June 2006
SIC DIODE
ripple current in the inductor can be calculated over the
mains period, starting with the maximum diode current
(IDMAX
):
MA
25
1
IDMA
(t M
∆IL (t MAIN
MAI
AIN ) = I IIN
AIN
N (t M
MAI
AIN ) +
AIN
MAIN )
MAX
X
2 OFF
Current (A)
20
1
IIN (t MAIN
∆IL (t MAIN
MAIN ) −
AIN ) if I IN (t MAIN
AIN ) >
2 OFF
.
∆ILOFF (t MAIN
)
MAIN
(Eq. 12)
This assumes one diode in the boost rectifier position;
otherwise, the diode current is shared between the diodes.
The shared current technique is generally only feasible with
Schottky diodes because of their positive coefficient of
on-state voltage with temperature.
The RMS current for the diode ( IDRMS
) is calculated by
RMS
integration. This gives a different, perhaps even misleading,
picture of the diode load as can be seen in the table.
IDMIN (t MAIN
AIN )
15
10
5
0
(Eq. 11)
IDRMS =
0
5
10
15
TMAIN
×∫
TMAIN
0
2
ID (t MA
MAIN
IN ) dt MAIN .
(Eq. 13)
The table shows the calculated PFC output power and
other parameters for SMPS at selected output power levels
between 350 W and 1000 W. The recommended full-load
and no-load inductor values are shown for two operating
frequency ranges, 100 kHz and 250 kHz, and the RMS and
peak currents with 85-Vac input line voltage have been calculated. This is representative of typical worst-case steady-state
low-line conditions. Actual worst-case conditions can be
more extreme under dynamic conditions, such as startup or
brownout recovery, and when the bulk bus voltage has sagged
lower than the nominal 300 V due to cycle skip or high load.
These factors can increase the current level 20% to 25%.
At first look, this seems to present primarily a forwardcurrent problem, but consider that, for conventional pn
diodes, the diode-induced switching loss from QRR is strongly
dependent on junction temperature and operating current.
Consequently, a low duty cycle/high peak current is a worstcase situation that dramatically raises the stress on the boost
switch and the diode from the QRR-induced switching losses
when operating at low line. The difference in QRR is a function
of operating current, temperature and the rate of di/dt. So
with silicon pn diodes, the upper switching frequency limit
will rarely be much higher than 100 kHz in order to avoid
thermal runaway.
Fig. 2 details the calculated current waveforms for steadystate low line. These are representative values for a 1-kW PFC
converter with 110-W output power, and the suggested boost
inductor for 100 kHz. The green trace is the input current
for 85-Vac line voltage, the blue trace is the calculated average switch current and the red trace is the calculated average
diode current. Note that the yellow trace shows the peak
diode current level when the boost switch turns off and the
boost rectifier begins conducting.
It is possible to avoid QRR-related switching losses in PFC
converters by using 600-V silicon carbide (SiC) Schottky
Time (ms)
Average current of switch
Input current
Average current of diode
Peak boost diode current
Fig. 2. The calculated current waveforms for a 1-kW PFC converter
example reveal the magnitude of input, diode and switch currents
under low-line (85 Vac) conditions.
VIN (t MAIN ) = VINRMS 2 sin(ω × t MAIN )
(Eq. 4)
1
t MAIN = 0 ms,
, ...TMAIN .
(Eq. 5)
f S × 10
Using the previously calculated values for RMS input
current, a waveform for the PFC input current can be
calculated:
i IN (t MAIN
2 sin(ω × t MAIN ) .
(Eq. 6)
MAIN ) = I INRMS
Next, the duty cycle for boost switch and diode will be
calculated over one ac mains period, as the prelude to calculating the ripple current. First, the switch duty cycle (dS)
is defined:
VIN (t MAIN
V
MAIN )
d S (t MAIN
> DSMA
, DSMAX , 1 − IN ,
AIN ) = if 1MAX
X
VOUT
VOUT (Eq. 7)
where DSMAX
is the maximum duty-cycle capability of the
MA
PFC controller. The diode duty cycle (dD) takes the remainder
of the clock period:
d D (t MAIN
(Eq. 8)
AIN ) = 1 − d S (t MAIN
MAIN ) .
Next, the ripple current ∆I as a function of input voltage
and duty cycle is calculated for the switch and diode:
VIN (t MAIN
MAIN )
d S (t MAIN
(Eq. 9)
AIN )
LP
VOUT − VIN (t M
MAIN
AIN )
AIN
.
(Eq. 10)
∆IILOFF (t MAIN
d D (t MAIN
AIN ) =
AIN )
LP
The minimum and maximum diode currents due to
∆IILON (t MAIN
AIN ) =
Power Electronics Technology June 2006
1
30
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SIC DIODE
I peak = 32 A
T = 12 µs
tPULSE = 4 µs
Fig. 3. A measurement of the input current through an SDT06S60 600V
SiC Schottky diode in a commercial SMPS shows the startup surge
current (the input voltage equals 100 V, the Ch. 2 amplitude scale
equals 5 A/div, the time scale equals 0.2 sec/div and the temperature
equals 25°C).
Fig. 4. The boost diode current from Fig. 3 is remeasured with an expanded sweep speed, revealing a peak diode current of approximately
32 A. (The Ch. 2 amplitude scale equals 10 A/div, the Ch. 2 time scale
equals 2 ms/div, the Ch. B amplitude scale equals 10 A/div and the
Ch. B time scale equals 5 s/div.)
diodes, which have become commercially available since
about the year 2000. [1] With no hole-carrier-related
QRR, and only capacitive displacement current as a switch-
ing loss factor, exceptional high-speed switching performance has been demonstrated by commercially available
components.[2, 3, 4]
However, like their silicon Schottky counterparts, the SiC
Schottkys use only majority carriers, and the positive temperature coefficient of on-state voltage limits their surgecurrent capability. In applications like wide-input-range
PFC converters, the overcurrent limitation may dictate that
the component be sized more for this characteristic than the
nominal operating conditions.[5, 6] How much of a problem
can this be in a typical application, considering the dynamic
events usually define the boundary conditions?
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Surge Current at Startup
Fig. 3 shows the diode current waveform in an SDT06S60
600-V SiC Schottky diode in a commercial power supply
for which the controller IC doesn’t have a particularly
well-managed soft-start characteristic. The peak startup
current in the boost diode exceeds 30 A for portions of the
startup period. This test was conducted with an ambient
temperature of 25°C, and measured from a cold starting
condition.
In Fig. 4, the same event is displayed with a higher main
sweep speed of 2 ms/div, and an expanded sweep on the B
channel of 5 µs/div. In this view, it’s clear that the peak diode
current is about 32 A with an operating duty cycle of about
33% (4 µs out of the pulse period of 12 µs). The question that
arises when this behavior is discovered during the testing of
a new design is, is this safe and, if so, with what margin?
One way to estimate the margin is to use a wideband
long-channel-length scope with integration capabilities and
establish the I2T stress on the diode. If an instrument like this
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Power Electronics Technology June 2006
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Fig. 5. The structure of a conventional SiC Schottky diode (top) is
compared with that of the merged pn/Schottky SiC diode (bottom).
isn’t available, another possibility is to prepare simulations
using full electrothermal SPICE or SABER models. Note that
conventional SPICE or PSPICE models lacking transient
thermal impedance structures and the modification of device
parameters as a function of junction temperature will not
be usable evaluating this type of problem.
In this case, an analysis was performed using the current
load waveforms as the input to the SiC Schottky rectifier. Due
to the positive temperature coefficient of forward voltage,
the actual power dissipation and predicted junction rise are
variable, depending on starting junction temperature. At
25°C, the typical ∆T is ~35°C and the worst-case part is
~52°C, posing no problem.
But with increasing ambient temperature, the situation
changes. At a TCASE starting temperature of 75°C, the typical
∆T is ~42°C and worst case is ~63°C, possibly resulting in
a terminal junction temperature of ~138°C, which is still in
spec but does not meet the derating criteria of many SMPS
customers in the computing segment. If we consider the
case of the 125°C starting temperature—which one would
hope is outside the realm of likelihood—a typical ∆T of
~50°C results, with a worst-case rise of ~75°C. This places
the junction temperature at ~200°C, well outside the safe
specification for the package and die attach.
Although SiC is fu an 8-A or 10-A rating to meet the surge.
The required oversizing for surge current in wide-inputrange PFC applications is part of the perception of a poor
value proposition for SiC Schottky diodes in general.
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Power Electronics Technology June 2006
SIC DIODE
Merged-Structure SiC Diode
40
To address this problem optimally, a new concept for
the high-voltage SiC rectifier has been developed using a
30
merged-structure device combining both Schottky and pn
25
structures, with a low-ohmic connection of p regions to
20
the anode of the device (Fig. 5).[7] This concept takes
advantage of the wide bandgap potential of SiC, where
15
Ideal characteristic: merged pn-Schottky diode
under normal operating conditions, the high pn junction
10
Bipolar pn diode forward characteristic
Schottky diode forward characteristic “cold”
potential (~3 V to ~4 V) of SiC will prevent conduction of
Schottky diode forward characteristic “hot”
5
Current surge capability
the pn structure. Only in overload conditions will this for0
ward voltage be reached, and the pn structure will provide
0.00
2.00
4.00
6.00
8.00
10.00
12.00
14.00
VF (V)
hole-carrier injection for conductivity modulation of the
drift region.
Fig. 6. The merged-structure device combines the transfer functions of
The p regions, sometimes employed in floating p bodies
both Schottky and pn structures.
in Schottky devices, have other benefits in that they will concentrate the maximum electrical field away from the Schottky
70
barrier surface. This allows using a higher-maximum field
Second-generation 6-A
potential in the blocking mode without degrading the bardiode, 400 �s current
pulses
60
rier and compensates for the area used by the P wells. This
also provides a true and consistent avalanche breakdown
characteristic—which is not possible across a Schottky bar50
rier—that secures additional ruggedness in the handling
and testing. Due to the material characteristics of the SiC
40
crystal lattice and the very thin epi layer possible with SiC
Schottky mode
high-breakdown field strength, the impact of pn junction
30
operation on the normally negligible stored charge of the
Bipolar mode
SiC Schottky diode is essentially unmeasurable, even at 10
times the rated current.
20
The combination of transfer functions of both Schottky
25°C
100°C
and
pn structures depicted in the graph of Fig. 6 is typical
10
150°C
of a 4-A diode. The Schottky transfer function shows a junc175°C
tion potential around 0.8 V with an initial linear resistance
0
that saturates with increasing current due to current den0.0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
sity, ultimately resulting in a rapidly rising forward voltage
VF (V)
when the current destruction point of the diode is reached.
Fig. 7. Typical values of VF were measured as a function of IF at different
This saturation current is not fixed but rather a function of
values of starting junction temperatures.
junction temperature; with increasing
junction temperature, the maximum
180
current is reduced, which results in
SDT04S60 4A
lower surge capability.
160
Contrast this with the pn junction
curve: the initial junction potential is
140
quite high due to the wide bandgap of
Start at normal
silicon carbide, but due to hole-carrier
operation
temperature
120
injection, the achievable current density
2G IDT04S60C
80°C
is much higher—following a very linear
100
function that actually extends up to 100
35°C
times the diode rated current, as testing
has shown. In principle, combining
80
these structures should result in the lower forward dissipation of the Schottky
60
0.65
0.67
0.69
0.71
0.73
0.75
0.77
0.79
0.81
0.83
0.85
at current levels up to a few times the
Time (sec)
rated forward current of the diode, with
the large overload capability and higher
Fig. 8. An electrothermal simulation of junction temperature rise for a conventional SiC
peak current of the pn structure.
Schottky diode and a second-generation, merged-structure diode reveals a better than 2-to-1
advantage for the latter.
In practice this is the case, as the
Simulated TJ (°C)
IF (A)
IF (A)
35
Power Electronics Technology June 2006
34
www.powerelectronics.com
SIC DIODE
current saturation effect of the Schottky is removed (Fig. 7)
and the 400 µs pulse operating range is extended to beyond
10 times the rated current over a range of starting junction
temperature of 25°C to 175°C.
Returning to the startup surge current problem, let’s
look at a similar example for a PFC using the 4-A diodes
(Fig. 8). As previously, we use the measured current waveform as an input for simulation of the junction temperature
rise of the diode. This graph compares the predicted junction temperature rise between the original 4-A devices and
the merged-structure diode, based on a starting temperature
typical for steady-state operating conditions. This simulation is representative of what occurs in
many cases when there is a brief power
interruption, perhaps just a few cycles,
and a restart occurs when the equipment is hot. The advantage is quite clear
toward the end of the startup phase, with
a better than 2-to-1 ratio in predicted
junction temperatures. The peak junction temperature is well within preferred
derating criteria as well as nominal
device limits.
In practice, with this merged-structure
technology, a diode of typically one-third
lower current rating can be used with
safety and performance similar to the
more expensive higher-current-rated
conventional SiC Schottky diode. This
comes with no loss in overall performance and significant secondary benefits,
including consistent avalanche breakdown capability and demonstrated safety
with high dV/dt.[7]
PETech
proceedings from CPES-NSF Silicon Carbide Symposium,
May 2003.
5. Zverev, I. “Switching Frequency Related Trade-offs in a
Hard Switching CCM PFC Boost Converter,” CD-ROM
proceedings from APEC 2003.
6. Zverev, I.; Kapels, H.; Rupp, R.; and Herfurth, M. “Silicon
Carbide Schottky: Novel Devices Require Novel Design
Rules,” proceedings from PCIM 2002.
7. Bjoerk, F.; Hancock, J.; Treu, M.; Rupp, R.; and Reimann,
T. “2nd Generation 600V SiC Schottky Diodes Use Merged
PN/Schottky Structure for Surge Overload Protection,”
proceedings from APEC 2006.
References
1. Rupp, R.; Treu, M.; Mauder, A.; Griebl,
E.; Werner, W.; Bartsch, W.; and Stephani,
D. “Performance and Reliability Issues
of SiC-Schottky Diodes,” presented at
International Conference on SiC and
Reliability Comp, 1999.
2. Kapels, H.; Rupp, R.; Lorenz, L.; and
Zverev, I. “SiC Schottky Diodes: A Milestone in Hard Switching Applications,”
proceedings from PCIM 2001.
3. Agarwal, A.; Singh, R.; Ryu, S.H.; Richmond, J.; Capell, C.; Schwab, S.; Moore,
B.; Palmour, J. “600V, 1-40A Schottky
Diodes in SiC and Their Applications,”
proceedings from International Power
Electronics Technology 2002 Conference,
pp. 631-639.
4. Rupp, R., and Hancock, J. “SiC Power
Devices Tailored for Power Management
and Supply Applications,” CD-ROM
www.powerelectronics.com
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Power Electronics Technology June 2006