IC Design
Jan Pleskac
Embedded Systems Design
Staff IC Design Engineer
30/11/2011
Copyright © S3 Group
Agenda
Introduction
•
•
Presenter and S3 introduction (just for context, no marketing)
Motivation
Embedded Systems (ES)
•
•
•
Definition and characteristics
ES Life Cycle
How good ES looks like?
ES design analogy with ASIC design
•
•
System architecture
Why power matter?
Conclusion
Copyright © 2007-2008 Silicon & Software Systems Limited
Slide 2
Embedded System - Definition
•
“An embedded system is a computer system designed for specific
control functions within a larger system.” Source Wikipedia
•
User interface - not necessary
•
Interface for interaction with other systems
•
•
RS232, USB, GPIO, SPI, I2C, ADC, DAC, Ethernet etc.
System on Chip – SoC
•
“Integrated circuit that integrates all components of a computer or other
electronic system into a single chip” Source Wikipedia
Copyright © S3 Group
Slide 6
Product Life Cycle
Need/Opportunity
Concept
Development
Retirement
Product Design &
Manufacturing
Upgrades
Support /
Maintenance
Production /
Deployment
Copyright © S3 Group
Slide 8
Product Life Cycle
•
NEED - Understand the purpose of the Product/Embedded System
•
•
•
Use CASE scenario
Functional Specification
Performance Requirements (power, throughput, Msps, ENOB, etc.)
•
Ask “What can be remove and still deliver required design?”
•
•
•
Communication issues
Application domain specific aspects
Application domain “known” aspects
Copyright © S3 Group
Slide 9
Product Life Cycle
•
Overdesign
•
•
“to design in manner that is excessively complex or that exceeds usual
standards” Source Merriam-Webster dictionary
Over-Constrain
•
•
•
X<Y, Y<Z, Z<X
Power vs. Speed requirements
Peek vs. Normal mode performance
Swiss Army Knife - Source Wikipedia
Copyright © S3 Group
Slide 10
Product Life Cycle
•
Concept development
•
•
•
Feasibility study
Quick research (IP suppliers, legal, domain experience)
Prove-Of-Concept (POC)
• short term development
• incomplete delivery from product perspective, but focused to key aspects
•
Design – typically small part of Life Cycle
•
•
•
Scope
(Un)certainty in NEEDs definition (What has to be done?)
Time to market pressure
Budget constrains
Time
Cost
Copyright © S3 Group
Slide 11
Embedded System / SoC
Copyright © S3 Group
Slide 12
System Design Trends
•
HW/SW partitioning
•
•
•
Hi-Level Modeling
•
•
•
•
•
Speed vs. Flexibility
Embedded CPU capability
Accuracy vs. Simulation
Algorithm POC in real word scenario
System performance analysis (on chip interconnect)
Early SW development – SW/HW co-design/co-verification
From IP to Micro Architectures
•
•
Buy vs. Make decisions
Aspects to be considered
•
•
time, cost, quality, flexibility, business model, risk
Growing complexity
Copyright © S3 Group
Slide 16
System Design
•
PCB with discrete components shrinking in
•
•
•
SoC – System on Chip
SiP – System in Package
•
•
Area, BOM reduction (Bill of Material)
Combo Flash/SRAM memory
ASSP - Application Specific Standard Product
•
•
•
Designed for specific market/domain, standard interfaces
Automotive (Motor Control, Audio)
Latest FPGAs with MultiCore CPU & peripherals HardMacro
• Programmable logic fully available for custom application
•
ASIC – Application Specific IC
•
•
Designed & tailored for specific needs
Power, Functionality, Security, Proprietary
Copyright © S3 Group
Slide 17
System Design – key aspects
•
Power
•
•
•
•
Generation DC/DC – fixed/variable output
Distribution (IR drop)
Peek vs. normal mode
System initialization
•
•
Power on Reset
Reset /Power sequencing
•
•
Clock generation & distribution
Clock domains crossing / resynchronization
•
PINOUT & ESD
•
Architecture is key for addressing those phenomena
Copyright © S3 Group
Slide 18
Power consumption and reduction
•
Power reduction techniques
P ~ Pactivity + Pshort + Pleakege
– Clock tree optimization & Clock gating, operand isolation, Multiple Vth,
MSV, DVS, DVFS, AVFS, PSO, Substrate bias, Memory split
(Picture from powerforward.org – LP_guide.pdf )
Copyright © 2007-2008 Silicon & Software Systems Limited
Slide 19
Power Consumption Physics
P = Pactivity + Pshorcircuit + Pleakage
Pactivity = A * f * Ceff * Vdd2
Pshortcircuit = Isc * Vdd * f
Pleakage = f ( Vdd, Vth, W/L )
Note: Different approach
has different impact. What
is appropriate should be
addressed by ARCHITECTURE
(Picture from powerforward.org – LP_guide.pdf )
Copyright © 2007-2008 Silicon & Software Systems Limited
Slide 20
Low Power Techniques
•
MSV – Multi Supply Voltage
•
DVFS – Dynamic Voltage Frequency Scaling
•
•
•
AVFS – Adaptive Voltage Frequency Scaling
•
•
•
Compensate for temperature, IR drop etc.
Closed-loop system
PSO – Power Shut-Off (Power Domains)
•
•
Prediction of computation load
Open-loop system
Most effective – eliminates leakage
Memory splitting
•
•
Scaling memory with actual need – power off/freeze control signals
L1/L2 cache on-chip and main memory off-chip
Copyright © 2007-2008 Silicon & Software Systems Limited
Slide 21
Low Power – Dynamic power reduction
•
Dynamic power
– Voltage, frequency
• PSO, MSV, DVFS, AVFS
• Reduce activity
– Reduce glitches
» Bus encoding
» algorithms
• Reduce short circuit current
– Equal rising/falling edges
– Short transition time
» Xtalk risk
– Load
• Logic restructuring
•
Addressed by technology and library selection
Copyright © 2007-2008 Silicon & Software Systems Limited
Slide 22
Low Power – Leakage power reduction
•
Leakage power
– Power voltage
• PSO, MSV, DVFS, AVFS
– Vth – VGS
• MTH
• Back/forward biasing
– Process
•
•
•
•
LP process
Hi-K metal gate
Strained silicon
SOI
– Implementation
• Dynamic gate length cells
• Complex gates
• Stack forcing
– Lowest leakage stage
– Multi input gates
– Future
• Dominant issue in coming technologies
Copyright © 2007-2008 Silicon & Software Systems Limited
Slide 23
Low Power – Power shut-off
•
PSO
–
–
–
–
–
PSO + single Vdd – most popular LP method
Recommended to define inactive isolation value
Use Hvt switch
CPE – determine number of PS
Always on cells
• Secondary power routing
– Implementation complexity
•
Stand-by mode
– Minimum voltage to maintain state
– Gate all inputs
Copyright © 2007-2008 Silicon & Software Systems Limited
Slide 24
Low Power – Advanced techniques
•
DVFS
–
–
–
–
–
–
–
–
•
Performance requirements
System level approach
Well defined clock boundaries and IFs
Complicated level shifters
Mode transitions – PV challenge
Complex Vdd generation
Complex clock generation and STA
ECSM libraries
AVFS
– HW monitors
• PVT
• timing
• load
– Complex Vdd generation (D 10mV)
– Verification challenges
Copyright © 2007-2008 Silicon & Software Systems Limited
Slide 25
Conclusion
•
Understand the context of your task
•
You have to always know why you are doing “XYZ”
•
Learn by watching (look around)
•
Design is small part in Life Cycle, but with huge impact to success
•
Appropriate architecture saves lot of headache
•
Remember “Cost of change” with respect to project stage
•
Think positive & share your ideas!
Copyright © S3 Group
Slide 27
Resources
•
www.eetimes.com
Design pages – domain focused pages (Audio, MCU, RF, etc.)
•
Vendors websites
•
•
Webinars & other public domain resources
•
•
•
•
MCU, ADC, ADC and other IC providers
www.eclub.cz
Linkedin & other social networks
metatv.cz
ARM TechCon 2011 – “2020 in 26 Easy Steps”
•
http://vimeo.com/31572096
Copyright © S3 Group
Slide 28
Thank You
Please send me your feedback
jan.pleskac@s3group.com
Copyright © S3 Group