Science Series Data Report
Vol 4, No. 5;May 2012
DAC Mismatching Compensation in Multibit Sigma-Delta
Modulators with Two-Step Quantization
Sakineh Jahangirzadeh
Department of Electrical Engineering, Shahid Chamran University of Ahvaz, Ahvaz, Iran
E-mail: s_jahangirzadeh@yahoo.com
Ebrahim Farshidi
Department of Electrical Engineering, Shahid Chamran University of Ahvaz, Ahvaz, Iran
Tel: 61357-8313
E-mail: farshidi@scu.ac.ir
Abstract
The use of multibit quantizers in sigma-delta modulators can increase SNR, improve stability and
reduce integrator power consumption. However, using multibit quantizers causes nonlinearity in DAC
converter. In recent decades the uses of data weighted averaging (DWA) methode has been proposed
for reducing mismatch errors. However, each added bit to quantizer resolution causes an exponential
increase in the power dissipation, required area and complexity of the DWA circuit required to
attenuate DAC mismatch errors. This paper proposes the prospect of using a segmented feedback
path with coarse and fine signals to reduce DWA complexity for modulators with large internal
quantizers. This reduces the DWA circuit complexity, power dissipation, and size. But this method adds
an additional noise to system. To overcome this problem, two solutions are suggested: one that uses
calibration method to cancel mismatch between coarse and fine DACs, and another that
frequency-shapes this mismatch error using requantization method.
Keywords: Sigma-Delta modulator, Data Wighted Averaging (DWA), Segmentation
1.
Introduction
The sigma-delta analog to digital modulator (Σ∆
ADC) has been widely used in recent decades for
low frequency, high resolution applications such
as
digital
audio
and
high-precision
instrumentation [1]. Recently, however, is
extending the signal bandwidths of Σ∆ ADCs
into the MHz range while maintaining high
resolution [3].
Three of the key design parameters that affect
the resolution of a Σ∆ ADC are: the sampling
frequency relative to the bandwith of interest
(OSR), the order of the noise transfer function,
and the number of internal quantization levels.
As each is increased, the theoretical resolution of
the ADC is increased. However, the complexity,
power dissipation, and required chip area also
increase.
32
Early Σ∆ converter used a single bit quantizer in
the loop because of their suitability for VLSI
implementation and their superior linearity
[4],[5]. The use of multibit quantization has been
limited because non linearity in the DAC of a
sigma-delta modulator translates directly into
non linearity of the entire modulator, producing
a distorted output. Non linearity in the DAC also
modulates the quantization noise into the signal
band, thus degrading the SNR. However,
multibit modulators have several advantages
such as increased resolution for the same
oversampling ratio, improved stability, relaxed
amplifier requirements and better tone behaviour
[1].
Attempts to eliminate the non linearity problem
associated with multibit Σ∆ modulators have
resulted in the use of DWA techniques which
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Science Series Data Report
shape the noise generated by DAC unit element
mismatch, shifting it to higher frequencies which
are out of the band of interest.
Increasing internal quantization levels beyond
five bits improves SNR but presents significant
challenges. Both the internal quantizer and the
DWA logic grow exponentially in complexity,
size, and power dissipation as the internal
quantizer resolution increases. Using two-step
ADC is a logical alternative for reducing
quantizer power. A folding ADC could provide
quantization above eight bits while still
maintaining the low latency required of the
internal quantizer. Recent work has also shown
that it is possible to incorporate two-step ADCs
with in asingle loop modulator, permitting lower
power quantizers while maintaining loop
stability [6], [7].
This paper will present two architectures that
permit the uses of DWA with two step quantizer.
The paper is organized as follows. In section 2,
basic principle of the data weighted averaging
algorithm is presented. In section 3, the
problems associated with applying traditional
DWA algorithm to a segmented coarse/fine
DAC structure are discussed. In section 4,
calibration method and requantization method in
section 5 to overcome these problems are
proposed. Simulation results are presented and
discussed in section 6,and concluding remarks
are provided in section 7.
2.
Vol 4, No. 5;May 2012
beginning with the next available unused
element. The operation principle is illustrated in
Figure 2. V(n) denotes the DAC input at clock
cycle n. In the 1st clock four unit elements are
selected. Then in the next clock the elements are
selected from the first unused, that is the 5th
element. If the last element is selected, DWA
will start to select the 1st one again. DWA shapes
the nonlinear errors with the first-order transfer
function (1-z-1) [ 8],[11].
3.
DWA With Segmented Quantizer
A two-step architecture for the internal
quantizercan solve some of the problems arising
Figure 1. Block diagram of the data weighted
averaging (DWA) method
The Data Weighted Averaging (DWA)
Algorithm
Multi bit quantization improves the stability and
the signal to quantization noise performance
of sigma-delta converters, but
it
also
necessitates the use of dynamic element
matching (DEM) to filter the nonlinearity error in
the signal band . Data weighted averaging (DWA)
is the most widely used DEM algorithms, due to
its simplicity and low hardware overhead.
Figure 1 shows block diagram of the data
weighted averaging (DWA) method.
The basic concept of DWA is to guarantee that
each of the elements is used with equal
probability for each digital input code. This is
realized by sequentially selecting elements,
33
Figure 2. The DWA operation principle
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Science Series Data Report
Vol 4, No. 5;May 2012
from increasing the internal quantization
levels beyond five bits. Since these
architectures provide the digital data in two
sections, coarse bits and fine bits, a logical
way to interface with the DWA is to simply
perform DWA independently on the coarse
and fine DAC banks, as illustrated in Figure
3. The quantizer produces NC bits as the
coarse signal and NF bits as the fine signal,
for a total of N bits (N = NC+NF). Figure 4
shows a mathematical representation of the
segmented architecture from Figure 3.
The two-step quantizer resolves the NC coarse
bits, and then subtracts this value from the input
Figure 3. Block diagram of segmentated Σ∆
ADC
and generates the NF fine bits from this signal.
The gain of 2 ( N  NC ) inside the quantizer
represents a binary right shift to insure the
correct place value of the bits, since the coarse
bits are the NC most significant bits of an N bit
signal. Since DWA shapes the error due
mismatch unit element DAC with first order
transfer function , the DWA blocks can be
represented as (1-z-1) , as seen in Figure 4. The
coarse and fine outputs are each applied to
separate DACs using smaller, independent DWA
circuits, reducing DWA complexity significantly.
The coarse DAC transfer function is weighted by
2 ( N  N C ) times that of the fine DAC to insure
that the original place values are preserved.
However, since this weighting depends on the
size of the unit elements involved, a gain
mismatch, 1- , will be present. The quantization
noise, QC, present in both signals YC and YF ,
ideally will cancel when the coarse and fine
signals are summed together at the modulator
input. This result be the same as if a single DWA
circuit with a single DAC had been in the
feedback path. However, because of the gain
Figure 4. Mathematical Block Diagram of
Segmented ∆Σ ADC
and will be transmitted to the output.
When the coarse and fine signals are summed
together, the quantization noise
will not
completely cancel while in the single-path
method would completely cancel because of
gain mismatch between the coarse and fine DAC
banks in the segmented method. The
non-canceled portion of the quantization noise
will be added directly to the input signal, and
thus be transmitted to the output of the ΣΔ ADC.
The output, Y, of the ΣΔ ADC in Figure 4 can be
written as :
mismatch between the DACs, the coarse
quantization
34
error will not completely cancel
Y ( z )  Yc ( z ).2 N  N C  YF ( z )
(1)
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Science Series Data Report
Vol 4, No. 5;May 2012
where
YC (z) 
2(NNC)[QC (z)  (X (z)  (1 Z 1)YF )H(z)]
1 (1  )(1 Z 1)H(z)
(2)
Y F ( z )  QC ( z )  Q F ( z )
(3)
by substituting (2) and (3) into (1), it is obtained
as follows :
Y (z) 


X ( z)H ( z )
1  (1   )(1  z 1 ) H ( z )
QF ( z )
1  (1   )(1  z 1 ) H ( z )
(4)
 (1  z 1 )(QC ( z )  QF ( z )) H ( z )
1  (1   )(1  z 1 ) H ( z )
For comparison, a single-path approach would
lead to:
Y ( z) 

X ( z) H ( z)
1  (1  z 1 ) H ( z )
Q( z)
(5)
1  (1  z 1 ) H ( z )
A comparsion of equations (4) and (5) show that
the segmented system has error term ε · (QC −
QF )(1-z-1) present in addition to normal
quantization noise. The value of the mismatch
term, ε, changes with each clock cycle due to the
operation of the DWA. For realistic unit-element
mismatch values, ε is small, but still large
enough to significantly affect the SNR of the
system.
4.
value. So the mismatch, ε from equation (4) can
be reduced by matching the average element
values between DACs with the ratio of 2N-Nc : 1.
The individual DAC element values are not
important, as long as the average element values
meet this ratio. In an attempt to measure and
match the average element values between
coarse and fine DACs, a start-up calibration
procedure can be used as shown in Figure 5.
During calibration, the connections from the
coarse/fine ADC to the feedback path are broken
and a single-bit path provides the modulator
feedback. A one-bit quantizer is used because it
is immune to the mismatch that plagues multi-bit
quantizers. The modulator input is grounded and
a fixed, DC test signal is presented to the coarse
and fine DACs through the DWA circuitry. The
output is sent to an averaging synck filter, and
then measured for each DAC individually, with
the other DACs disconnected from the circuit.
The relative measurement between coarse and
fine DAC banks can then be used to make the
necessary adjustment to match the ratio of the
average DAC element values. These individual
measurements are then compared and used to
calculate how much a single fine element must
be adjusted to insure an average element size
ratio of 2N-Nc : 1.
A distinct advantage of the calibration method is
the low complexity of the feedback path. For
an 8-bit quantizer, two independent, 4-bit DWA
implementations are required. Thus both the
complexity and the timing delay of the digital
feedback path are minimal.
Calibration Method
The mismatch term, ε, from equation (4)
represents the deviation from the desired gain
ratio of the coarse and fine DACs. Each DAC’s
gain changes with every cycle due to the DWA
operation. However, since
ΣΔ ADCs use
oversampling, the average gain of the DAC over
time is more important than any instantaneous
Figure 5. Block diagram of calibration method
35
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Science Series Data Report
5.
Vol 4, No. 5;May 2012
The Noise-Shaped Requantization (ReQ)
Method
The mismatch error between coarse and fine
banks can be noise shaped if the coarse
quantization is performed within a digital Σ∆
modulator. This method was initially proposed in
[9] for a Σ∆ DAC, then this method in [10] was
proposed for Σ∆ ADC along DEM with gain of
unity. This paper extends this concept to Σ∆
ADCs with DWA algorithm.
The basic idea is to generate a new coarse signal
with a digital Σ∆ modulator and use this
coarse signal to generate a new fine signal. This
insures that both the coarse and fine signals are
individually noise shaped, which is performed in
a way that causes the quantization error leakage
to be noise shaped as well. Even though it does
not completely cancel errors due to DAC
mismatch, the quantization error noise power
will be outside the signal band. The process is
modeled in Figure 6. Figure 7 shows a
mathematical representation of the ReQ
architecture from Figure 6. The digital coarse
and fine signals from the quantizer are first
concatenated to form an N-bit signal. This signal
is then requantized to NC bits using a digital
first-order Σ∆ modulator. Then coarse signal is
subtracted from the original N-bit signal to form
the new fine signal, comprised of NF+1 bits.
After requantization, the new coarse and fine
signals become:
YC ( z )  2
 ( N  NC )
[Y ( z )  Q C ( z )(1  z
Y F ( z )  QC ( z )(1  z 1 )
1
)]
Figure 7. Mathamatical block diagram of REQ
method
(6)
noise-shaped away from the signal band. The
output of the system with ReQ as in Figure 7 is
derived as follows:
(7)
Y ' ( z )  Yc( z ).2 N  N C  Y F ( z )
Signals Y'C (z) and Y'F (z) then pass through
independent DWA blocks and DACs and are
summed at the input of the modulator. With
first-order requantization (ReQ), the quantization
error that is not completely cancelled due to
coarse/fine DAC mismatch as in Equation (4) is
36
Figure 6. Block diagram for REQ method
(8)
where
YC ( z )  2  ( N  NC ) [QC ( z )  ( X ( z )
 (1   )(1  z 1 ) 2 N  N C .YC ( z )
(9)
 Y F ( z )(1  z 1 )) H ( z )]
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Science Series Data Report
Vol 4, No. 5;May 2012
and
YF ( z )  QC ( z )  Q F ( z )
(10)
by substituting (9) and (10) into (8), it is
obtained as follow:
Y ' ( z) 


X ( z) H ( z)
1  (1   )(1  z 1 ) H ( z )
QF ( z)
1  (1   )(1  z 1 ) H ( z )
For the calibrated simulation, one of the fine
DAC elements was adjusted to correct the gain
ratio between the coarse and fine DACs. The
simulation results for the calibrated system and
the power spectrum density of its output signal
are shown in figures 9 and 10 respectively. For
the mismatch of 1% the results show that the
calibrated system has a drop of only 0.5 dB in
the SNR which is much lower than that of the
segmented system.
(11)
( .QC ( z ))(1  z 1 ) 2 H ( z )
1  (1   )(1  z 1 ) H ( z )
which shows that that the coarse quantization
noise leakage is first-order shaped. Simulations
show that higher order REQ is not necessary,
first order REQ sufficiently suppresses coarse/
fine mismatch errors below the noise shaped by
the DWA within each DAC.
6.
Simulation Results
In order to verify the validity of the proposed
calibration and REQ methods in this paper a
second order sigma delta modulator with 8-bit
quantizer (4 bit coarse, 4 bit fine) and an OSR of
30 has been simulated using MATLAB. Figure 8
shows the simulation results for both segmented
and single-path
systems versus various
unit-element mismatch percentages. The element
sizes were selected assuming that the coarse
element percent mismatch be (24)1/2 times lower
than the fine element mismatch due to the 24
sizing ratio. As shown in figure 8, with the
addition of unit element mismatch, the overall
SNR of the segmented system drops much faster
than the single-path system. The results of
simulation show the SNR of segmented system
with 1% mismatch, is 20 dB lower than that of
single-path system.
Figure 8. Simulated results for segmented
system
Figure 9. Simulated results for calibration
system
37
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Science Series Data Report
Vol 4, No. 5;May 2012
Figure 10. Power spectrum density of output the
Figure 11. Simulated Results for REQ system
∆Σ modulator using calibration method
Figure 11 compares the performance of the
segmentation and ReQ methods against the
single-path
method. Again, a (4+4)–bit
quantizer, second-order modulator with an OSR
of 30 was used, and also the coarse and fine
percent mismatches were scaled assuming a 16:1
size ratio between coarse and fine elements. The
figure 12 shows power spectrum density of the
output signal for REQ system for the case of
1% fine element mismatch. The ReQ method
achieves an average SNR of 106.337 dB, which
is only 2 dB less than that of the full 8-bit DWA
method however number of unit elements of
DWA circuit much less than that of single-path
method. The simulated results are summarized in
Table 1.
Figure 12. Power spectrum density of output
the ∆Σ modulator using requantization method
Table1: Simulated Results
38
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Science Series Data Report
7. Conclusion
The DWA algorithm modulates the nonlinarity
error of the DAC due to mismatch unit elements,
moving the harmonic distortion out of the signal
bandwidth. However each
added bit of
quantizer casuses an exponential increase in
complexity of DWA and DAC circuitry.
The segmented architecture with coarse/fine
DAC and DWA combined with either the
calibration or ReQ methods proposed in this
paper allow for larger internal quantizers without
the exponential increase in DWA logic, while
still maintaining performance close to the single
path system.
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