2. ADC Architectures and CMOS Circuits
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2. ADC Architectures and CMOS Circuits Class Flash Pipeline SAR Integ Delta-Sigma 2. ADC Architectures and CMOS Circuits Francesc Serra Graells francesc.serra.graells@uab.cat Departament de Microelectrònica i Sistemes Electrònics Universitat Autònoma de Barcelona paco.serra@imb-cnm.csic.es Integrated Circuits and Systems IMB-CNM(CSIC) Integrated Heterogeneous Systems Design F. Serra Graells Time-Domain 1 /59 2. ADC Architectures and CMOS Circuits Class Flash Pipeline SAR Integ Delta-Sigma Time-Domain 1 ADC Classification 2 Flash Techniques 3 Sub-Ranging, Time-Interleaving and Pipelining Techniques 4 Successive-Approximation Techniques 5 Integrating Techniques 6 Delta-Sigma Modulation Techniques 7 Time-Domain Techniques Integrated Heterogeneous Systems Design F. Serra Graells 2 /59 2. ADC Architectures and CMOS Circuits Class Flash Pipeline SAR Integ Delta-Sigma Time-Domain 1 ADC Classification 2 Flash Techniques 3 Sub-Ranging, Time-Interleaving and Pipelining Techniques 4 Successive-Approximation Techniques 5 Integrating Techniques 6 Delta-Sigma Modulation Techniques 7 Time-Domain Techniques Integrated Heterogeneous Systems Design F. Serra Graells 3 /59 2. ADC Architectures and CMOS Circuits Class Flash Pipeline SAR Integ Delta-Sigma Time-Domain ADC Families Classification based on architecture approach: Flash High speed Sub-ranging Analog signal Digital signal Parallel ADC voltage/current amplitude Interleaved Pipeline code Algorithmic SAR Integrating Digital timebase Predictive ...and many more! Distinctive characteristics: Feedforward vs feedback control Single vs multiple stages Amplitude vs time domains Delta-Sigma High dynamic range Typically mixed solutions... Integrated Heterogeneous Systems Design F. Serra Graells 4 /59 2. ADC Architectures and CMOS Circuits Class Flash Pipeline SAR Integ Delta-Sigma ADC Evolution EPSCO DATRAC, B.M. Gordon, 1953 11-bit 50KSps 500W SAR ADC 0.5m x 0.4m x 0.65m, 70Kg Vacuum tube technology W. Kester, Analog-Digital Conversion http://www.analog.com/library/analogdialogue/ archives/39-06/data_conversion_handbook.html Integrated Heterogeneous Systems Design F. Serra Graells Time-Domain 5 /59 Class 2. ADC Architectures and CMOS Circuits Flash Pipeline SAR Integ Delta-Sigma Time-Domain 6 /59 ADC Evolution +60years State-of-art ADC Solid-state technologies B. Murmann, ADC Performance Survey http://www.stanford.edu/~murmann/adcsurvey.html -6 10 -8 EPSCO DATRAC, B.M. Gordon, 1953 11-bit 50KSps 500W SAR ADC 0.5m x 0.4m x 0.65m, 70Kg Vacuum tube technology P/f s [J] 10 W. Kester, Analog-Digital Conversion http://www.analog.com/library/analogdialogue/ archives/39-06/data_conversion_handbook.html Flash Pipeline SAR Delta-Sigma Other 10fJ/conv-step -10 10 -12 10 170dB 20 30 40 50 60 70 SNDR [dB] 80 11-bit Integrated Heterogeneous Systems Design F. Serra Graells 90 100 110 2. ADC Architectures and CMOS Circuits Class Flash Pipeline SAR ADC Evolution Integ Delta-Sigma Time-Domain 7 /59 ADC Performance enhancement: Architecture strategy Circuit design Integration technology State-of-art ADC Solid-state technologies B. Murmann, ADC Performance Survey http://www.stanford.edu/~murmann/adcsurvey.html Still room for further improvement? -6 10 -8 P/f s [J] 10 Flash Pipeline SAR Delta-Sigma Other -10 10 -12 10 20 30 40 50 Integrated Heterogeneous Systems Design 60 70 SNDR [dB] 80 F. Serra Graells 90 100 110 2. ADC Architectures and CMOS Circuits Class Flash Pipeline SAR Integ Delta-Sigma Time-Domain 1 ADC Classification 2 Flash Techniques 3 Sub-Ranging, Time-Interleaving and Pipelining Techniques 4 Successive-Approximation Techniques 5 Integrating Techniques 6 Delta-Sigma Modulation Techniques 7 Time-Domain Techniques Integrated Heterogeneous Systems Design F. Serra Graells 8 /59 2. ADC Architectures and CMOS Circuits Class Flash Pipeline SAR Integ Delta-Sigma Basic Flash Architecture Building blocks: Threshold generator ADC e.g. single-ended 3-bit flash ADC Latched comparator array Time-Domain thermometer code natural binary code Digital encoder combinational only logic Integrated Heterogeneous Systems Design F. Serra Graells 9 /59 2. ADC Architectures and CMOS Circuits Class Flash Pipeline SAR Integ Delta-Sigma Basic Flash Architecture Building blocks: Threshold generator Time-Domain 10 /59 ADC e.g. single-ended 3-bit flash ADC Latched comparator array thermometer code 1 clock cycle conversion time natural binary code Digital encoder Area and power scaling by 2ENOB Distortion due to technology mismatching combinational only logic Integrated Heterogeneous Systems Design F. Serra Graells Class 2. ADC Architectures and CMOS Circuits Flash Pipeline SAR Integ Delta-Sigma Latched Comparator Design Compact CMOS circuit: clock M3 M4 Non-overlapped clock phases M1 M2 Integrated Heterogeneous Systems Design F. Serra Graells Time-Domain 11 /59 Class 2. ADC Architectures and CMOS Circuits Flash Pipeline SAR Integ Delta-Sigma Time-Domain 12 /59 Latched Comparator Design Compact CMOS circuit: M3 clock High-speed operation M4 Each comparator crosses at different threshold Vthk Non-overlapped clock phases M1 Pre-charging phase M3 Decision phase M4 0 Threshold voltage offset? M2 M4 M3 0 M1 M2 M1 M2 Integrated Heterogeneous Systems Design F. Serra Graells Positive feedback to speed-up comparison Symmetrical loading 2. ADC Architectures and CMOS Circuits Class Flash Pipeline SAR Integ Delta-Sigma Comparator Optimization By attaching an array of level shifters: single-ended version clock C1k C2k signal baseline C1k C2k C1k C2k Integrated Heterogeneous Systems Design F. Serra Graells Time-Domain 13 /59 2. ADC Architectures and CMOS Circuits Class Flash Pipeline SAR Comparator Optimization single-ended version C1k Delta-Sigma Time-Domain 14 /59 All comparators latch at the same level (Vref) By attaching an array of level shifters: clock Integ C2k Single comparator design Low quiescent power (resistor-less thresholds) Capacitor area overhead Input capacitance increased Slower operation signal baseline C1k C2k C1k C2k Integrated Heterogeneous Systems Design effective signal F. Serra Graells effective k-threshold 2. ADC Architectures and CMOS Circuits Class Flash Pipeline SAR Integ Delta-Sigma Time-Domain 15 /59 Comparator Optimization By attaching an array of level shifters: fully-differential version clock C1kp C1kn C2kp Interference rejection Full-scale extension (+6dB) SNR enhancement (+3dB) Distortion cancellation (even harmonics) C2kn Area and power overheads (x2) Higher symmetry requirements Time Integrated Heterogeneous Systems Design F. Serra Graells 2. ADC Architectures and CMOS Circuits Class Flash Comparators Offset Pipeline SAR Integ Delta-Sigma Distortion due to DNL MOSFET VTH mismatching effects: M3 M1 Time-Domain 16 /59 M4 M2 CMOS technology Pelgrom's Law Integrated Heterogeneous Systems Design F. Serra Graells 2. ADC Architectures and CMOS Circuits Class Flash Pipeline SAR Integ Delta-Sigma Time-Domain 17 /59 Comparators Offset Thermometer code bubbles! Error propagation at encoding... Bubble 0 0 1 Latched comparator array 0 Digital encoder 1 1 1 Gaussian probability distribution Large device area (WL) and input capacitance penalties Integrated Heterogeneous Systems Design F. Serra Graells 2. ADC Architectures and CMOS Circuits Class Flash Pipeline SAR Integ Delta-Sigma Time-Domain 18 /59 Comparators Offset Thermometer code bubbles! Digitally assisted analog design: Bubble 0 0 0 0 Latched comparator array 1 0 1 0 Bubble error 1 correction 1 (BEC) Digital encoder 1 1 1 1 ? Integrated Heterogeneous Systems Design F. Serra Graells 2. ADC Architectures and CMOS Circuits Class Flash Pipeline SAR Integ Delta-Sigma Time-Domain 19 /59 Comparators Offset Thermometer code bubbles! Digitally assisted analog design: Bubble 0 0 0 0 0 Bubble error 1 correction 1 (BEC) 1 Latched comparator array 0 1 1 1 1 1 (WL) large enough to limit bubble distance to 1 code: Digital encoder 0 1 (1) X X X X 0 1 Integrated Heterogeneous Systems Design 0 1 F. Serra Graells 2. ADC Architectures and CMOS Circuits Class Flash Pipeline SAR Integ Delta-Sigma Comparators Offset More on digitally assisted analog design: an stochastic flash ADC Digital inverse Gaussian integral e.g. 63 comparators Digital full-adders S. Weaver, B. Hershberg and Un-Ku Moon, Digitally Synthesized Stochastic Flash ADC Using Only Standard Digital Cells, IEEE Transactions on Circuits and Systems I, 61(1):84-91, Jan 2014 Integrated Heterogeneous Systems Design F. Serra Graells Time-Domain 20 /59 2. ADC Architectures and CMOS Circuits Class Flash Pipeline SAR Integ Delta-Sigma Time-Domain 21 /59 Comparators Offset More on digitally assisted analog design: an stochastic flash ADC Almost digital Compact area Digital inverse Gaussian integral e.g. 63 comparators Digital full-adders S. Weaver, B. Hershberg and Un-Ku Moon, Digitally Synthesized Stochastic Flash ADC Using Only Standard Digital Cells, IEEE Transactions on Circuits and Systems I, 61(1):84-91, Jan 2014 Integrated Heterogeneous Systems Design F. Serra Graells Non-linearity compensation required Power consumption 2. ADC Architectures and CMOS Circuits Class Flash Pipeline SAR Integ Delta-Sigma Time-Domain 1 ADC Classification 2 Flash Techniques 3 Sub-Ranging, Time-Interleaving and Pipelining Techniques 4 Successive-Approximation Techniques 5 Integrating Techniques 6 Delta-Sigma Modulation Techniques 7 Time-Domain Techniques Integrated Heterogeneous Systems Design F. Serra Graells 22 /59 Class Flash Pipeline SAR 2. ADC Architectures and CMOS Circuits Integ Delta-Sigma Sub-Range Flash ADC ADC Fine stage Building blocks: Flash ADC S/H ENOB/2 bit Flash DAC Flash ADC ENOB/2 bit ENOB/2 bit Coarse stage Time-Domain MSB LSB Encoder Two-step coarse-fine data conversion scheme ENOB splitting can be chosen asymmetric depending on circuits... Integrated Heterogeneous Systems Design F. Serra Graells 23 /59 Class Flash Pipeline SAR 2. ADC Architectures and CMOS Circuits Integ Delta-Sigma Time-Domain Sub-Range Flash ADC 24 /59 ADC Fine stage Building blocks: Flash ADC S/H ENOB/2 bit Flash DAC Flash ADC ENOB/2 bit ENOB/2 bit Coarse stage MSB Speed reduction (x2) Non-linearity caused by mismatching between coarse ADC-DAC, and between coarse-fine ADC LSB Encoder Two-step coarse-fine data conversion scheme ENOB splitting can be chosen asymmetric depending on circuits... Better ENOB scaling of comparators and passive components! e.g. Number of comparators for 8-bit flash ADC: single-stage two-stage Integrated Heterogeneous Systems Design F. Serra Graells Class Flash Pipeline SAR 2. ADC Architectures and CMOS Circuits Sub-Range Flash ADC Fine stage Circuit implementation: Flash ADC ENOB/2 bit Coarse stage ENOB/2 bit Flash DAC 25 /59 Non-linearity cuased by non-unitary gain in MSB substraction to coarse flash ADC C ENOB/2 bit MSBs Time-Domain Compact SC implementation: Flash ADC S/H Integ Delta-Sigma LSBs single-ended version C Encoder C coarse clock fine signal baseline from coarse flash ADC Integrated Heterogeneous Systems Design C/2 C/4 F. Serra Graells to fine flash ADC Class Flash Pipeline SAR 2. ADC Architectures and CMOS Circuits Integ Delta-Sigma Time-Domain single-ended version Time-Interleaved Flash ADC Two-step CMOS comparator: sampling + auto-zero C1 M2 M1 clock S Q M2 C1 M1 26 /59 substraction + quantization C1 M2 M1 Offset insensitive! Compact area analog inverter-based Integrated Heterogeneous Systems Design Poor power supply rejection ratio (PSRR) F. Serra Graells 2. ADC Architectures and CMOS Circuits Class Flash Pipeline SAR Integ Delta-Sigma Time-Domain Time-Interleaved Flash ADC Counter-phase two-step CMOS comparator: Offset insensitive! clock S Q Q S C1A Compact area M2A Higher speed (x2) M1A 0 1 M2B C1B M1B Integrated Heterogeneous Systems Design Poor power supply rejection ratio (PSRR) Higher jitter sensitivity (both clock edges) F. Serra Graells 27 /59 2. ADC Architectures and CMOS Circuits Class Flash Pipeline SAR Integ Delta-Sigma Time-Domain 28 /59 Time-Interleaved Flash ADC Extending the same idea to multiple time-interleaving: e.g. N=4 clock Q S Q S Q S Q S S Q S Q Q S Q S Flash ADC Flash ADC Flash ADC Flash ADC Flash ADC Flash ADC Flash ADC Flash ADC Overall equivalent high-speed conversion Each flash ADC operates at low-speed (1/N) Large area (xN) High latency (xN) Complex synchronization Integrated Heterogeneous Systems Design F. Serra Graells 2. ADC Architectures and CMOS Circuits Class Flash Pipeline SAR Integ Delta-Sigma Time-Domain 29 /59 Pipeline ADC Combination of cascaded sub-ranging and time-interleaving: Stage 1 Stage 2 p-bit MSB clock stage 1 Stage M q-bit stage 2 stage M r-bit Time Alignment Time Alignment LSB Sub-converter functions: S/H Flash ADC p-bit Flash DAC p-bit residue same i/o full-scale Sampling and hold (S/H) Sub-range quantization Residue computation and scaling Sub-converter Integrated Heterogeneous Systems Design F. Serra Graells 2. ADC Architectures and CMOS Circuits Class Flash Pipeline SAR Integ Delta-Sigma Time-Domain Pipeline ADC Combination of cascaded sub-ranging and time-interleaving: Stage 1 Stage 2 p-bit MSB clock stage 1 Stage M q-bit stage 2 stage M r-bit Time Alignment Time Alignment LSB Simpler flash sub-ADCs Performance depends on first-stage only S/H Flash ADC p-bit Flash DAC p-bit residue same i/o full-scale No speed reduction High latency (xM) Sub-converter Integrated Heterogeneous Systems Design F. Serra Graells 30 /59 2. ADC Architectures and CMOS Circuits Class Flash Pipeline SAR Integ Delta-Sigma Pipeline ADC Simple 1-bit stage case study: Stage 1 Stage 2 Time Alignment Stage M M SC implementation of each stage: single-ended version signal baseline Integrated Heterogeneous Systems Design F. Serra Graells Time-Domain 31 /59 2. ADC Architectures and CMOS Circuits Class Flash Pipeline SAR Integ Delta-Sigma Time-Domain clock Pipeline ADC Simple 1-bit stage case study: sampling + quantization (1) Stage 1 Stage 2 Time Alignment Stage M M SC implementation of each stage: single-ended version residue (>0) + scaling signal baseline Integrated Heterogeneous Systems Design F. Serra Graells 32 /59 2. ADC Architectures and CMOS Circuits Class Flash Pipeline SAR Integ Delta-Sigma Time-Domain 33 /59 Pipeline ADC Simple 1-bit stage case study: Stage 1 Stage 2 Time Alignment Stage M M SC implementation of each stage: single-ended version Simplest flash sub-ADCs Inherently linear single bit quantization Noise contributions from stage 2 → multi-bit first stage signal baseline Offset sensitivity Integrated Heterogeneous Systems Design F. Serra Graells 2. ADC Architectures and CMOS Circuits Class Flash Pipeline SAR Integ Delta-Sigma Time-Domain 1 ADC Classification 2 Flash Techniques 3 Sub-Ranging, Time-Interleaving and Pipelining Techniques 4 Successive-Approximation Techniques 5 Integrating Techniques 6 Delta-Sigma Modulation Techniques 7 Time-Domain Techniques Integrated Heterogeneous Systems Design F. Serra Graells 34 /59 2. ADC Architectures and CMOS Circuits Class Flash Pipeline SAR Integ Delta-Sigma Successive Approximation ADC ADC Building blocks: residue digital state-machine (algorithm) S/H Successive Approximation Register (SAR) approximation Flash DAC N N-bit Integrated Heterogeneous Systems Design Time-Domain F. Serra Graells 35 /59 2. ADC Architectures and CMOS Circuits Class Flash Pipeline SAR Integ Delta-Sigma Time-Domain Successive Approximation ADC ADC Building blocks: residue e.g. 4-bit SAR ADC digital state-machine (algorithm) S/H Successive Approximation Register (SAR) approximation Flash DAC time N N-bit MSB LSB time Analog minimalist Speed requirements (xN) Very low-power consumption Performance limited by flash DAC Integrated Heterogeneous Systems Design F. Serra Graells 36 /59 2. ADC Architectures and CMOS Circuits Class Flash Pipeline SAR Integ Delta-Sigma Time-Domain 37 /59 Successive Approximation ADC Circuit implementation: clock S/H Successive Approximation Register (SAR) Flash DAC single-ended version N N-bit to SAR signal baseline from SAR Integrated Heterogeneous Systems Design F. Serra Graells 2. ADC Architectures and CMOS Circuits Class Flash Pipeline SAR Integ Delta-Sigma Time-Domain 38 /59 Successive Approximation ADC Circuit implementation: clock S/H Successive Approximation Register (SAR) Flash DAC single-ended version N N-bit to SAR signal baseline Integrated Heterogeneous Systems Design F. Serra Graells 2. ADC Architectures and CMOS Circuits Class Flash Pipeline SAR Integ Delta-Sigma Time-Domain 39 /59 Successive Approximation ADC Circuit implementation: clock S/H Successive Approximation Register (SAR) Flash DAC single-ended version N N-bit to SAR signal baseline Integrated Heterogeneous Systems Design F. Serra Graells 2. ADC Architectures and CMOS Circuits Class Flash Pipeline SAR Integ Delta-Sigma Time-Domain 40 /59 Successive Approximation ADC Circuit implementation: clock S/H Successive Approximation Register (SAR) Flash DAC single-ended version N N-bit to SAR signal baseline from SAR Integrated Heterogeneous Systems Design F. Serra Graells 2. ADC Architectures and CMOS Circuits Class Flash Pipeline SAR Integ Delta-Sigma Time-Domain 41 /59 Successive Approximation ADC Circuit implementation: clock S/H Successive Approximation Register (SAR) Flash DAC single-ended version N N-bit to SAR signal baseline from SAR Integrated Heterogeneous Systems Design F. Serra Graells 2. ADC Architectures and CMOS Circuits Class Flash Pipeline SAR Integ Delta-Sigma Time-Domain 1 ADC Classification 2 Flash Techniques 3 Sub-Ranging, Time-Interleaving and Pipelining Techniques 4 Successive-Approximation Techniques 5 Integrating Techniques 6 Delta-Sigma Modulation Techniques 7 Time-Domain Techniques Integrated Heterogeneous Systems Design F. Serra Graells 42 /59 2. ADC Architectures and CMOS Circuits Class Flash Pipeline SAR Integ Delta-Sigma Single-Slope ADC Time-Domain 43 /59 ADC Building blocks: S/H reset enable Digital counter N pulse-width modulation (PWM) clock 0 Integrated Heterogeneous Systems Design time F. Serra Graells 2. ADC Architectures and CMOS Circuits Class Flash Pipeline SAR Integ Delta-Sigma Single-Slope ADC Time-Domain 44 /59 ADC Building blocks: S/H reset enable Digital counter N pulse-width modulation (PWM) clock Analog minimalist Very low-power Speed requirements (x2N) Technological sensitivity (RC) Integrated Heterogeneous Systems Design 0 time F. Serra Graells 2. ADC Architectures and CMOS Circuits Class Flash Pipeline SAR Integ Delta-Sigma Dual-Slope ADC Time-Domain 45 /59 ADC Building blocks: S/H reset control Dual counter N clock Analog minimalist Very low-power Speed requirements (x2N) Technology independence (RC) Integrated Heterogeneous Systems Design 0 time F. Serra Graells 2. ADC Architectures and CMOS Circuits Class Flash Pipeline SAR Integ Delta-Sigma Integrate-and-Fire ADC Time-Domain 46 /59 ADC Building blocks: Asynchronous counter reset N pulse-density modulation (PDM) Current-mode sensors (e.g. imagers) Very low-power Speed requirements adapted to signal Technology sensitivity (C) Integrated Heterogeneous Systems Design 0 time F. Serra Graells 2. ADC Architectures and CMOS Circuits Class Flash Pipeline SAR Integ Delta-Sigma Time-Domain 1 ADC Classification 2 Flash Techniques 3 Sub-Ranging, Time-Interleaving and Pipelining Techniques 4 Successive-Approximation Techniques 5 Integrating Techniques 6 Delta-Sigma Modulation Techniques 7 Time-Domain Techniques Integrated Heterogeneous Systems Design F. Serra Graells 47 /59 2. ADC Architectures and CMOS Circuits Class Flash Pipeline SAR Integ Delta-Sigma Delta-Sigma Modulator ADC ADC General single-loop DSM architecture: noise-shaper DSM (predictor) digital output quantizer error Flash ADC S/H Flash DAC prediction Time-Domain digital decimator (down sampler) feedback DAC Integrated Heterogeneous Systems Design F. Serra Graells 48 /59 2. ADC Architectures and CMOS Circuits Class Flash Pipeline SAR Integ Delta-Sigma Delta-Sigma Modulator ADC Time-Domain 49 /59 ADC General single-loop DSM architecture: noise-shaper DSM (predictor) digital output quantizer error Flash ADC S/H In-band high-gain digital decimator (down sampler) Flash DAC prediction DSM signal vs quantization noise behavior? Noise-shaper filter: feedback DAC Either continuous- H(s) or discrete-time H(z) Flash ADC and DAC blocks can be relaxed! quantization noise signal output Integrated Heterogeneous Systems Design F. Serra Graells 2. ADC Architectures and CMOS Circuits Class Flash Pipeline SAR Integ Delta-Sigma Time-Domain Delta-Sigma Noise Shaping Simplest architecture: first-order (N=1) 1-bit (B=1) single-loop DSM integrator comparator S/H Single-bit feedback DAC is intrinsically linear time Integrated Heterogeneous Systems Design F. Serra Graells 50 /59 2. ADC Architectures and CMOS Circuits Class Flash Pipeline SAR Integ Delta-Sigma Time-Domain Delta-Sigma Noise Shaping Simplest architecture: first-order (N=1) 1-bit (B=1) single-loop DSM integrator comparator Single-bit feedback DAC is intrinsically linear S/H Oversampling is needed log(power) all-pass (delay) out-band noise signal 20dB/dec (differentiator) high-pass shaping Integrated Heterogeneous Systems Design log(frequency) F. Serra Graells 51 /59 2. ADC Architectures and CMOS Circuits Class Flash Pipeline SAR Integ Delta-Sigma Time-Domain 52 /59 Delta-Sigma Noise Shaping Simplest architecture: first-order (N=1) 1-bit (B=1) single-loop DSM integrator comparator Single-bit feedback DAC is intrinsically linear S/H Oversampling is needed Higher order (N>1) shaping to avoid signal to quantization noise correlation (harmonics) log(power) all-pass (delay) signal in-band harmonics (differentiator) high-pass shaping Integrated Heterogeneous Systems Design log(frequency) F. Serra Graells 2. ADC Architectures and CMOS Circuits Class Flash Pipeline SAR Integ Delta-Sigma Time-Domain 53 /59 Delta-Sigma Noise Shaping Higher-order (N) noise shaping: first integrator second integrator S/H gain coefficients Sharper noise shaping Signal to quantization noise uncorrelation (continuous spectra) log(power) 40dB/dec Possibility of loop instability for N>2 Coefficients optimization! log(frequency) Integrated Heterogeneous Systems Design F. Serra Graells 2. ADC Architectures and CMOS Circuits Class Flash Pipeline SAR Integ Delta-Sigma Time-Domain 54 /59 DSM ADC Design Multi-bit quantization: N-order B-bit single loop architecture: Resolution added to overall DR multi-bit (B) quantization Internal full-scale reduction Feedback DAC not intrinsically linear S/H High-order filtering: Sharper noise shaping Stability issues Ideal dynamic range: log(power) shaping order oversampling only signal (N+0.5)-bit/oct(OSR) 20N dB/dec 6N dB/oct direct improvement log(frequency) Integrated Heterogeneous Systems Design F. Serra Graells 2. ADC Architectures and CMOS Circuits Class Flash Pipeline SAR Integ Delta-Sigma Time-Domain 55 /59 DSM ADC Design Feedfoward cancellation: Internal full scale low occupancy Additional adder stage in front of quantizer S/H Resonator attenuation: Extra noise shaping at band edge Zero sensitivity to coefficient matching log(power) S/H log(frequency) Integrated Heterogeneous Systems Design F. Serra Graells 2. ADC Architectures and CMOS Circuits Class Flash Pipeline SAR DSM SC Circuits Integ Delta-Sigma clock S X Fully-differential 2nd-order single-bit example: input sampler reuse for DAC feedback common mode integrator initialization Integrated Heterogeneous Systems Design passive adder F. Serra Graells Time-Domain 56 /59 2. ADC Architectures and CMOS Circuits Class Flash Pipeline SAR Integ Delta-Sigma Time-Domain 1 ADC Classification 2 Flash Techniques 3 Sub-Ranging, Time-Interleaving and Pipelining Techniques 4 Successive-Approximation Techniques 5 Integrating Techniques 6 Delta-Sigma Modulation Techniques 7 Time-Domain Techniques Integrated Heterogeneous Systems Design F. Serra Graells 57 /59 2. ADC Architectures and CMOS Circuits Class Flash Pipeline SAR Integ Delta-Sigma Voltage-to-Frequency ADC Time-Domain ADC voltage-controlled oscillator (VCO) Building blocks: 1 Coarse counter reset S/H MSB Fine register 0 1 1 xor detection 0 Integrated Heterogeneous Systems Design Encoder LSB S F. Serra Graells N Q 58 /59 2. ADC Architectures and CMOS Circuits Class Flash Pipeline SAR Integ Delta-Sigma Voltage-to-Frequency ADC Time-Domain ADC voltage-controlled oscillator (VCO) Building blocks: Coarse counter reset S/H MSB Fine register Encoder All-MOS circuit implementation Non-linearity Vin-Ibias and Ibias-fVCO Low-voltage operation Technology sensitivity Integrated Heterogeneous Systems Design LSB S F. Serra Graells N Q 59 /59
