LC VCO Design
Procedure
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UMTS VCO
VCO design parameters
Design requirement
Oscillating frequency
Tuning range
Voltage swing
Phase noise
Supply voltage
Power consumption
2.1GHz
400MHz
0.7V
-110dBc@1MHz
3V
10mW
Technology parameters
Values
Technology
Number of metals
Transit frequency
MIM capacitors
Varactors
BiCMOS
4
50GHz
available
available
WCDMA Specs
Receiving Band (GHz)
Channel Spacing (MHz)
Multiplex / Modulation
MDSeff (dBm)
SNR (dB) / BER
Processing Gain (dB)
Tx-Rx Isolation (dB)
Blocker @ 8MHz (dB)
Value
2.11-2.17
5 (3.84)
FDD / QPSK
-99
7 / 1E-3
25
50
-46
L (8MHz)=-99-(-46)-10log(3.84e6)-7=-129dBc/Hz
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Series vs. Parallel Resonator
• frequency f0=2.1GHz
• desired signal power P=10mW
RS
L
C
QL=20
RTK
C
L
• L=3nH, C=1.9pF, RS=2Ω
• L=3nH, C=1.9pF, RTK=800Ω
• fundamental current and voltage
i=100mA, v=0.2V
• fundamental current and voltage
i=5mA, v=4V
• very large current
• moderate current and voltage
• realistic choice
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Negative Resistance Oscillator
ω0 =
V CC
C
V
L, RL
CV
1
LC
C = CV / 2
UT
−gm / 2
Q1
resonating LC tank
active part
Q2
IC =
I TAIL
QCS
IT
2
biasing current source
QCS
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LC Tank Design
• oscillation frequency
f0 =
1
C = CV / 2
2π LC
• determine L and C
• tuning range
f MAX
=
f MIN
CV ,MAX
CV ,MIN
CV ,MAX
C PAR
+2
CV ,MIN
CV ,MIN
C
1 + 2 PAR
CV ,MIN
⎛ f MAX
= ⎜⎜
⎝ f MIN
• parasitics impose larger
capacitive tuning range
2
⎡⎛ f
⎞
⎟ + 2⎢⎜ MAX
⎟
⎜ f
⎢
⎠
⎣⎝ MIN
2
⎤ C
⎞
⎟ − 1⎥ PAR • determine CMAX and CMIN
⎟
⎥ CV ,MIN
⎠
⎦
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How to Choose L?
• tank conductance
GTK
• phase noise
1 ⎛ 1
1 ⎞
⎜
⎟
=
+
⎜
ω 0 L ⎝ QL QC ⎟⎠
L( Δω ) ≅
• choice of L
• larger L => larger QL
R L + 2 RC
⎛ ω0 ⎞
⋅ F⎜
KT
⎟
2
VS
⎝ Δω ⎠
2
• larger L => larger RL
• larger L => lower GTK
• larger L => poorer
L
• larger L => lower power consumption
• larger L => lower fRES, fQ-PEAK
• larger L => lower tuning range
• choose for the largest L having peak Q close to the
operating frequency
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How to Choose C?
• phase noise
• tank conductance
GTK
RL
2
=
+
2
R
(
ω
C
)
C
0
( ω 0 L )2
L( Δω ) ≅
R L + 2 RC
⎛ ω0 ⎞
⋅ F⎜
KT
⎟
2
VS
⎝ Δω ⎠
2
• choice of C
• larger C => lower Q
• larger C => larger GTK
• larger C => lower RC
• larger C => slightly better
L
• larger C => larger power consumption
• larger C => larger tuning range
• choose for C providing not more than the required
frequency tuning range
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Active Part Design
• chosen LC tank parameters determine losses to
be compensated
GTK =
RL
2
+
2
R
(
ω
C
)
C
0
( ω 0 L )2
• cross-coupled pair conductance
gM = gm / 2
• oscillation condition gM>GTK determines the very
minimum compensating active-devices current
⎞
⎛ RL
2
⎜
I C = g mVT > 2GTK VT = 2⎜
+ 2 RC ( ω 0C ) ⎟⎟VT
2
⎠
⎝ ( ω0 L )
• choose for the transistors having enough fT (~10f0) for
the determined collector current
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What About Phase Noise?
• there is nothing better than the best LC-tank
• the best LC tank chosen determines power
consumption and accordingly active devices
operating current
• shot noise is directly determined by operating
current, i.e., LC tank
• the larger the transistor the lower the base
resistance thermal noise (but more parasitics)
• choose for as large transistors as possible having
enough fT (~10f0) for the determined collector current
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Tail Current Source
• Tail current noise around even multiples of the oscillating
frequency is transformed into the phase noise of the VCO
• Tail current noise contribution larger than all other
contributions together
• Reducing the output noise power of the current source, its
contribution to the phase noise is reduced as well
• emitter degeneration reduces the tailcurrent source noise transfer functions
• resistive degeneration effective at all
frequencies but requires voltage headroom
• inductive degeneration effective in narrow
frequency band but requires no voltage
headroom
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I CS, RID
VB,CS
QCS
IB,CS
IC,CS
ZD
125
So Far
VCO design parameters
Design requirement
Oscillating frequency
Tuning range
Voltage swing
Phase noise
Supply voltage
Power consumption
2.1GHz
400MHz
0.7V
-110dBc@1MHz
3V
10mW
Technology parameters
Values
Technology
Number of metals
Transit frequency
MIM capacitors
Varactors
BiCMOS
4
50GHz
available
available
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Simulations/
Layout/
Measurements
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Design Procedure
• Calculations
• estimation of design parameters
• Simulations
• Layout
• Measurements
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Simulations
• Simulation with estimated idealized components
• adjustment of estimated design parameters
• Simulation with components’ models provided by
technology
• adjustment of estimated design parameters
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Layout
• Layout design
• Layout extraction
• Postlayout simulation
• adjustment of circuit and layout parameters
• Layout verification
• design rules check
• layout versus schematic check
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Measurements (Design Verification)
• Chip packaging
• Printed Circuit Board design
• Measurement setup
• Simulation of measurement setup
• IC-package-PCB
• Interpretation of measured results
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VCO Design
Example Simulations
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Idealized VCO Schematic
VCC
L
CV
CV
• L=3nH, QL=25, CV0=3.8pF
UT
• CA=150fF, CB=600fF
CB
Q1
CA
CB
RB
RB
VB
ITAIL
Q2
• collector current (0.2mA, 3mA)
• transistor dimensions 0.5x10um2
CA
• tail current (0.4mA, 6mA)
QCS
QCS
LRID
LRID
• TCS transistor dimensions 0.5x20um2
• LRID=3.4nH
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VCO Schematic with Inductor Model
VCC
CL
L /2
CL
R L /2
C OX
C
R
SUB
SUB
CV
RC
R L /2
L/2
C
SUB
C OX
R
SUB
• L=3nH
• n=3, w=20um
CV
RC
UT
• dOUT=320um, s=5um
CB
Q1
CA
CB
RB
RB
VB
Q2
CA
• LRID=3.4nH
• n=6, w=7um
ITAIL
QCS
QCS
LRID
• dOUT=120um, s=1um
LRID
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VCO Design
Example Layout
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Layouting
• Components placement and routing
• Chip padding
• Isolation
• guard rings
• Protection
• Electrostatic Discharge (ESD)
• Substrate contacts, metal distribution
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VCO Layout – Top View
bond
pad
LRID
-gM
C
L
LRID
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Placement
• Generation of component layouts
• Component Separation
• sensitive I/O nodes (RF/LO)
• sensitive circuits (power amplifiers/oscillator)
• sensitive sub-systems (analog/digital)
• Component coupling
• substrate, interconnects, bondwires
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Routing
• Track width/length
• thick(wide)/long/top
• thin(narrow)/short/bottom
• Current density
• wide ground/supply lines
• Bottom metal component interconnect
• Top metal circuit/system interconnect
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Padding
• IC interface
• inputs/outputs – information signal lines
• bias lines – supply, ground
• Area increase
• size 100x100um2
• distance 100um
• ESD for sensitive nodes
• HF circuit performance degradation
• capacitance added
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Design Rules (Layout Verification)
•
•
•
•
•
•
•
Component size (width/length)
Component spacing
Track width
Track spacing
Metal density
Geometry
Grid
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Design Rule Compliant VCO Layout
• Design Rule Check (DRC)
• Comparison of layout and schematic (LVS)
• Generation of output file for fabrication (GDSII)
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VCO Design
Example Measurements
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Chip and Measurement Equipment Interface
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Verification Procedure
• Oscillator chip packaging
• Oscillator IC Printed Circuit Board design
• Measurement setup
• Interpretation of the results
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VCO Chip Microphotograph
LRID
-gM
C
L
LRID
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Packaged VCO IC
VCO chip
bondwire
bondpad
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Packaged VCO IC on PCB
SMD transformer
SMD resistor
VCO IC
package
bias choke
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SMD inductor
SMD capacitor
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Measurement Fixture
I/O
connectors
transformer
bias filtering
VCO IC
bias filtering
package
PCB
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Package and PCB Effects
• Measured vs. simulated
• Include into simulations
• bondwire inductance
• package lead inductance
• contact capacitances
• SMD components on PCB
• transmission lines on PCB
toPCB
CPCB
LBW
LPKG
CPKG
toVCO
CBPAD
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Measurement System
VCC-XF
Spectrum
analyzer
VVCO
+
+
VCC
+
+
LO
test
fixture
+
UTUNE
IBUFFER
VVCO
ITAIL
VCC
IBUFFER
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Measured Signal Spectrum
signal power
signal frequency
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Measured Frequency Tuning Range
• fLOW=1.8GHz
• fUP=2.4GHz
• Δf=600MHz
• VTUNE=3V
2,5
Oscillating frequency [GHz]
2,4
VCC=3V
2,3
2,2
2,1
2
1,9
1,8
1,7
0
0,5
1
1,5
2
2,5
3
Tuning voltage VT [V]
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Measured Phase Noise
PN(1MHz)=-110dBc@3mW
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Measured VCO Performance
VCO design parameters
Measurement Results
Central frequency
2.1GHz
Tuning range
600MHz
Voltage swing
0.7V
Phase noise
-110dBc@1MHz
Supply voltage
3V
Power consumption
3mW
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Conclusions
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So far
• Oscillator classification
• Oscillation condition – frequency, amplitude
• Oscillator phase noise
• UMTS oscillator design – estimation,
simulation, layout, measurements
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Job Offer
• RF/analog circuits design experience
• oscillators
• CAD design
• Cadence, ADS
• Measurements and PCB design
• Salary 60.000
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