IEEE TRANSCATIONS ON CIRCUITS AND SYSTEM – II: EXPRESS BRIEF
1
Thermal Compensation Method for CMOS
Digital Integrated Circuits Using TemperatureAdaptive DC-DC Converter
Dongsheng Ma, Member, IEEE and Chuang Zhang, Member, IEEE
Abstract—A cost-effective thermal compensation technique for
CMOS digital integrated circuits (ICs) is proposed. The
technique features a temperature-adaptive DC-DC converter,
serving as both temperature detector and variable power supply.
The converter adopts a delay-line based analog-to-digital (A/D)
converter to translate temperature information into digital
signals. By adjusting the output voltage, the DC-DC converter
can help stabilize ICs’ operating frequency. The system was
fabricated with a standard 1.5µm digital CMOS process. With a
supply of 3.3V, the converter is capable of providing a variable
supply voltage of 1.1 to 2.0V, with a maximum power efficiency
of 92.1%. With this thermal compensation technique,
temperature sensitivity of ICs is reduced from 4046 to 74ppm/°C
within a temperature range of 0 to 110°C.
Index Terms—thermal compensation, digital CMOS IC, adaptive
DC-DC converter
I. INTRODUCTION
C
URRENT CMOS IC design dominates digital IC market
due to its low power and low cost. However, MOS
transistor shows strong temperature dependence since
both electrical mobility (µ) and threshold voltage (VT) are
temperature-related [1]. This results in temperature variations
in drain-to-source current (Ids) and thus propagation delay of
logic gates. For example, in a typical CMOS ring oscillator, as
the temperature varies, the oscillation frequency drifts
accordingly, making the problems of jitter and phase noise [2].
Serious cases cause signal processing errors and even failure
of operation. In terms of reliability, large temperature
variation at “hot spots” can cause fatal damages on silicon
chips. Hence, effective thermal compensation and power
management are strongly demanded in VLSI systems.
In recent years, several on-chip thermal compensation
methods have been reported. In [3, 4], temperature variation is
measured by a temperature-sensitive resistor, and then
digitized by a high precise A/D converter. Thermal effect is
compensated by adjusting temperature coefficients stored in
memory circuits. Finally, a D/A converter changes error
correction information into analog voltage/current signals for
temperature compensation. In [5], a delay-locked loop (DLL)
is proposed, consisting of charge pump, phase detector, clock
synthesizer and one tunable VCO. The VCO incorporates a
series of current mirror circuits and trimming resistors for
frequency tuning. Power consumption by synthesizer itself has
been above 57mW. The designs require complex analog
circuit blocks such as A/D converters, with large power
dissipation and chip area.
In this paper, a cost-effective thermal compensation method
for CMOS digital ICs is proposed [6]. First, a delay-line based
digital A/D converter was employed as temperature detector.
Variations of operating frequency due to temperature and
process variations is minimized by adaptively adjusting the
power supply of digital circuits, which is implemented by an
adaptive-output DC-DC converter. The converter also controls
power flows in the entire IC and helps maintain the
temperature at desired level, which was not discussed in
aforementioned prior arts. The rest of this paper is organized
as follows. Section II depicts the design and operation of the
proposed thermal compensation system. Experimental results
are addressed in Section III to verify the design validity and to
evaluate the performance. We then conclude our design efforts
in Section IV.
II. DESIGN OF THERMAL COMPENSATION SYSTEM
A. System Architecture
Vout
Mp
L
Vg
Cout
Mn
Power Stage
Buffer Drive
Power Flow Controller
Load Power Meter
Pulse-Width Generator
Current Sensing Circuit
Vdelay
Digital Logic for
Error Signal Computation
Clk
Delay Cell N
Manuscript received April, 2005. This work was supported in part by U.S.
National Science Foundation Center for Low Power Electronics.
D. Ma is with Electrical and Computer Engineering Department, the
University of Arizona, Tucson, AZ 85721, USA, (Tel: 520-621-8733, Fax:
520-621-8076, e-mail: ma@ece.arizona.edu).
C. Zhang is with Micron Technology Texas, LLC, Allen, TX 75013 USA,
(e-mail: czhang@yahoo.com).
CMOS Digital ICs
Temperature Detection & Compensation
Delay Cell 2
Delay Cell 1
Fig. 1 Block diagram of proposed thermal compensation system
Fig. 1 shows the block diagram of the proposed thermal
compensation system, including a power stage, a power flow
IEEE TRANSCATIONS ON CIRCUITS AND SYSTEM – II: EXPRESS BRIEF
controller and a temperature detection and compensation unit.
The power stage of the DC-DC converter adopts conventional
buck topology to convert an external power source of 3.3V
into a variable power supply. Synchronous rectification is
implemented for low power and high efficiency. The stage is
regulated by a power flow controller including a load power
sensor, a current sensing circuit and a pulse-frequency
modulation (PFM) generator.
2
t total = 2 Nt
N
Power PMOS
Sensing PMOS
−
M5
inductor current iL
M6
)2
,
(1)
3
(2)
VT (T ) = VT (T0 ) − α (T − T0 ),
Vcon
(from buffer drive)
M3
2 NKV out
µ (V out − V T
µ = K µT 2 ,
1
M4
=
where td is the delay of each inverter stage, VT is threshold
voltage, K is a constant parameter for a given MOSFET and µ
is equivalent mobility of MOSFET. Here, the mobility µ and
threshold voltage VT are temperature dependent [9, 10], which
can be approximated by the expressions (2) and (3),
respectively.
Vdd
ibias
d
(3)
where α is temperature coefficient, determined by the
substrate doping level and the implant dose during the
fabrication. In this design, α is approximately 3.2mV/°C. By
combing (1), (2) and (3), we have
3
M1
Mbias
M2
ttotal
sensing current isense
By taking ∂ttotal
∂T
Fig. 2 Schematic of on-chip current sensing circuit
The load power sensor is to monitor instant power demand
from the load (digital IC). As the load varies, the duty ratio of
the converter varies accordingly to maintain the output voltage
at the desired level. Current sensing circuit used here is an
improved version of [7, 8], mainly performing on-chip current
sensing and over-current protection. The details of the circuit
are illustrated in Fig. 2. Instead of employing traditional series
sensing resistor to detect the inductor current (iL), on-line
transistor current scaling technique is applied. The transistors
M1∼M4 form a voltage mirror to bias the sensing PMOS and
power PMOS transistor with the same DC conditions. The
current flowing through the sensing transistor is thus linearly
proportional to the inductor current. Because the ratio of the
two transistors N (= (W L )Power (W L )sen sin g ) is very large, (N
is 2000 in this design), the current sensing circuit thus
consumes much less power than the power stage.
Temperature detection circuit consists of digital delay line
and signal processing circuits. Note that the delay line is
powered by the output of the DC-DC converter, Vout. Hence,
its delay time can be adjusted by adjusting the level of Vout.
Since the delay line circuit converts analog voltage Vout into
the delay of digital circuits, it is also named as delay-line
based A/D converter. Compared to traditional A/D converters,
this circuit can be simply implemented with digital delay
elements. Its operation will be discussed in Section II-B.
Clearly, by transforming voltage signals into delay/frequency
signals, this design requires much less silicon area than its
analog counterparts with larger noise margins.
B. Mechanism of Temperature Compensation
Suppose that the delay line in Fig. 1 embraces 2N stages of
inverters. Its delay time ttotal can be expressed as,
=0
Vout T 2
2 NK
=
K µ (Vout − αT − VT (T0 ) + αT0 )2
(4)
, we have
3
VoutT 2
∂ttotal
∂ 2 NK
|T =To =
(
) |T =To = 0. (5)
∂T
∂T K µ (Vout − αT − VT (T0 ) + αT0 )2
4
(6)
Vdd _ opt = αTo + VTo .
3
Here, Vdd_opt is the boundary supply voltage, at which the
delay of the circuit is temperature-independent. Eqn. (4)
shows that, to keep the delay ttotal constant, we can always find
a level for Vout to compensate the temperature variation.
1
Clk
0
1
Vdelay (1)
0
1
ttotal (1)
0
1
Error (1)
0
1
Vdelay (2)
0
1
ttotal (2)
0
1
Error (2)
0
1
Vdelay (3)
0
1
ttotal (3)
0
1
Error (3)
0
Fig. 3 Timing diagram of temperature compensation in three cases:
(1) when the temperature is constant; (2) when the temperature is
above the desired level; and (3) when the temperature is below the
desired level.
According to Eqn. 6, Vdd_opt is determined by the fabrication
process. If the actual supply voltage Vdd is higher than it, the
delay of the circuit exhibits positive temperature dependence.
IEEE TRANSCATIONS ON CIRCUITS AND SYSTEM – II: EXPRESS BRIEF
Otherwise, negative temperature dependence is observed. In
this design, Vdd_opt is about 2.15V, and the desired supply
voltage range for the loading circuits is from 1.1 to 2V. Thus,
the delay of the circuits is negative temperature-dependent.
To illustrate the mechanism of temperature compensation,
Fig. 3 shows the timing diagram of temperature detection and
compensation circuit under different temperature conditions.
A temperature-independent reference clock ‘Clk’ (in Fig. 1) is
applied at the input of the delay line. After a delay time of ttotal,
the clock signal can be found at the output of the delay line.
We name this signal as Vdelay to differentiate it from Clk.
Obviously, ttotal follows Eqn. (4), which can be measured at the
output of the phase detector in Fig. 4.
Vdelay
Phase Detector
Clk
Clk_H
Error
Frequency Counter
Qm
Qm-1
Qm-2
Q1
3
Ron, Mp
C. Adaptive DC-DC Conversion with Dynamic Power Loss
(DPL) Control
ESRL
Vout
(0, DT)
ESRC
Vg
Io
C
(a)
L
ESRL
Vout
ESRC
Ron, Mn
(DT, T)
Vg
Io
C
(b)
Fig. 5 Equivalent circuit of the power stage: (a) when Mp is on, and
(b) when Mn is on.
In a DC-DC converter, power dissipation of power
transistors and the parasitics in the power stage dominates the
entire efficiency. One major power loss, conduction power
loss, can be calculated based the two different modes shown in
Fig. 5. The conduction loss is approximately equal to
Fig. 4 Schematic of error signal generation
To quantize the delay, the signal ttotal is modulated by a highfrequency clock signal Clk_H. As a result, the delay
information is represented by m-bit binary data “QmQm-1...Q1”.
If the temperature is stable, the measured delay should be a
constant value as described in case (1) of Fig. 3. Here, the
delay data is set to be “10000000” (m=8).
If temperature rises, the delay ttotal decreases as in case (2) of
Fig. 3. As a result, Qm…Q1 decreases. For instance, a
“01111110” is detected by the frequency counter. The change
of this binary data reflects the temperature variation. Error
computation logic (Fig. 1) then sends the error information to
PFM generator to reduce the duty ratio of the DC-DC
converter. As results, less current will pass through the
inductor L to the output of the converter. The output voltage
Vout across the capacitor Cout then drops. Hence, the circuits
including the load and the delay line are powered with a
reduced supply voltage. The delay of the circuits returns to the
original level. The circuit’s operating frequency is thus
stabilized. In addition, because the power loss of digital
circuits is proportional to Vdd2, the reduced Vdd leads to less
power loss and thus less heat, helping decrease temperature.
If temperature drops, the delay ttotal increases accordingly.
The delay data thus increases as in case (3) of Fig. 3. For
instance, a “10000011” may be detected at Qm…Q1.
Accordingly, the converter’s duty ratio will be increased.
Hence, more current will be delivered, and the output voltage
Vout increases. Then, the circuits are powered with an
increased supply voltage and the delay of the circuits returns
to the original. Again, the increased Vdd leads to more power
loss and helps raise the temperature until the system reaches
the equilibrium.
L
PCond ≈
(DI o )2
µ p C ox (W L ) p (V g
(1 − D ) 2 I o
µ n C ox (W L )n (V g − VTn )
2
− VTp )
+
(7)
+ I o ESR L + ∆iC ESRC
2
2
Here, D is the duty ratio, Io is the output load current, ESRL
and ESRC are equivalent series resistance of the inductor L
and capacitor C, respectively. ∆iC is the averaged dynamic
current of the capacitor C. The switching power loss is
(8)
PSW ≈ C ox ((WL ) p + (WL )n ) f S ,
where fS is the switching frequency of the converter. We
ignore the power loss of short-circuit current and static power
since they are usually much smaller and can be minimized
through careful circuit design and layout [11, 12]. Hence the
overall power loss in power stage is approximately equal to
Ptotal ≈ PCond + PSW .
(9)
By taking ∂Ptotal ∂W p = 0 and ∂Ptotal ∂Wn = 0 , we can find the
optimal size of the power transistors Mp and Mn.
Vdd
M4
M5
Hysteretic
Comparator
M6
isense
Vcon
f(iL)
Counter
M7
M1
M3
M2
Multiplier &
Multiplexer
C
Temperature
Detection
Circuit
G2
G1
G0
f(vo)
Fig. 6 Schematic of power meter
However, the power minimization technique above only
works well for a converter with fixed load and output voltage
level. Since the output voltage and current in this converter are
both variable, the technique does not suffice. We thus propose
dynamic power loss control with an on-chip power meter to
achieve dynamic power transistor sizing. The power meter
IEEE TRANSCATIONS ON CIRCUITS AND SYSTEM – II: EXPRESS BRIEF
includes voltage and current meters and a digital
multiplication circuit as shown in Fig. 6. As discussed in
Section II-B, since the thermal compensation circuit can
obtain the output voltage information, we only need to
measure the current information at this moment. For the buck
converter, the averaged inductor current is equal to the load
current. The inductor current can be detected from the sensing
current isense (=iL/N) in Fig. 2, and then copied by a current
mirror in Fig. 6. Here, Vcon is the gate voltage on power
transistor Mp in Fig. 2. When Mp is on, the inductor current is
scaled and copied into M5 and M6 to charge up the capacitor
Cm. When the voltage across Cm reaches a threshold voltage
VH, the hysteretic comparator’s output flips. Obviously, the
larger the inductor current, the faster Cm is charged up, leading
to a larger number at the counter output. A digital multiplier
then multiplies the detected current and voltage for power
information.
4
III. EXPERIMENTAL RESULTS
The proposed design was fabricated with a standard 1.5µm
digital CMOS process. Fig. 8 shows the chip micrograph. Due
to the compactness of the delay-line based digital controller,
the active area is about 0.95mm2.
The values of inductor and filtering capacitor in DC-DC
converter are 4.7µH and 10µF, respectively. With an input
voltage of 3.3V, the measured peak-to-peak output voltage
ripple is less than 36mV. Fig. 9 shows the measured steadystate output voltage at 1.25V with reference to the inductor
current. Efficiency of the DC-DC converter is measured and
plotted in Fig. 10. Due to the proposed dynamic power loss
control technique, the efficiency can be maintained above 70%
over the entire output power range of 10 to 280mW, with a
maximum efficiency of 92.1% at 125mW.
Mn
Vcon (from Pulse-Width Generator)
buffer
Mn7
Mn2
Mn1
G0G1G2
G0+G1+G2
buffer
buffer
Fig. 7 Power transistor with DPL control
Fig. 9 Output of DC-DC converter with reference to the inductor
current
100
95
90
85
Efficiency (%)
The load power is divided into 8 levels according to its
magnitude. The ‘sensed’ power is then compared to these predetermined levels and is represented by a 3-bit digital signal
G2G1G0. Finally, the signal is applied to buffer drive to
determine how many power transistors should be turned on in
Fig. 7. If the converter is with full load, larger power transistor
is preferred to reduce the conduction power loss PCond. “111”
will be assigned to G2G1G0 to turn on all the transistors from
Mn1 to Mn7. When the converter only drives a very light load,
some transistors should be shut down to reduce the switching
loss PSW. “000” will be given to only allow Mn1 to be on. The
same scheme is also applied to power PMOS transistor.
Accordingly, efficiency of the converter is optimized at 8
levels instead of one.
80
75
70
65
60
55
50
0
50
100
150
200
250
300
Load Power (mW)
Fig. 10 Measured efficiency of the converter
Fig. 8 Chip micrograph
For thermal compensation test, we design 41-stage ring
oscillator as the load of the DC-DC converter. Ring oscillator
is a key component in signal processing and clock generating
circuits. Its frequency stability is important issue as drift of
target frequency increases jitter and causes instability of
system. More importantly, delay line and ring oscillator are
the most representative circuits of pipeline data-paths and
sequential logics, respectively. The researches on these can be
IEEE TRANSCATIONS ON CIRCUITS AND SYSTEM – II: EXPRESS BRIEF
extended and applied into the general applications based on
logical effort theory [13].
5
stability. The design provides another solution to high
performance thermal management on CMOS digital ICs.
2.5
ACKNOWLEDGMENT
2.4
2.3
The authors thank Paul A. Brokaw of Analog Devices Inc. for
valuable discussions.
Frequency (MHz)
2.2
2.1
REFERENCES
2
1.9
1.8
1.7
1.6
1.5
0
20
40
60
80
100
120
Temperature (degree)
Fig. 11 Measured frequency variation versus temperature
Temperature Coefficient (ppm/degree)
80
79
78
77
76
75
74
73
1
1.5
2
2.5
3
3.5
4
4.5
5
Frequency (MHz)
Fig. 12 Measured temperature coefficients at targeted frequencies
Fig. 11 shows measured results of frequency variation of a
41-stage ring oscillator with temperature. Without thermal
compensation, the variation is around 7 KHz/°C or 4046
ppm/°C as shown in dash line. With the proposed thermal
compensation, the frequency variation is reduced to 0.15
kHz/°C or 74 ppm/°C as shown in solid line. Temperature
dependence of ring oscillator is significantly suppressed. Fig.
12 shows averaged temperature coefficient of various target
frequencies generated by ring oscillators with different stages.
The temperature coefficients at target frequencies of 1 to
5MHz are below 79.3 ppm/°C by successfully applying the
proposed compensation method.
IV. CONCLUSION
This paper presents a new thermal compensation method by
employing a temperature-adaptive DC-DC converter. Details
on operation principle and circuit design techniques are
discussed. An IC chip was successfully fabricated and tested
to verify the design idea. The measurement results show
significant improvement on digital circuits’ temperature
[1] P. Allen and D. Holberg, CMOS Analog Circuit Design, Oxford
University Press, 2002.
[2] A. Hajimiri, S. Limotyrakis and T. Lee, “Jitter and phase noise
in ring oscillators,” IEEE J. Solid-State Circuits, vol.34, pp.790804, June 1999.
[3] R. Achenbach, M. Feuerstack-Raible, F. Hiller, M. Keller, K.
Meier, H. Rudolph and R. Saur-Brosch, “A digitally
temperature-compensated crystal oscillator”, IEEE J. of Solid
State Circuits, vol. 35, pp.1502-1507, Oct. 2000.
[4] W. Michael and D. Bogdan, Thermally Compensated Current
Sensing of Intrinsic Power Converter Elements, U. S. Patent
2003038614.
[5] D. Foley, M. Flynn, “CMOS DLL based 2V, 3.2ps jitter, 1GHz
clock synthesizer and temperature compensated tunable
oscillator,” IEEE Custom Integrated Circuits Conference, pp.
371-374, April 2000.
[6] D. Ma, C. Zhang, Thermal Compensation Method for CMOS
Digital Integrated Circuits Using Temperature-Adaptive Digital
DC-DC Converter,” U. S Patent Series No. 60/657, 342, Feb.
28, 2005.
[7] D. Ma, W-H Ki, C-Y Tsui, “A Pseudo-CCM / DCM SIMO
switching converter with freewheel switching”, IEEE
International Solid-State Circuit Conf. (ISSCC), Digest of
Technical Papers, pp. 390-391, San Francisco, Feb. 2002.
[8] D. Ma, W-H Ki, C-Y Tsui, “Single-inductor multiple-output
switching converters with time multiplexing control in
discontinuous conduction mode,” IEEE J. of Solid-State
Circuits, vol. 38, pp. 89-100, Jan. 2003.
[9] S. M. Sze, Physics of Semiconductor Devices, 2nd Edition, New
York, Wiley, 1973.
[10] R. A. Blauschild, et. al., “A New Temperature-Stable Voltage
Reference,” IEEE J. Solid-State Circuits, no. 6, pp. 767-774,
Dec. 1978.
[11] T.D. Burd, T.A. Pering, A.J. Stratakos and R.W. Broderson, “A
dynamic voltage scaled microprocessor system,” IEEE J. Solid
State Circuits, vol. 35, pp. 1571-1580, Nov. 2000.
[12] D. Ma, W-H Ki and C-Y Tsui, “An integrated one-cycle control
buck converter with adaptive output and dual loops for output
error correction,” IEEE J. Solid State Circuits, vol. 39, pp.140149. Jan. 2004.
[13] Sutherland, B. Sproull and D. Harris, Logical Effort, Morgan
Kaufmann, 1999.