YEDITEPE UNIVERSITY ENGINEERING FACULTY
ELECTRICAL CIRCUITS LABORATORY
EXPERIMENT 1:
Kirchoff’s Voltage and Current Laws and Power Balance
Objective:
Verifying Kirchoff’s Voltage Law (KVL), Kirchoff’s Current Law (KCL) and Power
Balance.
Equipment:
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1 HP 34401A Digital Multimeter
1 HP E 3620A Power Supply
1 Protoboard
1 1 kΩ ¼ W Resistor
2 5.1 kΩ ¼ W Resistor
1 6.8 kΩ ¼ W Resistor
1 10 k ¼ W Resistor
General Information:
In this exercise Kirchoff’s voltage and current laws and Power Balance are examined
by applying them to the circuit in figure 1.
i1
V1
5.1 k
i2
1
V2
Vs = 10 V
2
V5
6.8 k
1k
V4
i6
i5
d
e
5.1 k
i3
c
i4
10 k
is
V3
b
a
3
V6
1.8 k
Figure 1
1. Kirchoff’s Voltage Law states that the algebraic sum of all the voltages around any
closed path (loop or mesh) in a circuit equals zero. In order to use Kirchoff’s voltage law, we
must assign an algebraic sign (reference direction) to each voltage in the loop. Assigning
positive sign to a voltage rise requires assigning a negative sign to a voltage drop. Applying
Kirchoff’s voltage law to the first and the second loops in the circuit shown in Figure 1 yields;
𝐿𝑜𝑜𝑝 1: − 𝑉1 + 𝑉3 − 𝑉2 = 0
𝐿𝑜𝑜𝑝 2: − 𝑉𝑠 + 𝑉2 + 𝑉4 + 𝑉6 = 0
𝐿𝑜𝑜𝑝 3: − 𝑉4 − 𝑉3 − 𝑉6 = 0
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(1a)
(1b)
(1c)
2. Kirchoff’s Current Law states that the algebraic sum of all the currents at any node
in a circuit equals zero. In order to use Kirchoff’s current law, an algebraic sign corresponding
to a reference direction must be assigned to every current at the node. Assigning a positive sign
to a current leaving a node requires a negative sign to a current entering a node. Applying
Kirchoff’s current law to the first four nodes in the circuit shown in Figure 1 yields the following
equations;
𝑁𝑜𝑑𝑒 𝑎: 𝑖𝑠 + 𝑖2 − 𝑖1 = 0
(2a)
𝑁𝑜𝑑𝑒 𝑏: − 𝑖2 − 𝑖3 + 𝑖4 = 0
(2b)
𝑁𝑜𝑑𝑒 𝑐: 𝑖1 + 𝑖3 − 𝑖6 = 0
(2c)
𝑁𝑜𝑑𝑒 𝑑: − 𝑖𝑠 − 𝑖5 = 0
(2d)
𝑁𝑜𝑑𝑒 𝑒: − 𝑖4 + 𝑖5 + 𝑖6 = 0
(2e)
3. Power Balance theorem states that sum of the instantaneous power of the elements
in a circuit equals zero. Power of a two-terminal element is equal to the product of the terminal
voltage and current whose reference directions are chosen due to passive sign convention.
Applying Power balance theorem to the circuit shown in Figure 1 yields;
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∑ 𝑉𝑛 𝑖𝑛 + 𝑉𝑠 𝑖𝑠 = 0
𝑛=1
Procedure:
1. Construct the circuit shown in Figure 1 using the resistor and voltage source values given
on the schematic.
2. Accurately measure all voltages and current, calculate all element powers. Write the
measurements to the table in the result sheet.
3. Verify KVL for the loops in the circuit.
4. Verify KCL for the nodes in the circuit.
5. Verify Power balance for the circuit.
(Be careful about units. Forgotten units will not be graded! )
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