UNIVERSIDADE FEDERAL DE SANTA CATARINA
PROGRAMA DE PÓS-GRADUAÇÃO EM ENGENHARIA ELÉTRICA
SOFT SWITCHING TECHNIQUES FOR
MULTILEVEL INVERTERS
TESE SUBMETIDA À UNIVERSIDADE FEDERAL DE SANTA
CATARINA PARA OBTENÇAO DO 'GRAU DE DOUTOR EM
ENGENHARIA ELETRICA
XIAOMING YUAN
FLORIANÓPOLIS, MAIO 1998
ll
SOFT SWITCHING TECHNIQUES FOR
MULTILEVEL INVERTERS
XIAOMING YUAN
ESTA TESE FOI IULGADA PARA OBTENÇÃO DO TÍTULO DE
DOUTOR EM ENGENHARIA
ESPECIALIDADE ENGENHARIA ELÉTRICA E APROVADA EM SUA
FORMA FINAL PELO CURSO DE PÓS-GRADUAÇÃO EM ENGENHARIA
ELETRICA.
\
Prof.
\
Aà
~
d
Coordenador do
.Í
Q
Prof. Ivo Barbi, Dr.
Dr.
`
PD/"I
~
Orientador
BANCA EXAMINADORA
øfww
ø
Prof. Ivo
~
,!í_§_¡T1,.›.£
He, Dr.
Áeqzaudu šâuwú J: ámaa.
Prof. Hélio
Prof.
cães
Alexandre Ferrari de Souza, Dr.
Prof.
enizar
am.
Prof.
z
ruz
ff.
aíldo J
'
`ns,
Dr.
ff
~
erin, Dr.
Dr.
~
To my parents
IV
Acknowledgments
To
Prof. Ivo Barbi, for his professionalism, instruction
and solicitude from time to time
during this work. The rigorous approach taken for academic research will be the model to be
followed throughout the future technical career.
To
from
the professors in INEP, for their support and understanding.
Prof.
Enio Valmor Kassick
is
especially appreciated.
The generous
attention
Thanks are also due to Dr. Roberto
Rojas, for his friendliness and consultation.
To
W€I`€
the
many
colleagues in INEP, for their friendliness and help whenever difficulties
€l'lCOl1I1Í€I`Cd.
'
my wife, in particular, for the conciliation, understanding and devotion from her. To
my family and the family of my wife, for the sound backing from them, which has enabled me
To
to concentrate
on this work.
\
V
About the Author
Xiaoming Yuan was bo_m in Anhui,
P. R. China,
on May 30, 1966. He received the B.
Eng. degree from Shandong University of Technology, P. R. China, and the M. Eng. degree
from Zhejiang University,
P. R. China, in
1986 and 1993 respectively, both in Electrical
Engineering.
He was
for
'
with Qilu Petrochemical Corp. during 1986-1990 as a commissioning engineer
power system protection, automation and power
electronics installations.
He was a visiting
engineer at Tianjing Electrical Drive Institute during 1989 for the development of a
VVVF
400kVA
system. During 1993-1994, he was with the Power Electronics Institute of Zhejiang
University, developing
UPS and induction heating projects.
He was awarded
the
Baogang Scholarship
Education Commission and Baoshan Iron
University.
&
jointly sponsored
by China National
Steel Corp. during his study at Zhejiang
He is currently a student member of the IEEE Industrial Electronics
Society.
Vl
Contents
Nomenclature
x
Abstract
1.
xiii
Fundamentals of Multilevel Inverters
1.1.
Implementation of High Power Converters
1
1.1.1.
Device Association
1
1.1.2.
Converter Association
2
1.1.3. Cell
1.2.
1
Association
3
Diode Clamping Multilevel Inverter
4
H
1.2.1.
Voltage Synthesizing
4
1.2.2.
Modulation
5
DC Supply Structures
1.2.4. Neutral Potential Control of the NPC Inverter
1.2.3. Potential Drift
Other Operation Problems
1.2.5.
1.3.
1.4.
1.5.
2.
and
'
8
8
9
Capacitor Clamping Multilevel Converter
10
1.3.1.
Voltage Synthesizing
11
1.3.2.
Modulation
12
1.3.3.
Dynamic Clamping Voltage Distribution
13
Snubbing Techniques for Multilevel Inverters
14
1.4.1.
Dissipative/Regenerative Snubbers for Two-Level Inverters
14
1.4.2.
Dissipative/Regenerative Snubbers for Multilevel Inverters
16
1.4.3.
Snubber Problems
19
~
Conclusions
21
True-PWM-Pole Two-Level Inverter
2.1. Soft
Switching Inverter Circuits Review
2.1.1. Different
Types of Switching
22
22
22
2.1.2.
Resonant DC Link Inverter Circuits
23
2.1.3.
Resonant Pole Inverter Circuits
24
2.2.
True-PWM-Pole Inverter Circuit and Operation
27
2.3.
True-PWM-Pole Inverter Commutation Analysis
30
2.3.1. Total
Commutation Duration
30
2.4.
2.3.2. Auxiliary
Switch Peak Current Stress
2.3.3. Auxiliary
Switch RMS Current Stress
True-PWM-Pole Inverter Designing
2.4.1.
Transformer Ratio k
2.4.2.
Resonant Frequency mo
2.4.3.
Resonant Capacitor C, and Resonant Inductor L,
2.4.4. Auxiliary
Switch Gating Signal Width and Minimum
_
PWM
ON/OFF Time
2.4.5.
Rating of the Auxiliary Switch
2.5.
True-PWM-Pole Inverter Experimentation
2.6.
True-PWM-Pole Inverter Variations
2.6.1.
Normal Auto-Transformer Connections
2.6.2.
Modified Auto-Transfonner Connections
2.6.3. Capacitor
Connection
Conclusions
2.7.
Appendix 2.1. Mathematical Analysis of the ARCPI
Appendix
2.2. State equations for the
modified True-PWM-Pole schemes
Appendix 2.3. Analysis of the commutation resonance in the capacitor
i
connection inverter
3.
'
Operation of the Three Level Capacitor Clamping Inverter
3.1.
Basic Operation Problems
3.2.
Clamping Voltage Steady State Stability
3.3.
Output Voltage Spectrum
3.4.
Clamping Capacitor Stress
3.5.
Clamping Voltage Dynamic
Stability
3.5.1. Self-Balancing
under Ideal Condition
3.5.2. Self-Balancing
under Non-Ideal Condition
3.5.3. Self-Balancing in
Three Phase System
3.6.
Experimental Verification
3.7.
Conclusions
Appendix
4.
3
3.1.
PSPI_CE program for simulation under non-ideal condition
True-PWM-Pole Three Level Capacitor Clamping Inverter
8
viii
4.1. Circuit
4.2.
Configuration
70
Circuit Operation
71
Features
74
4.3. Specific
4.3.1.
clamping voltage
4.3.2.
Normal Auto-Transformer Connection of the Second Pole
74
slzbilizzúion
75
H
5.
4.4.
Topologizs for Mulúlevel case (M>3)
75
4.5.
Conclusions
78
Designing and Experimentation of the True-PWM-Pole Three Level
Capacitor Clamping Inverter
-
79
5.1.
Prototype Specifications
79
5.2.
Main circuit Designing
só
,
5.3.
5.2.1.
Power Supply
80
5.2.2.
DC Link Capacitor
80
5.2.3.
Clamping Capacitor
80
5.2.4.
Output Filter
80
5.2.5.
Main Switches
81
Resonant Circuit Designing
5.3.1.
_
Resonant Components and Auxilialy Transfonner
81
81
5.3.2. Auxiliary
Switches
81
5.3.3. Auxiliary
Diodes
83
5.4.
Thermal Designing
83
5.5.
IGBT Driving Designing
84
5.5.1.
Main IGBT Module Driving
5.5.2. Auxiliary
5.5.3.
5.6.
5.7.
5.8.
84
IGBT Module Driving
Zero Voltage Detecting
85
86
Control Designing
87
5.6.1. Control
Requirements
87
5.6.2. Control
Diagram
87
Experimental Results
Conclusions
ss
V
92
Appendix
5.1.
BASIC program for generating the gating signals in EPROM 27256M 93
Appendix
5.2.
Control diagram of the prototype
95
6.
Operation of the Neutral-Point-Clamped (NPC) Inverter
PWM Modulation
6.1.
Sub-Harmonic
6.2.
Neutral Potential Steady State Stability
6.3.
Self-Balancing under Ideal Condition
6.4.
Self-Balancing under Non-Ideal Condition
6.5.
Self-Balancing in Three Phase System
6.6.
Conclusions
Appendix
6.1.
_
PSPICE program for self-balancing under ideal condition
Appendix 6.2. PSPICE program for self-halancing under non-ideal condition
True-PWM-Pole Neutral-Point-Clamped (NPC) Inverter
7.
~
7.1.
Review of the Existing Work
7.2.
Proposed Circuit Configuration
7.3.
Circuit Operation
7.4.
Topologies for Multilevel Case (M>3)'
7.5.
7.6.
7.4.1.
Zero Voltage Switching on the Per-Leg Basis
7.4.2.
Zero Voltage Switching on the Per-Cell Basis
Experimentation
Conclusions
A
Appendix 7.1. BASIC program for generating the gating
8.
signals in
A New Diode Clamping Multilevel Inverter
8.1. Series
8.2.
EPROM 27256
Association of Diodes in the Conventional Inverter
Operation of the New Inverter
8.2.1.
Switching Cells of the New Inverter
8.2.2.
Switching State of the Diode Network
8.2.3.
Switch and Diode Clamping Mechanism
8.2.4.
Over-Voltage from Indirect Clamping
8.3.
Snubbing/Soft Switching of the New Inverter
8.4.
Experimentation
8.5.
Conclusions
Appendix
9.
6
8.1.
BASIC program for generating the gating signals in EPROM 27256
General Conclusions
References
~
Nomenclature
PWM: Pulse Width Modulation
True-PWM-Pole: True PWM Zero Voltage Switching Pole
inverter
NPC: Neutral-Point-Clamped inverter
ARCPI: Auxiliary-Resonant-Cormnutated-Pole-Inverter
ACRLI: Actively-Clamped-Resonant-DC
Link-Inverter
DPM: Discrete-Pulse-Modulation
ZVS: Zero-Voltage-Switching
ZCS: Zero-Current-Switching
SVM:
Space-Vector-Modulation
FFM: Fundamental-Frequency-Modulation
C1, C2:
DC link capacitors
Cm: clamping capacitor
Cf:
output filter capacitor
C,,, C,2, C,3_ CM:
Cs:
d:
snubber capacitor
instantaneous duty ratio
d,, dz, d3, d4:
fm:
fc:
resonant capacitors
instantaneous duty ratios of cell
1,
2, 3,
4
fundamental output frequency
switching frequency
G: self-balancing constant
im: instantaneous clamping capacitor charging current
icmmsz instantaneous clamping capacitor
rms current
ihpms:
instantaneous resonant inductor rms current from diode to switch commutation
ilmrms:
instantaneous resonant inductor rms current from switch to diode commutation
imã: instantaneous resonant inductor nns current
io:
instantaneous inverter output current
in:
instantaneous current out of the neutral point
im: instantaneous output filter inductor current
I°.m,s:
inverter output
rms current
inverter output
Ip:
peak current
device actual tum-off current
ITQ:
freewheeling diode reverse-recovery current
I,,:
k: auxiliary
L,,4_
transformer ratio
Lm: resonant inductors
Lf: filter
inductor
snubber inductor
Ls:
.
mod(t): modulating sinusoidal reference
M: index of sub-harmonic modulation/number of inverter levels
p:
number of switching
P0:
output power
Ps:
snubber loss
Q: quality factor
cells
.
R: resonant loop equivalent resistance
Ro: load resistance
SW: NPC
leg switching fimction
SW,: switching function of cell
1
SW2: switching function of cell 2
switching cycle
Vdc:
_
DC link voltage
VS,: device
blocking voltage of switch
S,
instantaneous inverter output voltage
vo:
V0.,mS: inverter
output rms voltage
vm: instantaneous voltage of resonant capacitor CH
vem:
vcs:
clamping voltage during dynamics
instantaneous auxiliary capacitor Cs voltage
vdl, vdz:
v A0:
DC link capacitor voltages during dynamics
direct inverter output voltage during
dynamics
f
Z0: resonant impedance
6: leading angle
õ:
of output voltage versus output current
declining factor of output low-pass filter
6: snubber loss factor
'
-
com: inverter
toc:
output fundamental angle frequency
sub-harmonic carrier angle frequency
AVAO: direct inverter output voltage variation to clamping voltage perturbation
Aim: load current variation to clamping voltage perturbation
Aicm:
clamping capacitor charging current variation to clamping voltage perturbation
Aicm.dc:
Ai":
in
Ainda:
DC component of Aim
variation to neutral potential perturbation'
DC component of Ai"
xm
_
Abstract
This thesis deals with the soft switching techniques applied to multilevel inverters for
high frequency high voltage and high power conversion. The following subjects are studied to
this end:
Multilevel inverter operation. After the brief inspection of the conventional high
1.
power converter
structures
employing device association or converter association,
fundamentais and problems of the multilevel inverters evolved from
examined. Clamping voltage
stability
cell association are
of the capacitor clamping inverter and
the. neutral
potential stability of the diode clamping inverter are explored in details.
Multilevel inverter commutation. Major snubbers used in two-level and multilevel
2.
The problems associated with these snubbers
inverters are reviewed.
are outlined. Further, soft
switching techniques reported for two-level inverters are assessed.
The transformer connection True-PWM-Poleutechnique
utilized
(NPC)
and tested in three
inverter.
(ARCPI)
level capacitor
is
proposed and
tested. It is then
clamping inverter and the Neutral-Point-Clamped
This technique along with the Auxiliary-Resonant-Cormnutated-Pole-Inverter
are both extended to the multilevel case (M>3), the topologies are demonstrated.
Auto-transformer cormection and capacitor connection True-PWM-Poles are also
discussed.
3.
_
New
multilevel inverter topology.
series association
is
of the clamping diodes
is
A new diode clamping multilevel
introduced, analyzed and tested. It's shortcoming
unveiled. Clamping, snubbing and soft switching of this
With
inverter free of
new inverter are shoitly treated.
this investigation, the basic aspects in regard to soft switching
inverters are outlined.
of multilevel
xiv
Resumo
Esta tese apresenta técnicas de comutação suave aplicadas a inversores
níveis para aplicações de alta freqüência, alta tensão e alta potência.
estudados
alta potência
A
com múltiplos
níveis.
Após breve
análise das estruturas de
convencionais que empregam associação de interruptores ou -associação de
conversores, examinam-se os fundamentos e problemas dos inversores
A
mútliplos níveis.
do potencial de neutro do inversor com diodo de grampeamento são exploradas
em detalhe.
'
.
Comutação dos inversores com múltiplos
2.
com
grampeamento do inversor com grampeamento capacitivo e a
estabilidade da tensão de
estabilidade
múltiplos
seguintes assuntos são
com esta finalidadez'
Operação dos inversores
1.
Os
com
níveis.
A maioria dos circuitos de ajuda à
comutação (snubbers) utilizados nos inversores com dois níveis e com múltiplos níveis é
revisada.
Os problemas
as técnicas de
associados a estes snubbers são delineados.
Além
disso, analisam-se
comutação suave conhecidas para inversores com dois níveis.
A técnica True-PWM-Pole com conexão de transformador é proposta e testada,
então utilizada e ensaiada
um
inversor
em um inversor com tres níveis com grampeamento
com grampeamento no
técnica e 0 inversor
com
ponto neutro
(NPC
-
sendo
capacitivo e
em
Neutral-Point-Clamped). Esta
pólo de comutação auxiliar grampeado
(ARCPI
-
Auxiliary-
Resonant-Commutated-Pole-Inverter) são estendidos aos casos de_múltiplos níveis (M>3) e
suas topologias são apresentadas.
Discutem-se também as conexões de auto-transformador e de capacitor para a técnica
True-P WM-Pole.
3.
níveis
Nova
topologia de inversor
com grampeamento a
com
diodos,
múltiplos níveis.
Um novo inversor com múltiplos
sem necessidade de
grampeamento é introduzida, analisada e
testada,
associação série dos diodos de
sendo também apresentadas as suas
deficiências. Analisam-se ainda o grampeamento, a estratégia de ajuda à comutação
_
(snubbing) e a comutação suave deste novo inversor.
Com
esta investigação, os aspectos básicos relativos à
com múltiplos níveis são apresentados.
comutação suave de inversores
1
Chapter 1. Fundamentals of Multilevel Inverters
Abstract: This chapter reviews the existing approaches for implementing high power
converters.
The ftmdamentals of multilevel
inverter circuits, including voltage synthesizing,
modulation as well as their specific problems are then discussed. Commutation issues of these
circuits are specifically treated
which will be the main subject of this thesis.
Implementation of High Power Converters
1.1.
The power
electronics
community has witnessed
in the last
in the ratings as well as the switching characteristics of the
Most remarkably,
the 3.3kV, l.2kA
IGBT modules and
decade continuous advance
power semiconductor
the 6kV,
6kA GTO
devices.
entered the market, and the development targets for the near future are the 4.5kV
module and the 9kV-12kV
traction drives
GTO
and supplies or
However, high power
thyristor [l].
utility applications [2] [3] [4], call for
involving higher voltage or current with adequate performance.
have
thyristors
IGBT
electronics, typically
switching operation
To meet this demand,
devices,
switching cells or converters have been associated as solutions.
1.1.1
.
Device Association
Parallel association: Converter current handling capability can be raised by paralleling
two or more IGBT modules together
[5] [6].
The major problem of this association
is
the
unequal current sharing due to the module parameters deviations as well as the construction
and thermal coupling
issues.
Moreover, highcurrent operation demands bulky setup with
voluminous power connections evoking problems with
thyristors
can not be associated in parallel, which will lead to unequal current distribution
Series association: Series association of
voltage operation in railway interties
commutated
AC/DC
[7],
GTOs
STATic CONdenser (STATCON)
converter [9] applications.
It is
[9]
level [9] [67].
By
[7].
has been a proven technique for high
[8]
and
self-
further enabled with the possibility to
supply the gate units directly from the main circuit rather than a low voltage supply
ground
GTO
stray inductances. In practice,
at the
device screening, gate units adaptation, precise gate tum-off timing
or hard gate drive [7] [l0], voltage sharing can be well ensured.
Series association of
2
IGBTs is also under investigation
the redundancy
it
offers
A distinguished advantage of series association is
by adding one more device
in the ring, as well as the individual
time extension as a result of voltage stress reduction.
device
life
1 . 1 .2.
Converter Association
In_
[1 1] [12].
waveforms as
the case of device association, either parallel or series, the converter
well as the di/dt or dv/dt rates of change do not benefit from the multiple devices. In converter
association, however, multilevel
waveforms
are synthesized while the di/dt or dv/dt rates
remain unchanged. Converter association can be realized in one of the following approaches.
DC side
AC side
in parallel/
in parallel
by transformer: As shovvn in Fig.
secondary voltages are imposed and the secondary current ripple
is
the leakage inductance has to be located at the secondary side,
which
transforrner construction [l4].
drives
[3].
But it
is
not
This configuration
recommended
for
is
found
at the
high.
To
is
limit this ripple
not favorable for
supply side of locomotive
STATCON application due to the harmonic currents
flowing through the inverters and the transformer secondaries
[8].
DC side in parallel/AC side in series by transformer: As shown in Fig.
at
l.1(a), the
l.1(b), currents
both sides are imposed. The low ripple secondary current results in lower converter losses
and magnetic
losses.
Railway
and also
interties [3]
STATCON
[8] [13]
have employed such
configuration. Transformer leakage inductance can be located at either side.
DC side in parallel/AC side in parallel by Current-Sharing reactor: As
1.1(c),
the
spontaneous current sharing
number of converters
is
is
shown
achieved through this configuration [15]. Obviously,
limited to two.
`
`
DC side in parallel/AC side in parallel by separate reactor: As shown in Fig.
paralleling converter subsystem, this structure is characteristic of
its
DC side
been widely
by
summing
utilized especially in industrial drive areas [7].
in series/AC side in series
by transformer: As shown in Fig.
currents at both sides are imposed allowing for lower losses.
in
l.l(d),
homogeneous modular
construction, operation redundancy as well as the reduced current ripple of the
current. It has
in Fig.
DC/AC/DC converter applications [16]
l.1(e),
again
Such configuration can be found
'
[l7].
A
DC side in series/AC side in parallel by transformer: As shown in Fig.
1.l(f),
voltages
of the secondary sides are imposed forcing each converter working independently. The
structure enables high voltage operation with reduced
harmonics in the summing current
[18].
AC side connected to open winding:
_
[l9], as
shown
in
ig. 1.l(g),.
In this case, the
3
DC
side can be either in parallel
or series or separated [20]. Chokes to suppress zero sequence
number of converters is limited to two.
voltage are necessary. Again, the
DC side isolated (H-bridge cascade inverter): As shown in Fig.
merit of this configuration
is
by JET
shows
other. Literature review
broadcasting amplifier by
[22]
ABB
most
salient
the possibility of direct connection to high voltage system,
allowing for elimination of the heavy transfonner. However, each
from the
1.1(h), the
[21]
more than a decade
that this [type
DC
side
must be
isolated
of inverter has been constructed as
and as high precision current supply. for plasma physics
ago.
It
has in the recent years been recommended for other
applications including industrial drives [23] [24], traction [25], active filtering [26] and
especially static
T]
VAR compensator [27] [28].
\_
T'
u!|
_\_
~
~
~
~
T
T
(b)
(a)
_\_
_
I
T
||!|
_\_
T
(d)
(C)
:HT
..._\_
1
l
(¢)
(Í)
Fig. 1.1. Different circuits resulted
1 . 1 .3.
(h)
(g)
from converter association.
Cell Association
Parallel association:
As shown
in Fig. l.2(a), the cellular structure allows for feeding
high current with greatly reduced ripple
[29]. In particular,
assuming a non-zero impedance of
the voltage source at the switching frequency, current sharing
alternative technique
less paralleling
was
also recently explored [31], as
shown
becomes inherent
[30].
An
in Fig. l.2(b). Direct reactor-
of cells has also been reported in engineering application, which enhances the
current capacity but without reducing the ripple [70].
Series association:
Explorations on the series association of cells in _the past two
decades have given birth to two major structures: the diode clamping multilevel inverter [32]-
4
_
[3 7],
and the
capacitor'
clamping multilevel inverter [38]
[39].
clamping inverter (N eutral-Point-Clamped-NPC) which has
Except for the three level diode
now been increasingly
re2 F*
raz-
by the industry for high voltage high power applications, other
circuits
accepted
of the family are
still
under investigations.
(b)
(=1)
Fig. 1.2. Different circuits resulted
1.2.
from parallel association of cells.
Diode Clamping Multilevel Inverter
-The idea of diode clamping was first established in three level”s case, which
known as the NPC
[34]-[37]. Fig. 1.3
inverter [32][33].
shows a five
It
was then extended to any
level inverter leg,
level
by
is
now
different researchers
which can be regarded as being set-up by
four two level switching cells in quasi-series: C4, S4, Sƒ; C2, S2, S2°; C2, S2, S3” and C4, S4, S4”.
Switches
S1, S2, S2
and S4 in the up-ann and also switches
ann can be regarded
in quasi-series.
switches in different
cells,
dv/dt remains the
1.2.1.
S4' in the
down-
timing the switching actions of the corresponding
an output waveform with five level
is
obtained, while terminal
same value as each single device sees in the cells.
Voltage Synthesizing
Suppose
By
and
S4”, S2”, S2'
that the
DC
V
link voltage is equally distributed
capacitors, then a staircase output
waveform with reference
to the
among
the four storage
DC capacitor neutral point
could be synthesized as shown in Fig. 1.4 according to Table1.l. Note that the eight switches
give only
each cell
‹›
0
five switching
is
states
and five output voltage levels are produced. The switching of
conditioned by the others as following:
C
An outer switch can only be turned on when the inner switch is in conduction.
An inner switch can only be tumed off when the outer switch is not in conduction.
V5
.
‹›|
__íC]
°'
Ã
__ C2
ZS
“Z
VAO
fl
Ã
52'
00-ii-0
ZS
Ã
D9
D3
ZS
D8
‹›4
›
S.-
I
52
I
'
S3
U
S2'
I
'
S3'
A
›
S3'
U
›
.
S4
4
D4
S.
I
‹›4
'
ÃD11
LL
Vi
‹›|
|Sš`
ZS Dn»-1
C3
Z§Ds ZFD|o
as
ao
VD2+Ds+mz
°¬l
i
Vml
VDz+ns+m2
'
›
|
ZÉ
Dó
VD4+D|oi
°-I
Vm+D3
|
I
IVn4+1›1o
P
C4
Voa
°i
VDõ
Vm+m+Ds
S4'
|:'
Fig. 1.3.
A five level diode clamping
inverter leg,
consisting of (5-l) storage capacitors, (5-l)×2
H
Fig. 1.4. Switching
i
sequence with the resulting output
waveform and the blocking voltages across
switches and a total of (5-l)×(S-2) clamping diodes.
the
clamping diodes.
V
1:
Table
1.1.
Diode clamping five
Output V A0
level inverter switches combinations
switches combinations
Levels
s,*
1.2.2.
3
S27
S3)
S49
V5=l/2 Vdc*
1
0
O
0
0
V4=l/4
O
1
O
O
O
0
1
l
O
O
Vdc
O
1
1
1
0
v,=-1/2 Vdc
0
1
l
1
1
V2=' 1
*
SI
Vdc'
Vdc stands for the total
Z
DC link voltage.
Modulation
Fundamental-Frequency-Modulation (FFM:
device rating
is
For
a major factor limiting the obtainable
large
maximum
power applications where
power,
full utilization
of the
6
device will be interesting [l4]. The
Additional benefit of FFM
the
is
expense of slow response. Bulky
FFM
has been deemed the best solution in this case.
low switching
filters
are always used to ensure
-PWM modulation: The
Sub-harmonic
and high efficiency,
loss (snubber loss)
increased
power
performance of turn-off devices together with advanced
low interfacing THD.
and improved switching
rating
circuit techniques
have been creating
PWM in high power applications. This can be found in most of
increasing possibilities using
the high power drive applications [20].
The idea of multilevel
PWM
has been well established that suits well the
PWM
The pattem shown
in Fig.
modulation of a M-level diode clamping multilevel inverter
1.5 is for the case
of a five level inverter
four carriers generating the four
different dispositions
[40].
of the
DC
with the
intersects
PWM signals for the four switching pairs.
carriers
The down
trace
neutral potential of the leg. Several
have been studied exhibiting different harmonic results
PWM modulation for single phase and three
Engineering applications of sub-harmonic
phase NPC inverter have been reported
Space-Vector-Modulation:
[40].
where the reference signal
leg,
output voltage with reference to the
illustrates the
at the
[3] [41].
-
Space-Vector-Modulation
(SVM)
has been extensively
PWM
reported to offer superior performance in comparison to conventional
techniques
(natural sampling or regular sampling etc.), in terms of the reduced harrnonics, optimized
switching sequence and increased voltage transfer ratio [42]-[44].
approach to realize
plane, a
NPC
redundant
has also been a major
PWM pattern in NPC inverter [l8], [45]-[47] by industry.
inverter can
triangular pattems,
It
be represented by 27 switching states located
among which 19 of them
states, as
shown
in Fig. 1.6.
are independent states
PWM
commands can be
voltage vector
is
located.
the next sampling period.
The
harmonic
at the
at the
complex
comers of
and the remaining 8 are
created
desired voltage vector at a constant sampling frequency, such sampling
by a sequence of three vectors defined
In a
is
by sampling the
then approximated
comers of the sub-triangle where the desired
Such approximation leads the output value
to the set-point within
_
resultant switching sequence
of SVM
is
essentially similar to that obtained
by sub-
PWM when adding a zero sequence component to the sinusoidal reference in a three
phase system
[48]. In principal,
level three phase
1+3M(M-1)
system will
SVM can also be applied to a M-level (M>3) inverter. A Mbe able to work with M3 switching states, among which
states are distinctive states.
No engineering results have been reported.
7
›‹VWW\\
ÍÂ
S.
as
‹t
\yÁ'A'›‹›
S4
VAO
Fig. 1.5. Multilevel
'_
"
-
um
PWM method for a diode clamping multilevel inverter leg.
~ ~ ~
°**°
'
-1,0,-1
Fig. 1.6. Space vector diagram of the
Closed loop modulation: In addition
27 switching
to the
states
'
of a NPC
inverter.
open loop schemes reviewed above, closed
loop schemes like hysteresis current control [49] or delta voltage control [23] have also been
investigated,
which allow the generation of multilevel gating sequences inherently
in the
8
closed loop. In particular, hysteresis current control has been used to supply high precision
current for the saddle coils in plasma research [22].
1.2.3. Potential Drift
and DC Supply Structures
Drift mechanism:
potentials
which may
The M-1 storage
drift if the net
capacitors at the
wavefonn
subjected to destructive voltage stress. For the
0
When
will
°
~
is
Both converge
five
and further some devices will be
level case
V3 which keeps
shown in Fig.
1.3,'
two
situations
stable.
Eventually a five level inverter
potential (level V3) doesn°t drift.
On the other hand, when the load current is pure-reactive, either lagging or leading, the net
average charge
flows
into each level over a switching cycle is zero. Ideally all
V3 and V4 are always
To
stable.
Use regulated
DC
complex AC/DC
Use regulation
results
have been reported.
sources in the places of the storage capacitors [52], which requires
circuitry to enforce the energy
flow
between the neighboring capacitors,
for both unidirectional or bi-directional operation [3 5] [53].
Use back-to-back system where charges from both
is
feasible only
control of the
Note
that
the following approaches
circuitry.
which is applicable
which
voltage
'
enable active power processing,
have been proposed but no engineering
°
floating
not pure-reactive, level V4 will decrease and level V2 will
to level
DC supply structures:
°
distortion
become a three level one, while the neutral
levels V2,
°
M-2
[51]:
the load current
increase.
link gives
average currents flowing into the given potentials are not
zero. Potential drift will cause output
can be identified [50]
DC
when
sides
compensate each other
input/output voltages are equal. Otherwise very
AC/DC converter will be required [54]
when pure reactive power is processed,
[50],
complex
[55].
potential drift
may
still
happen due to
unequal capacitor leakage currents, unequal device switching delays as well as asymmetrical
charging during transience operation
etc.
Thus
active control over each potential is
still
necessary in this case [56] [57] [58].
1.2.4.
Neutral Potential Control of the NPC Inveiter
Neutral potential self-balancing:
wave symmetric,
typically
When
switching function of each
when sub-harmonic modulation
is utilized,
NPC
leg
is
quarter-
the neutral potential
is
9
_
found to be self-balancing when the load
deviation causes
not pure reactive [59] [60]. Neutral potential
is
DC current component flowing in the neutral line rejecting the deviation.
However, under space vector modulation, when the two
states
of the middle vector are
not duly distributed during the local switching cycle [45], the neutral potential will become
unstable and the self-balancing property will be
Neutral potential control:
lost.
In the case of space vector modulation, neutral potential
control can be achieved in principle by
making use of the redundant
states
of the middle
vectors in a three phase system [45]-[47], [61]-[62]. The redundant state of a middle vector
tends to complement the charging/discharging
flowing
into the neutral potential resulted
same vector.
the other state of the
from
C
'
Depending on the extent of asymmetry
resulted mainly
from
different gating/switching
delays, load transience, load unbalance etc. in a practical system, the need for active neutral
potential control
à«
may
arise
even when sub-harmonic
can¡be realized by superimposing a zero sequence
PWM modulation is used. Such control
DC component equally to the three phase
references according to the neutral potential deviation direction as well as the system
operation
›....
'›‹z.z.~-
».z..
mode
[63]-[64].
fundamental cycle
suppressing
1.2.5.
is
is
that the net charge to the neutral potential during a third
that such action
of
Other Operation Problems
The complex
structure of the diode clamping multilevel inverter results
complex coupling among the commutating
parasitic inductances
through
S2”, S2”,
cell
and the non-comrnutating
and capacitances. Refer to Fig.
Dm and D4
parasitic inductance
S4”,
cells
through the
negative current
flowing
of S2' will then lead to the
due to the demagnetization of
of the neutral bus.
Indirect clamping of inner switches: Except for the
switches are not directly clamped. Refer to Fig.
1.3, for the
S2 in series with D, rather than S2 directly that
capacitor C2. Similarly,
by D2, D2 and DI2
when a
1.3,
to the neutral potential, the turn-off
discharging of the parasitic capacitances of S3' and
is
Note
altered without affecting the line voltage.
of the
a low frequency behavior.
Cell coupling:
in
So
it is
to C2.
S2' in series
Due
with D4,
is
two
lateral switches, all the inner
switching cell of C2, S2 and
clamped by D3 and D2
Dm rather than S2'
S2”,
it
to the storage
directly that is
clamped
to this indirect clamping, the discharged state will hold
and
10
unequal blocking voltage distribution will happen.
An imier switch always sees higher voltage
than the outer one and the center switches will be mostly stressed.
The unequal voltage
[19] [65]
and
is
distribution is a structural shortcoming
common for the
neighboring switches
is
of the
NPC
inverter [18]
diode clamping family. The voltage difference between the
directly related to the
clamping bus parasitic inductance and therefore
can be minimized by introducing advanced manufacturing techniques [68]-[70].
Series connection of clamping díodes:
number of
fast diodes
corresponding voltage
must be put
stress.
The
capacitances of these fast diodes
same
As shown in Fig.
in series in each
diversity of the
may
and Fig.
1.3
clamping path to withstand the
tum-on/tum-off characteristics and the stray
cause dynamic voltage distribution problems. In the
sense, different blocking characteristics of these diodes
distribution problems.
1.4 that appropriate
The use of grading
may
cause
resistance for static voltage sharing
voltage
static
and snubbing
A
capacitance for dynamic voltage sharing lead to lossy and voluminous solution.
of this problem willbe discussed in Chapter 8 of this thesis.
structure [3 7] free
›
Snubbing
new
Aside from the two
difficulty:
lateral buses, all the inner
clamping buses in a
M-level system (M>3) carry currents that are bidirectionally controlled which causes
difficulty in offering .polarized damping for tum-on.snubbing reactors. Non-polarized snubber
is
especially inefficient [66]. Solutions to this problem
employed
in this structure for
GTOs
can be
any practical applications.
Capacitor Clamping Multilevel Converter
1.3.
While the
was
NPC
inverter
also introduced [38].
until the introduction
leg
must be found before
is
switches S,,
However,
this technique
1.7. Similarly, this leg
cells: C4, S4
S2, S3
in the late '70's, the capacitor clamping. inverter
had received
of the “ Imbricated Cells” A[39].
shown here in Fig.
of four switching
was proposed
and
S,,';
C3, S2
corresponding switches in different
cells,
A five-level capacitor clamping inverter
and Sƒ; C2, S2 and
By
intemational attention
can be regarded as the quasi-series association
and S4 of the up-arm and switches
be regarded in quasi-series association.
little
S,”, S2”, S3”
timing
S2°; C1, S1
and
S4'
and
S2”.
Besides,
of the down-arm can
the switching sequence of the
a terminal output of five level
is
obtained.
l l
1.3.1
.
Voltage Synthesizing
In a
five
level diode
dependent on the other
~
clamping inverter
leg,
switching action of one switching cell
and the eight switches give only five
cells
different switching states
producing five level output. However, in a capacitor clamping inverter
clamping voltage
From
the operation of each switching cell
is stable,
is
leg,
suppose that each
independent of the others.
the eight switches 16 different switching states are available producing the
output. This redundancy can be witnessed
--›
3.
d¡×i0
CI I
dzxio
d3›‹io
›
_?_
_?_
Sz
S¡
Cell
2
C2
$ ¡c2
(d|-dz) xio
T
í›
T
(I-d¡) xio
V
i
d4›‹io›
S4
Cell 3
Cell
-
4
¡°
C4
¿ ¡c3
$ ¡c4
(dz-d3) xio
T
(l-dz) xio
322
T
(I-d3) xio
P
A
(dg-d4) xio
W:
W.
vb'
-
›
C3
Cuz
1.2.
S3
Cell
l
~cl
Fig. 1.7.
from Table
(1-d4) xio
P
Diagram of a capacitor clamping 5-level
P
inverter leg consisting
(5-l)× 2 switches and (5-1) storage capacitors.
A
VAO
¡o
lcl
J
'ic2
'icll
›
a
_¡M
›
g
Sr
|Si|
S2
n
sz'
S4”.
|
l
S37
s4
S1'
›
|
›
f
I
sy
›
|
s4*›
u
I
Fig. 1.8. Voltage synthesizing of the capacitor clamping
'inverter
is
five
under fundamental frequency modulation.
level
~
of
five
level
`
12
In comparison with the diode clamping multilevel inverter where one state corresponds
to
one
level, the multiple states for
each level in capacitor clamping inverter allows
performance optimization for the given
shows an
1.8
criteria.
illustrative voltage
synthesizing under fundamental frequency modulation pattem.
Table
1.2.
Capacitor clamping five level converter switches combinations
Output VAO
Switches Combinations
Sl
S2
S3
SJ
SI,
S2,
S3,
S4,
1/2 vdc
1
1
1
1
0
0
0
0
1/4 v_,c
1
1
1
0
0
0
0
1
-
A
1
0
1
0
0
1
0
l
O
l
l
0
l
0
0
1`0100101
'01011l010
0
-1/4 v,,Ç
-1/2 vá.
1
0
l
l
l
I
0
0
0
l
l
0
0
0
0
I
l
l
O
0
l
0
l
l
0
0
1
1
0
1
0
0
1
0
0
l
l
l
l
0
O
1
0
0
0
0
1
1
1
0
l
0
0
l
0
l
l
0
0
l
0
I
I
0
l
0
0
O
l
l
I
l
0
0
0
0
0
1
1
1
1
Vdc stands for the total
1.3.2.
'
_
DC link voltage.
Modulation
Steady state clamping voltage distribution:
during each switching cycle
set equal.
Steady
is
each capacitor
cell,
when the
is
cells,
load current
cell
must be
then guaranteed due to the
flow through each capacitor during each switching cycle
Output voltage harmonics: For a leg with p
applied to each
in Fig. 1.7,
supposed to be constant, the duty cycle for each
state voltage distribution across
zero average current
As shown
.
assuming an identical duty cycle
a set of gating signals phase shifted by 21:/p will produce an output
voltage where the harmonics up to p times of the switching frequency are zero [7l].
Clamping capacitor RMS current
defined, the instantaneous
RMS
13
stress [72]:
stress is
When duty cycle and phase
shift are
dependent on duty cycle and load power
both
factor.
Maximum RMS stress happens when only reactive power is processed. Phase shift can also be
'Mit
te
optimized for RMS current
Fig. 1.9.
Sub-harmonic
stress, rather
PWM
PWM
m...t
modulation pattem for five level capacitor clamping
carriers
shift
phase shifted by 90 degrees are compared with a sinusoidal modulating
higher than the carrier, the corresponding switch
1.3.3.
PWM
has been optimized for output voltage harmonics.
reference producing the four gating signals for the four
is
leg.
modulatíon: Fig. 1.9 shows a typical sub-harmonic
modulation pattern where the phase
Four
than output voltage harmonics.
is
cells.
When the modulating
turned on.
reference
.
Dynamic Clamping Voltage Distribution
Success of the capacitor clamping inverter depends largely on the stability of each
clamping voltage, especially during dynamics. Unequal distribution of the clamping voltage
causes output distortion, and will subject the Switches to destructive voltage
With the modulation pattem defined
it
in Fig. 1.9,
and when the load
has been verified that each clamping voltage will tend to converge
matter what are the
with the inverter
initial
[74].
stress.
is
not pure reactive,
at its
nominal value no
conditions, as a result of the self-balancing
mechanism
inherent
~
14
1.4.
Snubbing Techniques for Multilevel Inverters
A snubber network serves such multifarious functions
as to limit the device di/dt and
dv/dt rates of change, to transfer the switching stress, to suppress the turn-on/tum-off spikes
as well as to control the
EMI,
not allowed by the device
is still
itself.
For
GTO,
excessive voltage or current rates of change are
When high capacity I_GBT is
concerned, snubbed operation
favored [99]. Enormous energy will otherwise be accumulated during hard switching,
making device derating
1.4.1.
etc.
inevitable to avoid fatal junction temperature in operation [lO0].
Dissipative/Regenerative Snubbers for Two-Level Inverters
Dissipative snubbers: Dissipative snubbers can be distinguished between conventional
and low-loss snubbers as summarized below. One snubber
differs the other in the
ways of
discharging the snubber capacitor or demagnetizing the snubber inductor [75].
0
Conventional snubber: The mostly used conventional snubber [76] [77]
1.10(a).
An
additional clamping capacitor (2CS<Cc<5Cs)
is
circuitry sothat to simplify the low-inductance designing task.
is
0
is
shown
installed for the
Snubber loss
is
in Fig.
tum-off
high which
the major factor limiting the switching frequency.
Low-loss asymmètrical snubber: Snubber loss can
'be
reduced by about
60% by
only one snubbing capacitor, as shown in Fig. l.10(b) [78]-[80]. Snubbing of the
switch
is
using
down
achieved by a longer path including Ce, V6 and Cs, typically 5Cs<Cc<l0Cs. The
large storage capacitor suppress the voltage spikes but also necessarily increases the path
inductance.
An
option
is to
use distributed capacitors for Ce. With either a clamping
capacitor or a storage capacitor in the network, the switching of one inverter leg can be
influenced by the other due to the coupling introduced by
‹›
common inductance.
Low-loss symmetrical snubber: The large clamping/storage capacitor as well as the resulted
mutual coupling are absent in a symmetrical low-loss
[83].
The price paid for the space savings
is
circuit, as
shown in Fig.
the less tightly controlled device voltage stress,
typically 1.5 times instead of 1.2 times with the asymmetn`cal one.
The presence of the tum-on snubber
makes a small
capacitance
is
l.10(c) [81]-
in the discharging path
resistance reasonable for Rs, typically 0.39.
_
of the tum-off snubber
Thus the actual snubbing
nearly doubled, depends on the impedance encountered in the current path
15
to the remote capacitor. Typically 1.5 times
is
This effect reduces
attainable in practice.
the local capacitor to nearly half of the value needed for the device.
As a result, the snubber
loss is also nearly halved.
Regenerative snubbers: Regenerative snubbers developed in the past can be broadly
classified into passive recovery
schemes and active recovery schemes as will be reviewed
shortly below.
l
‹
RS'
CC
RS
_
C
__
'E
V8
._
_
-“S1
LS
A
VA
'E' 'V
CS2
`
W*
v
V3
V5
‹
S
V6
V5
V1
_
V4
vA
7L
Ls”
Rs
.
vó
v
L,/2
'
V4
›
V1
V'
V2
V4
C
_"
____s2
..
ú.
(a) conventional
snubber
(b) low-loss
Fig. 1.10.
asymmctrical snubber
Major dissipative snubbers
(c) low-loss
symmetrical snubber
for two-level inverter.
Passive recovery schemes: Typical passive recovery schemes have been to replace the
discharging resistors in the dissipative snubbers with a coupling transformer as have been
proposed in [76]
efficiency and low
which
is
[84].
The
principal
maximum GTO
problem with transformer recovery
is
the lower
switching frequency due to the core reset time limit,
dependent on the transformer turns
ratio.
To avoid
saturation, core reset
by
introducing a proper resistor in series with the transformer in order to dissipate the energy
associated with the magnetizing current, or in the other instance,
by opening
the
freewheeling path with an active switch have been studied [85] [86].
Other schemes of this category are to replace the discharging resistors with storage
capacitors
which accumulate the snubber energy and
will then
be sent back to the load
during the turn-off process, as was proposed in [87]. The additional current during tum-on
together with the complexity of this circuit has been the major drawbacks of this scheme.
Active recovery schemes: The general idea of a typical active recovery scheme
the dissipative resistors in the dissipative snubbers with choppers
is to
replace
which feed back the
l6
recovered snubber energy to the
[88] is
shown in Fig.
A general trade-off
and
settling
1.11,
DC link, as have been proposed in [88]-[89]. An example
where C3, Lc and D, work as an inverting step up/dovvn chopper.
exists in the designing
among over voltage, over current of the devices
time of the snubber components as can be fotmd in any other snubbers.
Experiment on a
good dynamics.
l.5MVA
system proves that a open loop control of the chopper offers
A regenerative snubber is also installed for the chopper
Normally,
[87].
three phases share the chopper(s).
The power
rating
and in-turn the complexity of the chopper
to the inverter switching frequency.
of chopper recovery
is
Snubber energy recovery for
may therefore be appropriate to state that the success
It
low frequency
limited to
GTOs
operation.
in series: Series
_
connection of GTOS are the state of
the art technique for implementing large capacity utility inverters.
is far
actually proportional
is
The efficiency, however,
lower than the conventional line comrnutated ones due to the snubber
recovery becomes hence interesting. Collective [90] and individual
have been tested recently, and the
300MW AC/DC
converter
recovered energy
is
[9].
latter
one, as
shown
Regenerative circuit
is
[9]
recovery schemes
been used in a
in Fig. 1.12, has
GTO, and
provided for each
fed back through the series connected diode rectifiers to the
Dc
G'
rz
DC link.
|]
É
zš'
the
_
b
c,_l__
Energy
loss.
L*
~1
~
a
'
~1
.
CS'
.
ú
__*
Fig. l.l
l.
Chopper recovery scheme
for the
asymmetrical low loss snubber. Db and Dc interface
the
two other phases
1.4.2. Dissipative
As
[88].
Fig. 1.12.
Method of snubber energy regeneration
GTOs in series, which has been used in a 300MW
AC/DC converter [9].
/Regenerative Snubbers for Multilevel Inverters
far as the
for
-
snubbing of multilevel inverters are concemed, the
received the most attention from industry and research community.
NPC
inverter has
The snubbing of the
17
capacitor clamping inverter seems not a different issue but has not been reported yet.
The
following content reviews solely the existing work on NPC inverter.
Dísszpative snubbers:
The
an
fact that
NPC
inverter leg consists of
association simplifies the problem of snubber arrangement for
0 Low-loss asymmetrical snubber: Fig. l.l3(a)
two
cells in series
it.
shows a low-loss asymmetrical snubber
for
NPC inverter, which has been employed by_Siemens AG in a 3MVA GTO (2.5KV, 3KA)
liquid cooled
cell
and C2
300
Hz drive system [18][19]. The two low-loss snubbers work for CI, V1, V3
V4
,V2,
cell respectively, in the
same
principle as in a two-level inverter.
prolonged snubbing paths for the two inner switches
V23, CS4,
(Vlz, CS3, Vzz
,
Cs, for V3,
VB for V,5, V2) call for particular construction attention.
=1
__C]
_
V” L
V
Cs]
V A
_
v~
V
vn
vz.
IE
›
:
.`
_R
'_C2
“_
V
Ls2
V”
V VZ4
Â
\
C 54
_
_'
V A
Vi4
I-
I
A
vz
az" V¡^
F
(b)
IF£¡^
ç-:zh
-
-Ir
7
(H)
CS2,
E
'
~
and
'~
~
:
Vw
The
I
vz.
.z.
'
‹«›
‹d›
Fig. 1.13. Different dissipative snubber arrangements for
0
NPC inverter.
Conventional snubbers: Fig. l.l3(b) shows an arrangement using conventional snubber for
NPC inverter which has been used for traction converters in Europe [75]. The four tum-off
snubbers directly mounted for each switch
may
give rise to serious coupling between the
l8
cells.
is
Aside fromthe outer blocking device discharging when
neighboring inner device
tumed-off, the outer blocking device can further undergo a unnecessary voltage dip
(associated loss)
shown in Fig.
°
its
when the other outer device is turned-off. With the modified arrangement
1.13(c
the
),
two
cells are
decoupled.
Symmetrical low-loss snubber: As shown in Fig. l.l3(d), the symmetrical low-loss snubber
can also be applied to
Note
NPC inverter working in the same way as in the two-level case [91].
modules are no longer applicable due to the reactor position.
that two-device
Any
Regenerative snubbers:
theoretically
be modified
dissipative snubbers that are
into regenerative
ones [92]
[93].
A
reported recently [65] [94], by extending the idea in [89], as
circuit, LS, serves as the
CS3
CS2.
and
CS, for
G, while
CS2
and
CS4 for G2. LS3
is
and
inverter can
successful example has been
shown
in Fig. 1.14.
In this
mitigated. This circuit has been used in a
Lú
limit the
tum on discharging of CS3 and
the recharging paths establishedby CS2 and CS3
tum-off snubbers CS4 and
for rolling mill drives
NPC
tum-'on snubber for G, and G3 while LS4 for G2 and G4. For tum-off,
The outstanding benefit of this snubber
for theouter switches
used in
CS,.
The problem of indirect clamping
choppers and the reported efficiency reaches 97%.
_l_
'
___
*ld
_
V
E+;
W
dc
___
Lú
Dc2
:1}~
C s2
S_
lläíllãi;
É:
Fig. 1.14.
A
thus
IOMVA back-back GTO (6-inch 6KV/6KA) system
by Mitsubishi Corp. of Japan. The whole 24
'
is
regenerative Snubber Circuit for NPC Inverter.
GTOs
share the four
19
Snubber Problems
1.4.3.
Snubbervloss:
All dissipative snubbers reviewed above consist of energy storage
components, which have to be discharged or demagnetized periodically. Snubber loss of an
inverter leg is given
by
(l.1) [75]:
1;={õ-Ê-cs-V¿%+%-Ls-(1%Q+1,Ê,)}.¿
(1.1)
where
CS:
Tum-off snubber capacitance
ITQ:
Actual turn-off current
In:
Free-wheeling diode reverse recovery current
Vdc:
LS:
fc:
DC link voltage
Tum-on snubber inductance
Switching frequency
6: Loss factor (c=3 for the conventional snubber and o'=l for the
The snubber
and
is
low loss snubbers)
loss is square proportional to the current switched
and the voltage blocked,
proportional to the frequency operated. With a low-loss snubber,
2% of the whole power installed for a 300-400 Hz system.
applications, this large
it
may occupy
1%-T
In high power high performance
amount of heat transfer becomes highly objectionable
resulting in
low
efficiency, limited frequency, and moreover, significant cooling and construction difficulties.
Regenerative snubber allows for improvement in efficiency. However, frequency
increase will necessarily be limited by the complexity of the recovery circuits.
Voltage/current overshoots:
Most snubbers,
dissipative or regenerative, use a polarized
series inductor for voltage transfer during turn-on,
current transfer during turn-off.
The tum-on and turn-off snubbers
other, instead, each is involved in the operation
0
The energy accumulated
and a polarized
parallel capacitor for
are not independent of each
of the other.
in the series inductor during turn-on will
be transferred to the
damped resonance
across the device causing voltage
in the parallel capacitor during
tum-off will be transferred to the
parallel capacitor during turn-off in a
overshoot.
0
The energy accumulated
series inductor during turn-on in another
current overshoot.
damped resonance through
the device causing
20
When
inductor or capacitor with higher values are used for optimizing the switching
loss, the voltage/current
result
overshoots and also the snubber loss are amplified accordingly. The
of such overshoots
voltage and around
is
the derating of the switches, typically
by 40%-60%
in the
nominal
20% in the nominal current depending on the thermal condition.
Turn-on and turn-off snubber interactions can be decoupled by a specific arrangement
[95]-[96], as
shown
in Fig. l.l5. Obviously, the large electrolytic capacitors for voltage
ti
51
ii
overshoot limiting lead to voluminous and expensive solution.
.
T
Vdc
Fig. 1.15.
Snubber circuit free of voltage/current overshoots across/through the main switches.
Snubbing diode
to the following
°
°
issues:
problems
The need for a snubbing diode
in the turn-off snubber gives rise
[98]:
Forward recovery of the snubbing diode contributes
to the first turn-off voltage spike
during the rapid decreasing of the anode current, which
is
known as VDSP for GTO.
Additional construction inductance in the snubbing path due to the mounting of the
snubbing diode causes another term to the first tum-off voltage spike.
‹›
Reverse recovery of the snubbing diode interacts with the parasitic inductance of the
discharging resistor and causes a negative voltage spike (third tum-off voltage spike).
‹›
In the case of asymmetrical snubber, snubbing diodes in a non-commutating
become pre-flooded when
the
common
potential
voltage stress caused by a cornrnutating leg.
very high stress
if the
switch
is
is lifted
due to the
The pre-flooded diodes
turned on at such moment [80].
common
will
.leg
can
inductance
be subjected to
'
21
_
Turn-on snubber loss: Tum-on
snubber inductor in the power circuit
is
required by
all
snubbers, which causes considerable .steady state loss.
Snubbíng complexíty for devices
individual tum-off snubber [7], which
Energy recovery
calls for circuitry
Prolonged snubbing path
V
Each device
in series:
is
always oversized to
of great complexity
in a cascading string requires
assist equal voltage sharing.
[9] [90].
'
-
diode clamping multilevel inverter:
in
All the switching
arms, except for the up-arm of the up-most cell and the down-arm of the down-most
normally composed
of- several
or the freewheeling path.
The
cell, are
switches and several diodes in series for either the forward path
internal inductances as well as the
mounting inductances of
these additional switches or diodes in the forward or freewheeling path will necessarily
aggravate the voltage spike problem.
Prolonged snubbing path
-
in capacitor
clamping
inverter:
All the switching cells,
except for the inner-most one, always involve a clamping capacitor in the snubbing path.
Similarly, the internal inductance as well as the
capacitor will add to the voltage spike problem.
1.5.
0
mounting inductance of
clamping
_
Conclusions
When adequate capacity and performance of an installation can not be fulfilled with the use
of single device, associations of devices, conveiters and
-
this
series association
of
cells
has led to
new
cells
have been developed. The
topologies including the diode clamping
multilevel inverter and the capacitor clamping multilevel inverter, both promise high
voltage operation with reduced harmonics without necessitating heavy magnetics.
0
Snubbed operation
is
needed for
GTOS and is favored by high capacity IGBTs. The use of
snubber leads to objectionable problems, which become more pronounced for multilevel
inverters. Frequency-increase
with regenerative snubber
is
limited by the complexity of the
recovery circuitry. The pursuit for an advanced solution replacing snubbers in multilevel
inveiters for high frequency operation constitutes the major objective
of this thesis.
22
Chapter 2. True-PWM-Pole Two-Level Inverter
~
Abstract: This chapter reviews the state of the art of the soft switching inverter circuits
for high
power applications. The transformer connection True-PWM-Pole
in details as
results
is
analyzed
an altemative for the Auxiliary-Resonant-Commutated-Pole-Inverter (ARCPI),
of which are verified with a
5kW half bridge prototype.
auto-transformer and capacitor connection
2.1. Soft
inverter
True-PWM-Poles
Topology variations including
are discussed.
Switching Inverter Circuits Review
Switching process defines the operation condition of the device and holds essentially the
most
critical position in
power
electronics.
The
different switching types as well as the
representative soft switching inverter circuits [101] [102] are reviewed briefly.
2.1.1. Different
Types of Switching
'
.
Besides hard switching which
is characteristic
of tum-off with
full
load current and
turn-on under full voltage, other three types of switching are identified as follows [102][104]. Typical switching
waveforms
are illustrated in Fig. 2.
Inductive turn-on/capacitive turn-ofif'
the
tum-on
1.
An inductor is in “series with the device to reduce
loss while a capacitor is in parallel with the device to reduce the
tum-off loss. The
savings in device losses are penalized by the troubles imposed by the trapped energy in the
reactive elements.
Inductive turn-on/zero current turn-off'
.
An
inductor
is
in series with the device to
reduce the tum-on loss while the tum-off occurs at zero current with zero loss by extemal
circuit
means. Tum-off voltage spike due to the rapid voltage transition from the inductor to
the device after the device tum-off and the associated loss during the device reverse recovery
are characteristic of this switching type. Series inductor in the
main path as well as the charge
dump of the parasitic capacitance during tum-on (Power FETS) reduce the efficiency.
Capacitive turn-ofl/zero voltage turn-on:
A capacitor is in parallel with the device to
reduce the tum-off loss while the tum-on occurs
Tum-on
at zero
current spike due to the rapid current transition
voltage by extemal circuit means.
from the capacitor
to the anti-parallel
23
diode as well as the associated loss-during diode forward recovery are characteristic of this
switching type. Demagnetization of parasitic inductance during tum-off leads to voltage spike.
Logically, a forth switching type characteristic of zero voltage turn-on and zero current
turn-off should exist [105]. For the case of inverter
due to the greater complexity and
voltage
current
P
~
(b) Inductive tum-on,
tum-off
capacitive turn-off
Fig. 2.1. Switching
vglmge
voltage
current
'
Hard tum-on, hard
has not yet been investigated probably
less practical interests.
voltage
current
(a)
it
waveforms
current
P
(c) Inductive
P
~
tum-on,
(d) Capacitive tum-off,
zero voltage tum-on
zero current tum-off
for different switching types.
All snubbers are of the first switching type with Inductive turn-on/capacitive turn-ofl
Among the two soft switching types, the second type of switching with inductive turn-on/zero
current turn-ofl has been popularwith
1960s and l970s [106]-[l08],
all
the forced
commutated
thyristor circuits during the
called today Zero-Current-Switching
it is
(ZCS)
for short.
For
gatezcontrolled devices, the third switching type with Capacitive turn-ofi'/zero voltage turn-on
has "been extensively explored and has been abbreviated as Zero-Voltage-Switching (ZVS).
Recent work [109] [110] have suggested the use of the second switching type for IGBTS due
to the
growth in the turn-off switching
loss as the junction temperature increases.
When zero
concemed, aiding network
voltage switching
phase or per-inverter
is
may be configured on
basis. Per-phase positioning yields the variant
per-
of the resonant pole
inverter family, while per-inverter positioning yields the resonant link family.
The resonant
pole family generally has more elements but individual phase works autonomously. In
comparison, the resonant link family suffers from severe coupling between phases.
2.1.2.
~
Resonant DC Link Inverter Circuits
Perhaps the most mature circuit of this family
Link-Inverter
(ACRLI)
[1l1], due to
its
is
the Actively-Clamped-Resonant-DC
low component count and high development
depicted in Fig. 2.2. However, the discrete nature of the resonant
low frequency output voltage has
DC
-
status, as
link requires that the
to be synthesized following a Discrete-Pulse
Modulation
24
(DPM)
[112].
And
a resonant link frequency that
PWM
frequency of the
inverter is required to attain
by imposing greater number of pulses onto the
exceeding 300
[113]
[1 14].
kVA
200
comparable load harmonics level or
DPM inverters need to compensate for the inferior resolution
control bandwidth performance.
rated in excess of
four to six times as fast as the operating
is
load. Presently available
kVA, the size, cost and cooling of the resonant inductor become
Í_-
Clamping
capacitor
1.3-1.5 times the
I
F
Inverter
main devices
_Y_
__- Resonaf
DC voltage
capacitor
04
°_|
V
Q?
III
,t
__
~*'Í‹§›3~I*lÊÉf~
°_|
Ó
ffa4
Fig. 2.2. Actively-clamped-resonant-DC-link-inverter
PWM
operation
was explored
meanwhile, the considerable amount of
etc.
DC voltage.
switch
Resonant
inducmr
in
limiting issues
clamping
°-l
bl
xzzúfizó
are
with link frequency up to 70-l00kHz. For inverter ratings
Main device blocking voltage is clamped to about
ACRLI
ACRLI inverters
[ll5], but
PWM resonant DC
(ACRLI).
was not preferred
[l16]. In the
link circuits [117]-[1l9], [146]
need yet to be examined further for high power applications.
2.1.3.
Resonant Pole Inverter Circuits
The resonant pole family
is
generally realized
by loading the
inverter inductively at the
switching frequency, regardless of the actual load current condition.
been studied for
this
purpose during the past decade [120] [l2l].
A variety of circuits have
Among which the Auxiliary
-Resonant-Commutated-Pole-Inverter (ARCPI) [122], as shown in Fig. 2.3, has been deemed
the
most plausible
circuitry
and
waveforms
of the
full
in high
PWM
power application area [123]
capability.
for a switching cycle are
ARCPI consists of
these
two
[147],
The phase plane of
shown
due to
its
small power auxiliary
the resonance and the relevant
in Fig. 2.4 'and Fig. 2.5 respectively.
critical issues:
The
control
25
A
“
Ç
D|
Á'
C¡-1
°_|S|
_
S”
Vdc
í'
aí
5°'
1
3-
Dm
Iboost
LI
'load
nf
DSM
Í
D2
52
°_|
f
_
\
/
Cn
I
\
Z PWM gating
i
_,
.Ná
/
\
.
'l08d)
| | 1 i
>
\
\ \
\
/
, /
I
___
/
/
/
Phase plane representation of the resonance
Fig. 2.4.
signal
=
t
Í
i
E
l
lãarñp
š
E
X
Sú
*dead
'
E
l
ati
vvvv
I
I
4
S1
I
.
v
Ill"
:ff
D2 to §|
É
;
oommiltati n
š
*
a
f
z
›
z
=
É
z
=
5
.
É
'
¡Lr
Â
â
5
Fig. 2.5. Relevant
tmmp
____|_,-:____
/
between L, and Cú during a switching cycle.
Â
S2
Í
¢
/
Vcfz
boost
Inverter (ARCPI).
¿
\ \
/
-_.
_/
' | | 1 1
\
Fig. 2.3. Auxiliary-Resonant-Commutated-Pole-
\ /
tramp=0
,
_\
-
C2
.
¡Lr
AB
=
l
`
Iboost
Í
š
šlboost
I
IL
¡
1°
D2
mmutatin
¡¡
›
I
wavefonns of the ARCPI during a switching
cycle.
Control: For diode to switch commutation, before turning-off the triggered
switch, the corresponding auxiliary switch
switch current
is
current valued-at
allowed to ramp up
I,,00S,.
must be turned on
until the triggered
Such ramp stage guarantees
in
main
advance so that the auxiliary
main switch
carries
that the pole voltage will
an adequate
swing
to the rail
level taking into account the uncertainties especially the losses in the resonance process [81]
[124].
Without this
stage, resonant capacitors
can not be fully charged or discharged
of the resonance, and considerable loss will be caused
if a
switching action
is
at the
imposed
end
[125].
Consequently, to maintain always an adequate level of I,,00s,, the ramp time tmmp must be
controlled to follow the load current. Precíse measurements of the load current as well as the
26
resonant inductor current become therefore mandatory, which will increase the cost and
reduce the
reliabilíty [I26].
As
1500” current
the
inductor current ramps up very fast, this control
always small (5-I OA) and the resonant
is
is
hard
reverse recovery current will enhance the commutation but
Zero voltage switching
is
inverter applications including
further affected
by the
to
be implemented [I27]. Diode
can not be coimted on.
it
DC center tap potential.
motor drives, the center tap potential
is
Generally, in
self regulating at
1/z
Vdc
due to the equalization of charge in and out of the respective phases as the direction of each
phase current altemates between positive and negative. However, when low frequency high
output current
Hence
[128].
will
be
supplied, significant drift
is
tmmp
must also be controlled
lost if Iboos,
to
is
likely to
happen during a sustained
compensate for
this drift.
interval
Zero voltage switching
remains unchanged.
tdead Control: As shown in Fig.
2.5, after turning-off the
main switch must be turned on between
charged and the anti-parallel diode
starts
instant
main
switch, the opposite
A, where the resonant capacitor gets fully
conducting,
and
instant B,
where the resonant
inductor current decreases to the load current level and the anti-parallel diode stops
conducting, as expressed in (2.l).
2
“L”
acos[
where
Ibama)
V
,/(ff +‹1z,.,..zz›>2
“'°
= _._.l_
t/20,4
is
S
]Stdead
~
2
Ú”
acos[
the resonant frequemry,
V
Ibama)
]+Ib0m,Í/i
,/‹-ff +<1zmzÛ›2
Z° = -ÊL
\l2C,
is
(2.1)
df*
the resonance impedance.
From (2.1), both intervals are not related to the load current and tm, can ideally be set to
constant over the whole output period. However, the following uncertainties will be
influential and the preset constant tm, can go outside the actual range of instants
0
A and B.
Variation of the parasitic resistance due to heating effects.
° Variations of the input
DC voltage as well as its center tap
i
potential.
As a result, voltage status of each main switch must be supervised to secure more robust
zero voltage switching without regard to any circuit parameter variations [128] [I29].
Mathematical analysis for the
ARCPI is given in Appendix 2.1.
'
27
2.2.
True-PWM-Pole Inverte_r Circuit and Operation
With a view
to reduce the control complexities
inverter [130] using transformer comiection, as
J-
0
4
Dal
‹›|
D1
51
IS'
°-|
Dsa2
Cri
:
t3
VN:
'Í
+
i
~&~
Í
vd
,.
-
L'
Nz.
i
Da2
'
p
1
S2
_
D1
-
t
_? _ _ _ __(_k=_"*1““)_
,
,
fil
N|
Dal
an altemative.`
2.6, is studied as
iuh
Dal
IS
sa2
shown in Fig.
x
JL
of the ARCPI, a True-PWM-Pole
.
í
¡_k,'
_ (__'_'°í"Z___
ti-
_
I
“"'
Cn
Í]
t5
t9
Í1
›Vcú
Dsal
sal
is
im
É
X
I
1
\-fx
Fig. 2.6.
Transformer connection
inverter scheme.
`
Tme-PWM-Pole
Fig. 2.7.
'
V
Phase plane diagram of the resonance
between L, and Cú during a switching cycle.
Prior to discussion of the commutation process, the following conditions are assumed:
0
Positive load current
0
Transformer
rail level in
im is flowing and remains constant during the commutation.
is set to
ratio
ensure sufficient energy for the pole voltage swinging to the
the presence of commutation losses, as will be discussed in subsection 2.4.
0
Construction parasitics, switching transience and transformer imperfections are neglected.
0
Main switch turn-off and auxiliary switch turn-on happen
the
at the
same
instant as decided
PWM scheme, while the main switch tum-on happens until the detected voltage across
the switch declining to zero. Conduction interval of the auxiliary switch
covering the
âèl
is
constant
maximum commutation duration as will be discussed in subsection 2.4.
With reference
relevant coimnutation
the
by
to the phase plane
waveforms
commutation of the
diagram of the resonance shown in Fig.
in Fig. 2.8,
2.7, the
and the commutation step diagrams in Fig.
inverter leg during one switching cycle consists of the next steps:
2.9,
28
A
PWM gating signal
|;
_
1
_
(Ú
Ê:
.
_____
'_'
.-_...__
dead
2
Vl
.W
o§ 5
2
-
Y
Y
V
V
Y
Ê
oommu non
Vcr2
Y
..
_
.
_
_-.
D2
wmmutan
S1 1°
fi
ã"_"__'__"_í_`
='
'load
Y
.___
_
_
.`_,_m_m_,..W
5'
Fig. 2.8. Relevant
D,,2'.
v.
ls ló
*3 14
-
¿;
`.,._.
commutation wavefonns of the True-PWM-Pole inverter during a switching cycle.
Step I
(to-t 1): Circuit
Step 2
(t 1-tz):
steady
Freewheeling diode D2 carries the load current.
state.
S2 is turned off and S22 is
tumed on at
Step 3
among
current
~
iurises to the load current level at
and
C,2 is
C,, is initiated.
Step 4f(t3-t4):
vC,2 rises to V,,c at
t2
charged while
enhances the charging current and therefore
leading to blocking of D2. Resonance
C,, discharged.
facilitates the
(t4-t5):
iu falls to load current at
t,,.
Recovery current of D2
commutation process.
leading to conduction of D,.
t3
zero voltage. Rapid current transfer from C,2 and C,, to D,
Step 5
leading to conduction of Da2 and
'
.
(t2-t3):
L,, C,2
t,,
DC link voltage Vdc enforcing
N2 sees a positive voltage of kV,,c which joins the
decreasing in D2
5
Then
S, is turned
on
at
may cause oscillation.
D, then stops conduction and
S, starts
u
canying current.
Step 6
(t5-t7):
another steady
Step 7
C,,, C,2.
Da,”. C,, is
Step 8
extinguishes at
state. S, carries
(t7-tg): S,
between L, and
of Da, and
iL,
t5
allowing for tum-off of S22 at
tumed off and
Sa,
is
turned on at
N2 sees a negative voltage of
charged and C,2
(tg-t9): vC,, rises to
is
Vdc at
stray/intemal inductances of the paths
(t9-t 10): iu falls to
Circuit reaches
I
load current.
t7,
kV,,c after
which
innitiates
turn-on of
Sa,
a resonance
and conduction
discharged.
tg
leading to conduction of D2.
zero voltage. Rapid current transition from C,, and C,2 to D2
Step 9
t6.
may
Then
S2
is
tumed on
at
cause oscillation due to
.
zero at
t9
allowing for turn-off of Sa, at
the original steady state. D2 carries load current (same to Step I).
t,,,.
Circuit retums to
11
1
í
;{n2@Dsn2
ÃDÚ ãhl
‹^'
É
+ N2 -
Vdc
___
Crl
Lr
T›
lu
.N]
'‹...,.¬..,...f
_
É
f
'load
al
f'*'
NZ-
Vdc
.
N..
A
°'l
^
ii,
Saz W Dsaz
S1
¡
Lr
¬›
š
.¿.
7.
11
fl›
N]
2:..
Cr]
‹*=
:i
fiãszl
%'"` ED”,
SMDS”
Cn
CQ
Dal
f'
:Í
šl
Step
1 (to-tl)/step
9
Step 2
(tg-tm)
‹À'
À.
H
um
s
(t,-t,)
fiê
Vdc
.'
S¿|
.I
U
E!
cn
›‹›
zâf-‹'
NZ-
ff
._‹^
Dsal
s al
ä
Thgd
IN¡
›
;§z›
load
'
al
Y
2
:›
r2
,_
Step
Step 4
3'(t2-t,)
"'¡
ÍÍ
í
(t,-t.,)
‹›4
F'
S¡¡2
ir
al
'*=
gê
A
Cn
(I-,IAI
-
1
A
°=2
'
I
CH
z-
vdc
¡í§z=z=z=z=:ââ
¬«.
v-
L,
mí
.N¡
¬‹.
Sal
Dsal
W...
z...
-
5-*
nv G.
fil
4
anal,
Step 5
+ Ni .
Vdc
..z.`.`›-
››....z,â
À
D2 C Í2
Dsal
Dal
Step 6
(t4-ts)
›
À
Á
D2 Cú
I
(ts-t7)
r
A
°{
Szz
l
DB2
Dszz
fr
A
'
às
2:1.
'
_
+ N2 _
Vdc
fl
¬›
E
gâ
,_-.:'
í
.
.
D.
Da2
H
ø
Êà-Í
1
+ N2
Vdc
=¿.¡.¿...¡¿,...§
:L
‹›‹
Snz
....z
p
......zzz.zz...
,.....W..
ãi
S
*,-
'
(ff^
_
..._z-‹-g,›
éh
,I
Da;
.@_f_
IQ
.
Szlvm
,:=›z:
.
‹
“2
›
‹›4
Sz
'Ê
zi
¿;-
0
'¬f¬:
._._
1
Step 7
Fig. 2.9.
Step 8
(t,-ts)
Commutation
step diagrams of the
True-PWM-Pole
(rzërg)
inverter during a switching cycle
30
In summary, for the
True-PWM-Pole
inverter circuit, the
main switch works with zero
voltage tum-on and capacitive tum-off, whereas the main freewheeling diode works with zero
voltage turn-on and zero current turn-off. Superior to the conventional snubber, the capacitive
tum-off loss of the main switch can be minimized by optimizing the resonant capacitor to
end. Meanwhile, depending
on
this
forward recovery property, the snap-on of the main
its
freewheeling diode does not introduce any considerable loss.
Moreover,
all
the auxiliary devices
work with zero
current tum-off.
And
yet voltage
is
only reapplied after tum-on of the opposite auxiliary switch and no voltage spike can occur.
By
comparison, although the auxiliary devices in the
ARCPI
DÇ link voltage,
block half the
they suffer from tum-off spike which calls for the use of additional snubbers [13 1].
Besides, despite the bridge configuration, the tum-on of the auxiliary switch
is
actually
snubbed by the resonant inductor since the opposite freewheeling diode carries no current
beforehand and
its
reverse recovery
is
negligible. Transformer excitation is reset to zero after
each cornmutation and no magnetic accumulation can happen.
In particular, by designing the transformer ratio less than I/2,
source valued at (1-k) Vdc which
is
an auxiliary voltage
higher than Vdc/2 becomes available which delivers
sufiícient energy for the resonant pole to swing to the rail voltage.
and the associated control complexities with
the
ARCPI are no
Thus
the “boost” stage
longer necessary in this case.
The auxiliary switch can be "simply turned on at the same instant as the main switch
is
turned
off Losses íncurredƒrom the extra turn-on/turn-ofi" actions of the switch are further avoided.
2.3.
True-PWM-Pole Inverter Commutation Analysis
The following assumptions
°
Resonance
ang 1 e
fr equency
a› L
T, quality factor Q=-oíi
‹›
is
are
made
1
mo = U-Í=CÍ= , resonance impe dancezb =
.
_
J;
L,
swr tchmg cyc 1 e
.
,
.
infinite neglecting losses in the resonance process.
Unit current i= iZ0 /Vdc, unit voltage;
2.3.1. Total
in the analysis:
= v/ Vdc, unit time
Í
= two
.
Cornmutation Duration
For diode to switch (D2 to
duration t5¡=t5-t,
is
given by
(2.2):
S,)
commutation, the unit value of the
total
comrnutation
31
k
d
d
a›0t51=(l%;5+(1r-acosm)+T+0¡%
Í]
For switch to diode
is
given by
\/1-2/c
Í;
(2_2)
D2) commutation, the unit value of the total duration
(S, to
(2.3):
t,,,=t9-t7
'
a›0t97 = 11- acos
zk
+ÍlOad
1-k )
(2
-acos
2
'
-Hiload
2
`
.
_
.à
+ [1-2k+i¡0ad2 -l¡0ad
(23)
-
Equations (2.2) and (2.3) are graphically shown in Fig. 2.10(a)(b).
16.893
“
F
Vá
14.601
~
r
~
41-rw
.«...
°)0ts1
wzw.
--‹.›T‹".›
2
3:
10.011
1.125
í"
5.433
›¿.z=;;‹.
3.142
///
/
/“\+
'
12.309
0
'
0.5
3.104
l
í
1.5
2
-_*-_- I
"('
3.142
03051 2.011
Í
Y
1.455
1<=o.3s
'
0.393
k=0.5
2.5
0.33
3
i
Diode
to switch
0.5
l
commutation
(b) Switch to diode
ts,
and
tg,
2
2.5
3
commutation
with load current and transformer ratio.
Obviously, for diode to switch commutation, the
On
_
1.5
¡1‹›a‹1
Fig. 2.10. Variations of commutation durations
current.
_
.
0
¡1‹›za
(a)
k=0.35
‹› kzoz
2.ss
:_
`°`
F
total duration increases
with the load
the contrary, for switch to diode commutation, the total duration will decrease
with the load current. Both will increase with decreased transformer ratio.
2.3.2. Auxiliary
Switch Peak Current Stress
For diode to switch (D2 to
S,)
commutation, the unit value of the auxiliaxy switch (Sú)
peak current isapl can be represented by
(2.4):
32
U; =(Í.;+1-k)
(2.4)
For switch to diode (S, to D2) commutation, the unit value of the auxiliary switch
peak current isapz can be represented by
ISWZ =(J(l-k)2+z¡0ad
-zload)
3.125
'
2.6
/
/
Ísapl 2.015
1.55
1.025
0
0.5
1
065
_"*_““" ++
-×-
°-54°
**
-×-
0.244
(2.4)
and
2
0.143
k=0.5
2.5
3
0.041
I
0
0.5
1.5
1
2
(b
)
3
Switch to diode commutation
of the auxiliary switch peak currents with load current and transformer
(2.5) are represented in Fig. 2.1 1(a)(b).
commutation, however,
2.5
ima
it
ratio.
For diode to switch commutation, the
peak current of the corresponding auxiliary switch increases with the load
to diode
1‹=0.5
1<=0.35
"' k=0.4
fl_ k=0.45
___.
Diode to switch commutation
Fig. 2.11. Variations
1‹=0.45
`
Íloâd
«(a )
35
k=o'4
1<=0
ÍSHP2 0.34ó
I
1.5
(2.5)
0.447
*>'.
0.5
(2.5):
%
165
(Sal)
will decrease with the load current.
current.
For switch
Both will increase
with reduced transformer ratio.
RMS Current Stress
The resonant inductor RMS current stress over switching period resulted from diode to
2.3.3. Auxiliary
Switch
switch commutation íbpmu can be expressed by (2.6):
I
'
.
Biblioteca Univetsštária
+}Â- jáz
À*
UFSC
33
resulted
from switch to diode
[zíš +(1-1z)s¡n(í)]2âí+íl_.-ƒáfz [J1Í2?-1zí12âí
where:
11
“buzz/(1“k)
k
-
Lz
=fi-0°0S(§)
Lg =(§,,Í+¬/1-21‹)/k
Similarly,
the resonant
commutation iLm,ms
expressed by
is
É
1
Jöfz
_ _
_
current
(2.7):
í
'r
(zbmms) -TIO
RMS
inductor
_2_
[z'¡0ad+(k-1)sin(z)-f¡Oad¢0s(:)] dz
_
(21)
_
[-,/1-2k+(z¡0ad)2 +z'¡0ad +1‹z]2dz
›«
.
where:
1-k
k
.Í¡=7Z'-¿l(I(Bí'-Í-d(3(Bí'"'Í2
__
J‹1k›+‹z,m,›
Jz =‹J<1-1‹›2
The
-
+<í;›2
_
2
RMS
switch to diode commutation
z-Lmmz
[fl
(a)(b).
2+z¿
-
2
t
-Z)/k
auxiliary switch
shown in Fig. 2.12
2
t/(1/‹›+‹z,m,›
2
¡
current during diode to switch commutation
Sanrms
are equal to
,-
Lrprms
The resonant inductor RMS
and
,-
Lrnrms
respectively,
current can then be described
aprms
and
which are
by (2.8):
(2.s)
34
I
277
k=o.3, T=9o
k=o.4, Í=9o
-0k=o.s, j=9o
<>- |‹=o.3, 3“=45
-vt-
I
076
-0-
i‹=o.4,
i
Sapms
í_____
,/A
//
/
o.õ12
o 41
Í=9o
r=9o
r=9o
¶=4s
k=o.4, T=4s
}k=0.5,
0092
¡Sanm1s 0.069
\.I
o 047
0
0.5
I.S
l
25
2
o.oo2
3
L008
0.509
L506
2.004
2.502
_*
3
'load
diode to switch commutation
Fig. 2.12. Auxiliary switch
¬
:i
0.011
íioad
(a)
'Í`=45
I
o 024
o zõs
0 066
-N- '|<=o.3,
-fk=o_4,
-0i‹=o.s,
4)- |<=o.3,
-0-
0.lI4
/
T=4s
k=o.s, T=45
0.874
0136
'
-1-
(b) switch to diode
commutation
RMS currents related to the load current, transformer ratio and switching cycle.
An auxiliary switch is subject to the diode to
switch commutation current or the switch
to diode cornmutation current altematively at the fundamental frequency in accordance with
the load current direction.
switch
RMS
commutation,
From
Fig. 2.12, for diode to switch
commutation, the auxiliary
current increases with the load current. Nevertheless, for switch to diode
it
will decrease with the load current.
Both
will increase with reduced
transformer ratio or reduced switching cycle.
2.4.
True-PWM-Pole Inverter Designing
2.4.1.
Transformer Ratio k
When
losses in the resonance process (device conduction loss, resonant inductor loss
and resonant capacitor loss
as
shown
in Fig. 2.13.
To
etc.) are
considered, the actual phase plane
guarantee that the pole voltage can
still
becomes compressed,
reach the
rail level
which
ensures zero voltage switching in this case, the transformer ratio k should 'meet (2.9):
V
V
Vdc(1-k)-f z-fã
(2-9)
35
Í^
=
|
'
Actual phase plane
considering losses
_»iiii --‹_1‹›_fiš«›_Â<&-1f›i.Tz«2--_
Í
__
Ê;
›Vcz2
_
Fig. 2.13. Actual phase plane for the resonance after considering the losses in the process.
H
Where
w L
Q="(;¿_r
and
R represents the equivalent resistance in the resonance loop. Equation (2.9)
can be simplified to (2.l0):
-
~¬-.,
ul"
-1
kSl___7.[..
M2
8Q
(2.l0)
When the transformer ratio is set less than
1/z
according to (2.l0) taking into account the
losses in the resonance process, zero voltage switching is then guaranteed Without any
additional
measurements or control complexities. Such extra freedom in transformer
deemed the most distinguished feature the True-PWM-Pole
2.4.2.
Resonant Frequency
ARCPI.
co.,
The resonant frequency should be
set
by optimizing the
auxiliary switch according to Fig. 2. l2(a) based
2.4.3.
offers over the
ratio is
RMS
current stress of the
on the switching frequency of the system.
Resonant Capacitor C, and Resonant Inductor L,
The resonant capacitance should be optimized
for the
_
main switch turn-off
loss [132].
Based on the resonant frequency and the resonant capacitance, the resonant inductance
decided.
is
then
36
2.4.4. Auxiliary
Switch Gating Signal Width and Minimum
The minimum width of
maximum
the auxiliary switch gating signal
must be
set
above the
value of the commutation duration, as demonstrated in Fig. 2.l0(a). In the same
sense, the inverter
minimum
PWM ON/OFF time
this value.
2.4.5.
PWM ON/OFF Time
(t,-t,
in Fig. 2.8) should also
be
set
above
1
Rating of the Auxiliary Switch
Due
to the zero current switching in the auxiliary circuitry
and due also to the high
switching frequency with respect to the thermal inertia of the device, the rating of the
auxiliary switch should be chosen according to
However, auxiliary switch peak current
peak output current
rating,
which
stress as illustrated in Fig. 2.12(a).
2.1l(a) should not exceed the device
illustrated in
normally
is
RMS
its
25%
higher than the device peak switching
current in the case of IGBT.
Aside from the transformer
.
.
ratio that is attributed touensure zero voltage switching,
designing of the resonant parameters
is
always a compromise among the
switching loss, device rating and duty cycle loss
(DC
many
factors
voltage utilization) etc.
such as
Practical
designing shouldbe oriented to serve the specific designing purpose where one particular
requirement may outweigh the others.
2.5.
True-PWM-Pole Inverter Experimentation
A proof-of-concept 5kW IGBT half bridge
built
inverter, as
modulated with normal sub-harmonic sinusoidal
the prototype are
shown
shown
in Fig. 2.14, has
PWM modulation. The specifications of
in Table 2.1. Designing results
of the resonant and transfonner
parameters according to sub-section 2.4 are shown in Table 2.2.
Table 2.1. Prototype specifications
DC input
V,,c=420V
voltage
Output
pgwer
Output voltage
_
P0=5kW
Load current
been
Vom,
Modulation
=l06V
index
I°_,,,,,
Switching
=42.5A
frequency
_
M=0. 78
f,=6.5kHz
37
Í
I
I
c
ú_
:_
L
li
Dul
I
Ã
ZS
HKÊS
Dm
Szz
D'
S'
Dal
°-|
_
~¬_- g
CH
:
VN:
'
+
~
‹›
_
.Nz
Vdc
L¡
.
.N|
C2
K}
u
1
1.
Fig. 2.14.
,
E
*W
Dz
Sz
*°
cf
C¡z
'
Ro
V
13°”,
Dsal
Sal
c.
ED”
Lf
A
.
L
5kW IGBT half bridge inverter.
Diagram of the
Table 2.2. Resonant and transformer designing results
M
x
~
Resonant
1.
capacitor
maximum tum-off loss 4W.
Resonant
I.
inductor
on air core bobbin,
Auxiliary
1.
Transformer
60 tums Litz wire (7 strands
Capacitance: C,=0.luF,V2. Type: low-loss polypropylene, 3. Estimated
ISAWG copper wire wound
Inductance: L,=l2uH, 2. Structure: 36 tums
Transfonner
(15 strands
Current rate of change 20A/uS.
3.
k
ratio:
24AWG)
=0.4, 2. Structure:
in the
24AWG)
Two
in the
secondary
in parallel
each made up of
primary and 24 tums Litz wire
wound on E65/29
ferrite core,
3.
Allowed equivalent resonant loop resistance around l.95Q.
As a
result
of the above designing, the resultant
12.7uS according to Fig. 2.10(a). The
maximum commutation
maximum peak and RMS
duration
is
currents of the auxiliary
switch are 89.5A and 21.5A respectively according to Fig. 2.1 1(a) and Fig. 2.12(a). Thus the
auxiliary switch gating signal width is set at 14.4uS and the
Widths are set
the
at
minimum/maximum
l6.8uS and 136.8uS respectively. Dead time of 2.4uS
two main switches.
is
PWM
inserted interlocking
'
Two SEMIKRON IGBT modules (SKM50GBl23D, 1200V/SOA) are employed as the
main and auxiliary switches, four ultra-fast HFA30TA60C (600V/30A) work as the auxiliary
diodes. Two storage capacitors C, and C2 each rated at 350V/3300uF form the DC center tap.
A low-pass filter (L¡=1.45mH,
Besides, four
C,~=l2uF)
SEMIKRON SKH10
and auxiliary IGBTS. Each driver
is
is installed at
the output.
intelligent driver are
interfaced
by an
used for driving of the main
external zero voltage detecting circuit to
38
the gate terminal of the
The
voltage becomes zero.
Fig. 2.15
2.16 shows the
IGBT
module, which releases the gating signal when the detected
of which are described in Chapter
details
shows the output load side voltage and
ZVS
5.
waveforms. Fig.
filter inductor current
comrnutation process of the main switch S, during switching cycle.
Further in Fig. 2.17, the details of tum-on at i,oad=56A are shown. For a predicted dv/dt of
111V/uS (averaged over tg-t3) and
And in Fig. 2.18, the details of tum-off at i¡,m,=56A are shown. For a
and l8A/uS respectively.
predicted dv/dt of
The
of 20A/uS, the experimental values are about 114V/uS
di/dt
307V/uS (averaged over
first voltage spike of about
the experimental value
tz,-ts),
120V appears due
about 277V/uS.
is
to the stray inductance in the turn-off
snubbing path (prolonged loop for measurement objective). Fig. 2.19 shows the main switch
turn-on at zero load
cLu°rent.
'I'
io
"
1
_
E
_i
L
V
'
,¿
_
«i-.z
_
.Ç
1
_
'_
rf
I
,
¬¬-~
M":
'hi
'x
`
5*
Á.-ff*
I
u
›
,
=~
1..
|.
.
'_
....\
1
_
_
_
\‹.
_
e
E
,_
rff
.
íioov/D¡v;2oA/Div;5ms/Div.
Fig. 2.15. Experimental output voltage
t
and
filter
inductor current.
o
~
-o-¢-1-1--o-|-o-|--o-1-s-1--+-+»+-‹›--¬-o-+-|-
ÊIOOV/Div; IOÀ/Div;
Fig. 2.16. Experimental
¢i1uS/Div
commutation process of the main switch
`
(S,)
~_
Vsl
É
Í
.
lsl
É
~1-+-+-1-`-o-1-o-›--o-›-+-+--f-‹-o-+-
'_fl
l
:
¬-1-o-é--o-o-o-v--9-:-o-f-_
E
_
l
100V/Div; l0A/Div; 2uS/Div
Fig. 2.17. Experimental zero voltage switching process of the
VSI
Ísl
-o-o-o-o--+¬-+-+--o-¢-o-e--o¬-‹-o-
2
1
main switch (S,).
-¬-‹-›-f--›-à-o-‹--+-o-+-‹--o-o-+-+-
--
n_r
_
ii
roov/Div; 1oA/Div; ms/Div
Fig. 2.18. Experimental capacitive
tum-off of the main switch
(S1).
Vsl
-o-o-1-e--o-r-é-f--o-à-o-o-
-o-o-o-o--v-e-f-+--o-1-‹-o--1-o-o-‹~
lDl
IOOV/Div; 20A/Div; 5uS/Div
Fig. 2.19. Experimental
commutation process of the main switch
I
(S,) at zero load current
40
.
Fig. 2.20
shows the commutation process of the auxiliary switch
(Saz) at i,°ad=20A.
For
the predicated commutation duration of 7.2uS according to Fig. 2.l0(a), and the predicted
peak current of 47.8A according to
respectively.
is
Fig. l.l l(a), the experimental values are
6.7uS and 40.5A
The tum-on is inductive and no reverse recovery current from the opposite diode
seen. In the meanwhile,
no tum-off voltage spike
generated.
lis
The voltage protrusion
afterwards occurs due to the dynamic charging/discharging of the floating middle potential of
the auxiliary leg.
Fig. 2.21
primary
side.
shows the commutation process of the auxiliary diode
The
at the
transformer
turn-off spike suggests the introduction of simple snubbing to the diodes in
l
practice.
_
.
i
i
¡sa2
í
_
_
uuumunniííímfi
Í
'
___.L.
ya
Fig. 2.20. Experimental inductive
ioov/Div; 1oA/Div; sus/Div
í
tum-on and zero current tum-off of the auxiliary switch
vDa2
-
1Da2
_
|~
1
.
:
vsä
Ê
I
load
ill'
i
›
<]-Ã
..._.._...__..__.
_
Ê
Fig. 2.21. Experimental
.
_
_
..
.
_..
`
l00V/Div; l(lA/Div;` 5uS/Div
commutation process of the auxiliary diode (Dá).
(Saz).
41
Fig. 2.22
shows the resonant inductor current in relation to the load current and the main
.device voltage. Fig. 2.23
shows the
details for switch to
diode commutation at i,0ad=26A. For
the predicted commutation duration of 2.25uS and the predicted peak current of 14.2A, the
experimental values are about 2uS and
l0A
respectively. In the meantime, Fig. 2.24
the details for diode to switch commutation at i,0ad=l8A.
shows
The experimental commutation
duration and peak current are about 6.2uS and 46A, which are in accordance with the
predicted values of 7.3uS and 50.8A according to Fig. 10(a) and Fig. 11(a) respectively.
VS2
í
i
1
Íload
-¢-›-o-f--1-o-o-o-
i
ÍLr
íxoov/Div; 1oA/Div; lous/Div
_
Fig. 2.22. Experimental relationship
¿
among the resonant inductor current, load current
and main device voltage
(S2).
Vs2
z
1
~o-o-¢-‹-¬¬-‹-+-+-o-‹-+--o-›-‹-o-
1Lr
¡
r
-‹-+-‹-‹-
1-u_u
í
Fig. 2.23.
Resonant inductor current
100V/Div; IOVA/Div;'2uS/Div
in relation to the load current
and the main device voltage
during switch to diode commutation (S,to D2).
(S2)
42
-
--
›-
-
------¬--.-¬-.¬-____.¡..¡-¡--¡¡¡¡-¡-zw- --------
í
Fig. 2.24.
Resonant inductor current
--
‹
~
¬_
-
100V/Div; l0A/Div; 2uS/Div
and the main device voltage
in relation to the load current
during diode to switch commutation (D2 to
2.6.
-
(S2)
S,).
True-PWM-Pole Inverter Variations
The fundamental idea of the True-PWM-Pole
inverter is to introduce a bi-directional
DC link voltage to establish the auxili a1'Y
voltage source in the resonance path which joins the
voltage supply for the resonance. Besides transformer, this bi-directional voltage source can
also
be formed by auto-transformer, or by capacitor as discussed below.
2.6.1.
Normal Auto-Transformer Connections
Two auto-transformer connections
I.
í
1
.I
S
E
“
TW*
Í
z'0
LI
.
U~
3'
ca E»
Â
°4K}
Sal
Dsal
O-i
'
(21)
:
«
_
:
L
QiD
ÇÍ,
2.25.
I-
C fi
-
5
Z
1
'*'
ÍN2
9
Vdc
D
|
shown in Fig.
l
Á
DM
4%
Fig. 2.25.
[130] [133] [134] are
DM
J
S2
D2
-__
C¡|
Vm
.
. N;
L¡
N.
I
-9 .z
«Qi
SM Ds”
D¡
*l
+
V
Si
Daz
ZS
O-i
--_
C [2
(b)
Two variations of the True-PWM-Pole inverter with auto-transformer connection.
43
At the first glance, the auto-transformer connection
offers attractive properties over
transformer connection counterpart. The current flowing through the auxiliary switch
(1-k) times of that with the transformer connection,
which allows
is
its
now
for further reduction of the
In the case of Fig. 2.25(b), the auto-transformer primary voltage
auxiliary switch rating.
rating as well as the secondary current rating are further nearly halved.
flow
Nevertheless, auto-transformer connection causes freewheeling current
during
steady state in the auxiliary circuitry, which results in considerable steady state loss in the
auxiliary circuitry. Moreover, the auxiliary switches will operate with hard switching.
Fig. 2.26
S2
shows the relevant experimental wavefonns based on
commutation happens. Due
prior to the
commutation
commutation
(tl).
Fig. 2.25(a)
flowing through
to the freewheeling current
L,,
when D,
N2 and
to
Dm
the resonant inductor current does not return to zero after the
(tl),
flows through
Instead, this residual current
switching of the auxiliary switch
N2 and
L,,
Saul,
causing hard
Sa, (t3).
Upon tum-off of S,,1,the opposite freewheeling diode Dm, starts conduction, which forces
~r~
›‹
thecurrent decreasing in the resonant inductor. In the meanwhile, a voltage
is
reflected on the
auto-transfonner primary side due to the current decreasing in the secondary side, which
forces Daz into conduction carrying a increasing current.
and;the resulted net
currents add to each other
flux changes at a rate which maintains the voltages on the both sides.
The secondary
Dm declines to zero
until the
The two
current reverse direction at
t4.
Afterwards,
both currents get equal and
(ts),
when the summing
current in
flow steadily through D,,2, N,, N2
and L,
next switching action. The auto-transfonner flux can not be reset to zero.
ÍN2
freewheeling
7'
<}-
_
current
¡DSa2
z
\
r
_
“L~.\»-,
|Nl
idual curr
t
f¡eew|,Le|¡¡¡g
current
4
.,
1
.
I
m__
Q-
:_
'is
IOA/Div; 2uS/Div
Fig. 2.26. Experimental
diode
waveforms of the currents
(Dm) when auto-transformer
is
used
in the
in the
two windings and the auxiliary freewheeling
True-PWM-Pole
inverter (Refer to Fig. 2.25(a)).
44
The
current spike at
Similar
2.6.2.
indicates the reverse recovery
phenomena have
auto-transformer
are taken
tl
may be used
of the freewheeling diode
also been observed for the circuit of Fig. 2.25(b).
in the
True-PWM-Pole
which prevent the flowing of the freewheeling
Dm.
As a result,
measures
inverter only after adequate
current.
Modified Auto-Transformer Connections
From
the above analysis, the freewheeling current
and each one becomes aggravated by the
to eliminate the freewheeling current
By
The
resulted
from the residual current
residual current is primitively the auto-
Such being the case, the following measures can be taken
transformer magnetizing current.
l.
other.
is
and the residual current flowing.
M
breaking up the freewheeling current path, which leads to the transformer
u
connection True-PWM-Pole.
2.
current,
By
de-coupling the interaction between the freewheeling current and the residual
which can be realized by making the auxiliary switch a unidirectional one.
Based on the second measure, the four schemes shown
The
in Fig. 2.27 are obtained.
resonant inductor current rating in the two schemes of Fig. 2.27(a)(b)
is
further halved.
However, the equivalent resonant inductor and resonant capacitor are reduced. For the case of
Fig. 2.27(a), the reduction coefficient is 1/(l+k),
coefficient
is
k/(l+k),
which means
capacitance are increased.
and for the case of Fig. 2.27(b),
this
that for a given dv/dt or di/dt, the required inductance
and
Moreover, the auto-transformer primary in Fig. 2.27(a) and the
auto-transformer secondary in Fig. 2.27(b)
now
block the
full
DC
voltage.
The
state
equations for the commutation resonances of the two schemes are given in Appcndix 2.2.
The idea of unidirectional
auxiliary switch has
been verified in a
shown
inverter prototype.
The topology
diodes used are
APTl5D60K(600Vl5A). Other components
transformer connection
for experimentation is
True-PWM-Pole prototype (L,=l5uH,
5kW half bridge IGBT
in Fig. 2.27(c),
are
the
two
series
same with the
rather than 12uH). Fig. 2.28
and Fig. 2.29 show the relevant waveforms when S2 carries current and
is
turned on and off.
zzz
Q
F
I:
Dsl
IS
Dsâz
*P
.N¡
ipki.,
°-I
Vcr2
Da2
Dsal
Da
¬*
¡|‹
ku I. kvea
1.,
S81
:
‹›-|
" :1
Vdc
D1
S1
Da'
°-l
S az
J.
Ds!
D2
Saz
~
1/k
ZS
S¿|
Daz
Dsal
‹v.ú.z-v..1›1f×
0-ll
I:
Dz
C¡›z
Ds!
(b)
1
Q
Ds2
S
Dal
S81
OZ
Vdc
_
--V
iloza
Ô
is:
Daz
E
›|
Dz
5a2
Dsal
VN:
+
_
Q N2
Lr
NÍ
1
Sz
ÃDa2
D2
Cr!
°-I
S81
4
Dsl
Dsa
I
Ds]
i
I
(¢)
Fig. 2.27.
Dal
ZS
Cfz
04
Dsgl
H
Vdc
I
¡s2
l
Ds:
I
..z.
Ji
l
Dsaz
5'
Sa
D
l
“N15
°-l
z
°.|
-_.
Sz
C
I
*F
ll'
í.
(21)
z.:.
_›
.
tâl.
°-I
C
t
i.,
kN|
Cfz
*I
_
_,°4
Dm
Vdc'Ven
Dsl
¿
5|D|
I
Vd
*L
S2
L~
°l
W
‹d›
Topology variations of the modified auto-transformar connection True-PWM-Pole.
“À
'Lr
f
ñ_vs2
*_
Á
;+¬-›-›-¬¬-‹-›-
a_,Ê*
_
_
1/
É
\â \
>
\
/
\ \.V_/\`-f____..
\¡\,\,\,_J..¬_.-.__
Í
í
Fig. 2.28. Relevant experimental
100V/Div; l0A/Div; 2uS/Div
waveforms when S, is tumed on carrying the load current.
46
“
2
_/X/\\\/ÊV/\z¬\/___ /'\. A'
F
É
sI
I
I
l
/
_%%Pfi_fi%_%%~
_|_O_f_|__1_O_|_9_'-O_O-1'-1-*-T-0-9-4"*
Ê*°:_
í
_
,
f"
'Lf_
1
_
.
.
ÍIOOV/Div; l0A/Div; 2uS/Div
Fig. 2.29. Relevant experimental
The
waveforms when S2
is
turned off from carrying the load current.
waveforms are shown
relevant auxiliary switch commutation
in Fig.
2.30.
Obviously, the auxiliary switch turns on and off at zero current. However, a reverse voltage
spike appears across the series diode right after the resonant current
reverse voltage spike
is
resulted
voltage which does not reset instantly.
The
ILI/
ÍV2§'^l
VEL
/
;a¬_¬¬¬+
s
,-\
zz-›._
E
The
by the auto-transformer secondary
of the reverse voltage spike
›
+H+
is
shown
RCD snubber across the series diode.
2
Á
/
\\
5
details
be suppressed by a simple
_
zero.
from the interaction among the stray capacitances of the
auxiliary devices and the resonant inductance, forced
Fig. 2.31. This spike. can
is reset to
/
lezw
5.
aaa;
/1"/"“_T*”"¬`1"""'¬
5
100V/Div; l0A/Div; 2uS/Div
Fig. 2.320. Relevant experimental auxiliary switch Sa,
when S, is tumed on carrying the
wavefonns
load current.
in
47
zfi¬\V~z
L....J“...V.f_¿...,.__..._,__...r.,_
,
.
.
.
...Q-
.
'
&
É za:
.
,
\
VM
.
.
\\
5
V
\
Í
_
.
Dsl
1
i..
í
í
¡
Fig. 2.31. Experimental details
100V/Div; SA/Div; luS/Div
-
of the reverse voltage spike resulted from
the auxiliary switch Sa, tum-off during D, to S2 commutation.
When
modified auto-transformer connection
the
circuits are
transformer connection circuit, the auxiliary switch current stress
“__
z»
PF*
extra simple
RCD
snubber
is
needed for the
series diode.
is
compared with the
nearly halved while an
Other benefits including the auto-
transfonner voltage/current stress reduction or the resonant inductor current stress reduction
are possible with
its
variations,
which are also tested in the
laboratory.
‹.._.~
‹‹
2.6.39.
Capacitor Connection
Capacitor can be used in the place of the transformer or auto-transformer to attain a
True-PWM-Pole
inverter, as
shown
in Fig. 2.32. This circuit resembles the traditional series
current commutation circuit [108], which has recently been considered for use in the boost
converter with turn-off device [135].
Da:
Si
í
°-I
o-l
sal
Dsa2
Vdc
.F
+
ã
H
Di
I
DSM
:
.
_-P
Ú
'load
¬
¬
Sz
°-{
S31
Csi
D2
CS2
:
Dal
t
Fig. 2.32.
New True-PWM-Pole inverter with capacitor replacing the
transfonner or auto-transfonner.
48
new
Control and operation sequence of this
pole inverter are
transformer cormection True-PWM-Pole. Fig. 2.33 (a)(b)
tum-off processes of S2 when the load current
is
show
carried .by S2
all
the
same with the
the experimental tum*-on and
and D2 respectively.
Similar to the transformer or auto-transformer connections where the secondary voltage
altemates direction naturally after each commutation, the capacitor voltage in this case
changes
direction after each
its
commutation as a
result
of the charging/discharging by the
DC
link voltage forcing
the resonance, rather than subtracts from, like the transformer connection,
which leads to more
resonant current. However, the capacitor voltage always adds to the
than sufficient resonant current. In Fig. 2.34, the experimental capacitor
is to
find
the capacitance for C,
which
is
resonant current, capacitor (C,) voltage and commutation duration.
assumed
a compromise
among
Certain loss must be
inverter [l07].
When
compared with the transformer connection True-PWM-Pole
this circuit is
inverter, the troubles associated
expense of the
in the
issue in
in the resonant loop to avoid iterative capacitor voltage increment, as is the
McMurray
at the
voltage in
The key
relation to the load current under the given circuit parameters is illustrated.
designing of this inverter
(vc, )
main
circuit
fairly
with magnetics (manufacturing labor, loss
pronounced resonant
current.
and zero current switching
etc.) are
Both ensure zero voltage switching
in the auxiliary circuit without
any extra
measuring or controlling.
Mathematical analysisof the commutation resonance
is
given in Appendix 2.3.
“Q”
i
..z.a.m-e~1¬l
"¬"
4 ->
^
~v--,-.».z-Í” ~›zzz¬'v-.
âõ
tz
-4'-i~+-O--i'-1-i-Ó-*Í-O-l-l-'
4l-^f“'i_l-'-i'-l'-1-i-
1.>.~ ,_ ~'\w-‹\-›.-ø.=\'~.~zf-zm.--_-.^~.-:. 41
2-oi
_..-»¬,-.¬~‹iw-“N---.,-âi.
y
-_
^ ~
~ _-¡
¡LI`
^~×-^~.~=-›~‹›--1.-.^~:^-.1..‹‹›-«¿.^-.--'\-z»
\\
-----~‹¬-f-v-¬-w--/›-
100V/Div; IOA/Div; 10uS/Div
(a)
commutation processes when S,
avoided,
carries current
g
3-V:
'
_
I
1
4_>._..._.. .....-._..~._..
z
-
.-
z-...__-«._.
J.
1s2
~-._
__-_.__._‹
.¬._¿
É
V
~»ú-mx
-+-+-r-e--‹-o-H--›-1-ø-‹--+-‹-f-o--›
1 _»
~*W“MMrmwMwn
_
2-‹›
_
-o-v-›-f--o-o-1-H
-+-o-o-ê-
iL¡~~*^^.~v
_.
.~.»~^t
X
-.~.
.zz~
.
--.~.~~.~.-.~‹-«Í
_
/_,./=¬‹/-~¬-^~^~\\^-'-~/M/\
/
1
100V/Div; 10A/Div; 10uS/Div
(b)
commutation processes when D,
carries current
Fig. 2.33. Experimental S2 commutation- processes
when S2 or D2 carries current
(Cs,=Cs2=0. luF, L,=7.5uH, C,=2uF)
vzf
~
w»'^`
'~vv
›--›`
`
í.,__-*_
-1-_.
í.
1-í-.
---_
í_-
__,
,ii
-zí
Q-‹›
í
llllp
zpíí
-_:-_
11
-í
z-í
ni-~
¡í-ç
.-ti
.í
,
__;_
›
za:
_
wwwr
I
í
50V/Div; l0A/Div; 2mS/Di\'f
Fig. 2.34. Experimental capacitor (Cs) voltage related to the load current.
(Cs¡=C,¡=0. luF, L,=7.5uH, C,=2uF)
2
7.
Conclusions
Resonant pole inverter solves the problems of the conventional snubber associated with
snubber interaction, series inductor and snubbing diode
with simultaneous zero current switching, which
regenerative snubber.
etc.
The
auxiliary circuitry
works
a significant advantage over the
is
-
Transformer connection True-PWM-Pole inverter avoids the control complexities of the
ARCPI, while
zero voltage switching for the main switch and zero current switching for
the auxiliary switch are always guaranteed.
comparable to the
The
ARCPI .circuit while its voltage
auxiliary switch current stress is
stress is
clamped
to the
DC rail voltage.
Experimental results from a 5kW half bridge prototype agrees well with the analysis.
The normal True-PWM-Pole
and residual current
from such problems as freewheeling current
in the auxiliary circuit, primitively
the auto-transformer,
results
inverter suffers
which renders
showing the problems of this
this
scheme not
due to the magnetizing current of
practically applicable.
structure are explained.
The modified auto-transformer connection True-PWM-Pole
problems by introducing a diode in
current stress
circuits.
is
series
.
Experimental
'
inverter solves the
above
with each auxiliary switch. The auxiliary switch
halved in the modified auto-transformer connection True-PWM-Pole
Further reduction of the auto-transforrner voltage/current rating or the resonant
inductor current rating are possible with
5kW prototype verifies these solutions.
its
variations.
Also, experimental results from a
51
Appendix
2.1.
Mathematical analysis of the ARCPI
Refer to Fig. 2.3, Fig. 2.4 and Fig. 2.5, the commutation duration, peak current
and quasi-rms current
stress (over switching cycle)
Í: iZ0 / Vdc,
values used are: unit current
stress
can be mathematically analyzed. The base
unit voltage;
= v/ Vdc
,
unit time
Í
= two
Throughout the analyses, the unit value of IMS, current is assumed to be 20%.
l.
Total commutation duration
For diode to switch commutation, the total commutation duration is given by (2.lA):
_'
Í¿¿¡¬
1
tl
.¿.
.
Z
+ iboost
(2.lA)
+4[l10ad +lb00s¡]
2
2
For switch to diode cormnutation, the total commutation duration is given by (2.2A):
- = 2a
tsd
T'_ .í"
iboost
- 2 GCOS
__
-í
cos~
-í
+í
Í
tl
+ llboost
'l'
-
lload 1
2
+ 4i¡,00s,
(2.2A)
(2.lA) and (2.2A) are represented in Fig. 2.lA.
g
15.179
l2.834
10.489
tds
8.144
5.799
3.454
tsd
“O9
Fig. 2. lA. Total
o
0.5
1
_
1.5
QE
2
2.5
3
commutation durations versus load current for diode to
switch commutation and switch to diode commutation.
.
52
2.
Auxiliary device peak current stress
V
For diode to switch commutation, the auxiliary switch peak current
:_~
lsapl
=
f- +
lload
is
given by (2.3A)
t--2
fl
(2-3A)
Z+lb00st
For switch to diode commutation, the auxiliary switch peak current is given by (2.4A):
_ _ __
isap2
=
_iload
+
[1
Z
+ (íboost + iload)2
(2-4A)
(2.3A) and (2.4A) are represented in Fig. 2.2A.
3.538
2.983
_
_
lsapl
2.438
1.888
_
1.338
of/ss
1sap2.
0.239
o
0.5
1.5
1
2
3
2.5
iload
peak currents versus load current for
diode to switch commutation and switch to diode commutation.
Fig. 2.2A. Auxiliary switch
3.
Auxiliary switch
RMS current stress
É
For diode to switch commutation, the auxiliary switch
Í
2a coS__Ê?2~SÍ__
F
›
z~saP,ms
z
RMS current is given by (2.5A)
2
V?
2(íload +iboost)
Ã
--2
_-Hboost
1 _
_
\'_¡
Zfzâz +-É
ó[
1
_
_'
__
(zm, + šsinz +z'¿,,,0s, zømâf
(2.5A)
53
For switch to diode commutation, the auxiliary switch RMS current is given by (2.6A):
.í'“
lsanrms
'
=
í
i__+z'__
_+ (boost +1Ioad)2
1
2b00s'1“2'1
f
2¡
É
load
boost
2a cos
I It dt + LTÍ
4
.
I
0
Tífí
.
I
.*"_1.°
_
'"
šsmt "' (lload +lboost)c05Í)dÍ
(lload
O
(2.6A)
(2.5A) (2.6A) are represented in Fig. 2.3A.
l.26l
I
.054
T=45
\
0.846
0.639
\
is prrns
0.432
/
0.224
1
0.017
0
0.5
san
i
Fig. 2.3A. Auxiliary switch
s
1.5
1
T-90
2
2.5
3
load
RMS currents versus load current for
diode to switch commutation and switch to diode commutation.
Resonant inductor average current during one switching cycle can be similarly obtained.
case,
By comparison
the ARCPI is
with Fig. 2.10, Fig.
2.11'
and
2.12 regarding the
True-PWM-Pole
almost equal to the True-PWM-Pole in terms of the commutation
durations and the auxiliary switch current stresses.
54
r
Appendix
1.
C,2 are
2.2. State equations for the
modified True-PWM-Pole schemes
For the case of Fig. 2.27(a), the
state equations for the
resonance between
L,, C,,
and
given by (2.7A):
Lr
diLr
1+1‹ dz
=
Vdc
1+k
_vC”
(2.7A)
2Cr2 dvCr2 =
T«Ê7z`_z1T`
2.
.
'L'
_ IL
1+_k
For the case of Fig. 2.27(b), the
state equations for the
resonance between
L,, C,,
and
H
Cú are given by (2.8A):
Ê_d'l__K¢1¿_vC2
_
1+k
1+k
dt
21‹C,z dvcrz
1+k
From
dz
"W
_.
I'
ku
(2.sA)
1+k
the above equations, the phase plane for each commutation resonance can be
obtained which facilitates the mathematical analysis as well as further physical understanding.
55
Appendix
2.3.
Analysis of the commutation resonance in the capacitor comection inverter
(diode to switch commutation)
I.
z'L,
S2 turned ofland Sa2 turned on, D2 current decreasíng until blocking
V
V
*
= °?-s1n(w,r)
_
(2.9A)
I'
vc,
where
co,
2.
_
z
L,
vcs
É
= V* ‹z‹›s(w,z)
=
(2.1oA)
1
,
Z,
É
= [L
Commutation resonance,
and V
the initial voltage of C,.
.
.
.
C
C
V _V**
= IL á¿‹z‹›s(w,'z) +-°Ísm(w'z) +1L
_
(2.11A)
É:
z
(V0 -V
,,,,
C
c +c
C2
)F”c‹›s(zz›,'f)-1LZ%-z,'sin(w,'f)-1L%f+V**
Í'
S
CC
C
(2.12A)
s
C
= (V0-V**)É‹z0s(zz›, z‹)-1,¿%3-sz, sm(w, :)+1Lä¿”:sz+V**+(I/O
where Cs = Cs¡ //CS2,
V
3.
=I
Ê,
CC
Cp =
V" is the initial voltage of C,.
iL,
is
CS2 charged and CS 1 discharged
sv
vc,
..
'
_
'
-V
,,
C
HF:
(2.13A)
a›,'=
Tí,
l
Z,'=
L
lá
,
and
.
IL is
the load current,
Lrƒully demagnetized, Cr charged
=o=**
V***
cos(a›,t) - Ts1n(co,t)
_
(2.l4A)
Í'
i
vc,
=V
*=|‹=|=
cos(a›,t)
where V***
is
+I
*=|==o‹
Z, sin(a),t)
the initial voltage of C, and I***
Commutation from
(2.l5A)
is
the initial current of L,.
switch.to diode can be analogously analyzed.
'
só
Chapter 3. Operation of the Three Level Capacitor
Clamping Inverter
Abstract: This chapter deals with the major operation problems of the three level
capacitor clamping inverter, including clamping voltage stability, clamping capacitor stress,
and output spectmm
3.1.
Experimental results from a half bridge inverter verify the analysis.
etc.
Basic Operation Problems
A half bridge three level capacitor clamping inverter, as shown in Fig.
two two-level switching
cells,
namely, C¡, C2,
S1,
3.1, consists
of
S4 (cell 1) and Cm, Sz, S3 (cell 2), which can
be treated separately in the modulation point of view.
When
the two cells share a given
switching frequency, the control signal of one cell can be distinguished from the other by the
duty cycle and the phase
shift relationships,
0
Clamping voltage steady
0
Output voltage spectrum.
0
Clamping capacitor
0
Clamping voltage dynamic
which will decide the next aspects of operation:
state stability.
stress.
stability.
n
D1
51
_*
C.
°_i
Í.~m=(d|-d2)i|.›zà
o
c,
l
°_i
cm
_
O-i
v.../2
¿d|×ih“
D,
sz
`
Ã
¿
à í._.›
sz
Ílflfld
D.
V-4 =SW
0-'
S4
Fig. 3.1.
3.2.
A
ZSlv,¿.=sw,×v,,J2
_.__i
Í
ú,ס.,,,,,
|
×V.¡,/2
D;
Configuration of a half bridge three level capacitor clamping
Clamping Voltage Steady State
inverter.
Stability
Referring to Fig. 3.1, steady state stability of the clamping voltage
cturent
flowing through
the clamping capacitor. Stability will
is
decided by the
be guaranteed as far as this
current can be averaged to zero during each switching cycle.
When
the load current
is
'
57
supposed to be constant during a switching cycle, the average current flowing through the
clamping capacitor during that switching cycle will be given by
:
ícm
_ d2)
(dl
where
d¡
.
(3.1):
ilnad
and dz are the instantaneous duty cycle of cell
1
and
cell
2 respectively. Obviously,
i¢m=0 or d,=d,=d will ensure the steady state stability during the local switching cycle.
3.3.
Output Voltage Spectrum
It
has been concluded that a set of control signals phase shifted by 21t/ p (p
number of cells)
is
the
an output voltage where the harmonics up to p times of the
will produce
switching frequency are zero [74]. In a two cell°s case,
when vem
is
supposed to be equal
to
:›i
VdÍÍ/2,
VAO
the output voltage
_
-VS3 +Vs4
given by
(3.2):
Vdc
Vdc
_
u-T--SW2'T+SW1'T-*Ê
where SW; and
the
is
Vdc
SW2
Vdc
(3' 2 )
are the switching functions of cell
down switch (S4 or S3) is
l
and
cell 2.
When SW;
or
SW2=l,
in blocking state.
wrrier
I
came' 2
m0d(t)
=
M sin(comt + 0)
11
É
l
d
I
*
l
OA
||«z.|
im
Í
Vw
0V
......... ..
Vó./2
i
sw,
1
sw,¬
‹
Fig. 3.2. Sub-harmonic
J
(mlgr
|‹
g›£^¿^.S"
PWM
g
First
Sampling Cycle
‹
i
“_“TT-'
>
Second Sampling Cycle
modulation pattem of the main
circuit
and the associated waveforms.
58
Control signals fulfilling the conditions of equal duty cycle and
generated by intersecting a sinusoidal modulating reference with two
triangle caniers, as
shown in Fig.
3.2.
Assmning
coordinate zero, the two natural sampling
that the
1:
'rt
phase
and
SW;
can be
phase shifted bipolar
modulating reference
PWM series SW¡
shift
starts
from the
can be expressed in
Fourier form as given by (3.3) and (3.4) respectively [l36][l37]:
sw
+
+
1
2
w :uz
S =:2,:4,..
m=
sw 2
=
:À '=
2
02-sin(mú› t-Í)
_
"W
C
2
M
-í--sin(;)cos[(ma› C t+na› m I)-mn]
”'”
2
(33)
~
mM7r
2
,M
“--ícos(-.-)sín[(ma›
t+nm '" t~)-mfr]
C
2Jn
10°
M
NP/18
m=135...
mM7r
2
(-1)
Nnz
[Vl
J-*M8
2
2
,N
mz
m+l2J
-"-'
00
=l+£sin(ú› '” t)+
mM/r
mf”
¢1,¬:3,..
lM'‹
=-+-nm
2
2
sl
2
mM/r
"""'
+1
'"
1)
Ê
-
m=1,3,5...
‹1›m22J°2
°‹
-í--smma)
mff
°
f
--"›
2
mM7z'
-
2J
¬:‹×>
5=
M
«zjms
2
T
-"-_sin(flí-€)cos[(ma›ct+na›mt)-mrr]
Ê» .n=¬¿2,¢4,..
"W
2
( 3.4 )
mM7r
+
Í°°
š=
M
+1 Í3 ,..
n=._
.NM8
,
V-À
where
M
is
2-Í"
2
y
mn'
'
cos(T)sin[(mwct + nwmt) - mør]
the modulation index, (om is the sinusoidal modulating reference frequency, co C is
Mn
(L)
2
the triangle carrier frequency, and J n
of argument
LI*/Íl'_.
2
'
is
M
n order
Substitution from (3.4) and (3.3) in (3.2), the output voltage of the half
bridge three level capacitor clamping inverter
“
the Bessel function of the first kind and
given by
is
(3.5):
mMn'
VAO = Vdc -í sm(a›mt) + Vdç
.
w
iw
m=š4,"
nzišâw
2_1
n
2
----mn
W,
cos(T)s1n[(ma›ct + nwmt) - mn] (35)
_
59
From
(3.5), the
following conclusions are obtained regarding the output spectrum under
phase shifting condition:
'rc
The tríangle carrier fiequency components 'together with
0
its
cross modulation harmonics
are canceled.
Among the cross modulation harmonícsfamílíes, m=I, 3, 5..families are canceled.
No even harmonics exist in the spectrum.
0
0
3.4.
Clamping Capacitor Stress
When control signals for the two cells are with equal duty cycle and are 1:
'
the
phase shifted,
RMS current stress through the clamping capacitor will be dependent on the load current
together with the duty cycle of the local switching cycle, which
z¿,,',_,,,,,(f›
z'c,,,_,,,,s‹z›
=
=
z',,,,,d‹z›\/2p‹1-‹f‹z››
›',,,¿,,,,‹f›«/2‹1‹z›;
;
is
given by (3.6) and
(3.7):
when â>o.5
(3.ó)
when â<o.s
(3.7)
where icm_¡.mS(t) is the quasi-instantaneous
which is solved over switching
cycle,
RMS current stress through the clamping capacitor
and d(t) is the duty cycle of the two
cells.
Moreover:
dm = lif%W
(3.s)
So that substitution
for (3.6)
and
(3.7) yields (3.9):
_
icmƒmsm = iload(t)V 1 'mod (UI
Eq. (3.9)
is
represented in Fig. 3.3.
regards the clamping capacitor stress:
0
0
(3 9)
From which,
the following conclusions are
»
RMS current equals the peak load current.
Maximum RMS current occurs when pure reactive power is transferred.
The maximum
_
Similarly, the voltage ripple across the clamping capacitor is obtained in (3.l0):
drawn
as
60
Avcm
(t)
= Tfzmzd
ff)
Cm
where Avcm(t)
is
(1-Im‹›d
(3-10)
‹f›|›
2
the voltage ripple amplitude.
1
vç
|
0.9
-
,'
cm.rms (t)
_%__._í.
Í
0.7
__
'
s
Í
Í
`~
\~
`\
\
›
\
\
load (Í)
\
06 ._
0.5
O4
\
M=0.6
o
\
3.5.
\\
f
/
~{
I
/
/
I
_.
¡
`~--'
.
_
/
_
I
I
0.004
o.ooõ
o.oos
0,01
t
stress related to load current
and load power
factor.
Stability
of the clamping voltage to retum to
value after a perturbation with no specific control over
Assume
`
/
Í
0.002
stability refers to the ability
3.5.1. Self-Balancing
;`
/
'
=3
= 1,,sin(wmr), mod(t) = Msin(w,,,t + 9) , C0m=2TC×Õ0-
Clamping Voltage Dynamic
Dynamic
`\-f
/'
GD
I
Clamping capacitor current
¡,md(¡)
\
_
-'
\ `
\
I
o
Fig. 3.3.
/
\
\
~
\
\
I
_
`
\
Í
\
'Í
`
"
_/'
\'
I
i
\
`
-
//
`
`\
//'
os
9=1t/2
'
z'
z
|
,/
\
z
////I
|
|
\\
it, i.e.,
its
nominal
the self-balancing ability.
under Ideal Condition
that for
some
reason, expected or unexpected, typically during the start-up
process, the clamping voltage arrives at a value other than Vdc/2, then the output voltage can
be expressed by
VAO
(3.1 1):
V,
4
V,
:sw2vcn1+swi(_š__vcm)_%
which can be rearranged as
(3.l2):
61
VC
= %‹~‹»1
Hwz -1›+‹S»1
VC
-~‹wz›‹%
The second part of (3.12)
variation. Substitution
from
mz)
represents the output voltage response to the clamping voltage
and
(3.3)
(4.4) in (3.12), the output voltage variation is given
(3. 1 3):
-
---v °"' ›{
Av A” = ‹Vd°
2
s=
fims
'M
É
QM
m=1,3,5...
‹
M
2
mff
-W
4.1" 2
n=i2,i4,"
Assume a
mMfr
fi
- 1›74"°
iísm'‹ ma)
WH' 1
:oo
+
m,,
s1n(-2-) cos[(ma›ct +
Vdc
Azload = (-2- v Cm){
_
_
+1
‹×>
É
m=1,3,5...
(-1)
-
5=
ÇM8
'M
E= li;
When
z
--”›
2
(313)
nwmt) -
m1r]}
mfi
__
mM/z'
- -í-sm(ma›ct
É âmwc)
mfi
1
zz
_
zm co
C
(3.14)
~
4-7,,
1‰Ҥ
(3. 14):
¿"~2-410 2
_
-"lg-4-'í
p
C
load impedance of zj¿9j at the harmonic frequency of j, the corresponding
load current variation can be written by
+
1
Z
sm(
_
mwc +nwm
mir
this load current variation is
2
)cos[(maJct
+ nwmt) -
mn - 9mwc_¡_nwm ]}
reflected back to the clamping capacitor, the
resultant charging current variation will be given
by (3.l5):
.
_
_
Aim = Aim, (sw¡ - swz)
(3
Substitution from (3.3) (3.4) and (3.14) in (3.'l5), the result of
substantially complicated expression
when
Aicm
by
and
the clampingvoltage balancing
is
of
interest
and
this fact
is
may
which
.
1 5)
will be a
not allow for any physical insight. However,
particularly
concemed, only the
simplifies the task. The
current variation can finally be written by (3.16):
DC
DC
component
in
component in the charging
62
.
AlClVLdL'
Vdc
=
-vem
(3-
where:
G=5 5 =
+_
2
â=
__”
2
m+l
ÍÇÂM8
{[‹-1)
Y'
2
%12ícos‹0mwc›}
1
C
mM”
4-Ín 2
Í;
¡;Ms
This
mM1r
Y'
n=fl,i4,"{[
'
Sm(
mn,
mfr 2
2 )l
(317)
l
zmwcfluom
°°5( 0ma›c+na›m )}
DC charging current can be related to the clamping voltage variation by (3.18):
(7 ' WG _ °`m 'az'
dvcm
Vdc
(3-18)
The clamping voltage dynamics
is
given in the end by
(3. 19):
_CmG
__1_,
Vc
Vc
um = -5'-+mm‹°›-%1@
where
(119)
vem (0) denotes the initial value
clamping capacitor and Cm/G
The
self-balancing
is
of the clamping voltage,
Cm
is
the capacitance of the
the time constant for the first order dynamics.
mechanism analyzed above
is illustrated in
Fig. 3.4.
perturbation Avcm, the output voltage will vary correspondingly (AvA0)
current variation Aimd.
The
clamping capacitor will give
original perturbation
which
For a given
results in load
resulted charging/discharging current variation Aicm for the
rise to voltage
and the clamping voltage
component AAvcm, which tends
is finally
maintained at
its
to cancel the
nominal value.
The foregoing discussion supports the next conclusions with regard to the self-balancing
ability
under ideal condition:
63
Al/cm
AV0”.
=0
+
sw]
_sw2
âí
Al/ao
Clamping voltage
.I
mem
~
sw! _;sw2
1
1'
Fig. 3.4. Self-balancing
'
minar]
l
mechanism of the three
AAVcm
CL J'Al.cm
M
I
+
l
'
level capacitor
clamping
+
Ma..
AVC!!!
inverter.
components of odd multiples of the triangle carrier
drift leads to
frequency and their cross-modulation harmonics at the output, according
to (3.I3),
which
essentially determines the self-balancíng ability.
Clamping voltage dynamic
0
G
.
will
always be positive if 0
ensure the clamping voltage
with normal inverter load.
0
stability depends'
is
i.e.,
G expressed by (3. I 7).
non-pure-inductive/capacitive load will
regardless of its initial conditions. This
stability,
is satisfied
V
Clamping voltage response
dynamics
¢ in/ 2,
on the sign of constant
exhibits typical one order performance.
The duration of the
dependent onthe time constant -(Cm/G) of this dynamics, which
is
further
decided by: clamping capacitance, modulation index and load properties.
3.5.2. Self-Balancing
under Non-ideal Condition
Practical circuit contains various non-ideal conditions [138]
asymmetrical operation of the two
cells
which
and the clamping voltage
potentially lead to
may
drift as
a
result.
Among them, deviation from ideal trigger timing deserves the most treatment.
In an extreme case, duty cycle of one switching cell
one load current direction, and
is
is
always higher than the other for
always lower for the other direction. Both tend to over-
charge (discharge) the clamping capacitor. However, while the clamping capacitor being
over-charged (discharged), a discharging (charging) current arises simultaneously due to the
self-balancíng
mechanism counteracting
of the asymmetry, there
the net current
cycle.
flow
exists
to the
This conclusion
is
the current of the first case.
a new operation point other than
clamping capacitor
verified by
PSPICE
is
averaged
Dependent on
the
to zero
the extent
nominal value at which
during each switching
simulation, the results of which are
shown
in
Fig. 3.5(a)(b).
For this simulation, the half bridge three level capacitor clamping inverter
by sub-harmonic
Table
3.1.
is
modulated
PWM pattem, as shown in Fig. 3.2. Parameters/specifications are shown in
Duty cycle difference
for the case of Fig. 3.5(a) is 0.01 (-0.01)
and for the case of
64
Fig. 3.5(b) is -0.01 (0.01).
after the first order
Table
The clamping voltage
dynamics.
is
balanced
Vdc=800V
voltage
Clamping
C,,,=680uF
respectively
of self-balancing under non-ideal condition
Output
L¡=0.lmH Modulation
Filter
C,=4uF
index
Operating
fC=l0kI~Iz
Fundamental
M=0.8
R0=1Q
Load
resistance
fm=60I-Iz
Frequency
frequency
capacitance
560V and 240V
PSPICE program for this simulation is listed in Appendix 3.1.
3.1. Circuit parameters/specifications for simulation
Input
at
Initial
clamping Vcm(0)=4()()
V
voltage
Besides the extreme case discussed above, dead time causes no clamping voltage
because
it is
symmetrical for the two
cells.
Dead time
effect for
one
cell is
canceled by the
same effect for the other cell during the switching cycle.
'nnflnnl oonlmlafion
Dlhlfm nm: 021088! 092521
Tompoulurozilfi
600V
SWV
520V
050V
Vem
“OV
400V
380V
(a)
Om:
2
u
V(\1.l D)
Duty cycle
2
SMB
I00r|B
150m!
200!!!
fm
difference 0.01 for the positive current, -0.01 for the negative current
'nnfiiwul oofrtnlhfion
Datnlfm nn: 0M.lM_l.Iâl.'ãJ
WV
;
lmmtnlliilfl
MV
NOV
W
Vem
2BOV
2l0V
200V
(b)
om:
Duty cycle
Fig. 3.5.
100m:
50m:
zz
v(w,|s)
drift
\50ma
200m9
Tm
difference ~0.01 for the positive current, 0.0l_ for the negative current
Clamping voltage self-balancing under non-ideal operation conditions.
65
_
3.5.3. Self-Balancing in
Three Phase System
For a three phase system, as shown in Fig.
3.6, generally the
same procedure
in sub-
section 3.5.1 can be followed. For any initial deviations Avzmz,cm1›,zmz of the three clamping
voltages, the corresponding load current variation in each individual phase
which
is
then refiected back to each clamping capacitor detennining
its
must be solved
charging/discharging
current variation. For this purpose, the corresponding voltage variation between the
neutral points
O and O” is of the principal importance.
When three
sinusoidal modulating
the three phases intersecting the
same
waves with
carrier
two
_
21:/3
mutual phase
shift are
applied for
wave, the resulted switching functions can be
expressed by (3.20):
5-`‹zš`
«Í-`|zš`
Cn
_.__.v.
L
Ãnz
OZ
cm
l
5-`4z:°`
Ãnz
osll
l
Cmh_
u
5%
t
zf
CM
ZÉ
Í-1
ÃÃI”
°”
osii
Íll
‹Í|ÃD`
@@
C
Zgnz
Â
5125
0.
Fig. 3.6.
(sw,-sw,)u_h_L,=
+
i
m
=
where
."l"18
5° P'
Three phase three level capacitor clamping inverter system.
4»
m
=
FMS
oo
S = ÉÉ ,i 4
‹pa,¡,,¢=0, -21:/3,
5” P'
7(-I)
f"
m+1
2
mM1r
JO
2
fr
sm(ma›ct-3)
_
'
¶sín(";l)cos[( mcoct + ncomt) -
(320)
'K
21:/3 for
phase A,
between each phase terminal and the
B
nçou_,,_C]
and C. From (3.20) and
(3.12), voltage variation
DC link neutral potential is given by (3.2l):
s
66
AVAO
BO,CO
_ SW2 )a,b,c Avcmmcmb cmc
=
Afterwards voltage variation between the two neutral points
Av,.,,
is
expressed by (3.22):
= %(Av,0 + Avg, + Avco)
From
(3-22)
(3.2l) and (3.22), load voltage variation of each individual phase can be obtained
and the same procedure
in sub-section 3.5.1
can then be followed for the reflected
charging/discharging current variation of each clamping capacitor. This procedure
detailed here
not
and only the conclusions are given as following:
When clamping
I.
is
voltages in three phases are not equal (say, perturbation of clamping
voltage in one phase during normal operation), the
odd multiples of the
triangular carrier
frequency and their cross modulation harmonics enforce the self-balancing, which
similar to the half bridge case. The three clamping voltages willfirstly get equal
move
2.
to the
nominal value synchronously.
When clamping
is
and then
4
voltages in three phases are equal (say, start up process), the cross
modulation harmonics of the odd multiples of the triangular carrier frequency (odd
multiples of the triangular carrierƒrequency are canceled) enforce the self-balancing. The
three clamping voltages
3.6.
move
to the
nominal value directly and synchronously.
Experimental Verification
Basic experimental verification of the self-balancing ability
scale prototype. Refer to Fig. 3.1, the prototype parameters
Table 3.2, and the results are shown in Fig.
and the clamping voltage
clamping voltage
is
is
3.7.
monitored.
conducted on a small
and specifications are given in
For Fig. 3.7(a)
monitored. For Fig. 3.7(c)
is
(d), the
(b), the
DC
DC supply is opened
supply
is
closed andthe
F
Table 3.2. Prototype parameters/specifications for experimental verification of the self-balancing
Input
_
_
Vdc=200V
Output Filter
voltage
Clamping
capacitance
Cm=l650uF Operating
frequency
L,-=l .45mH
Modulation
C¡= 1 2uF
index
f¢=6.5kHz
Fundamental
frequency
M=0.62
fm=50Hz
67
From
the experimental results
responds to the
overshoot
DC
shown
both cases, the clamping voltage
supply voltage change with first order characteristic and no resonance or
caused. However, longer time
is
in Fig. 3.7, in
taken to reach steady state
is
when
the load
is
step-down or step-up, which means that the time constant of the dynamics
lighter for either
runs inversely proportional to the load resistance. This result
is
in line with (3.19).
1
Vdc
'_"-›¬_T
§Y‹¶=
Í
štbttr
zl*
9/
1
Vc
1
Í
§I§.f$\7""t3|fT9"h
_
(a)
ivete
1
'
š‹)()v"`(ñ?¶›‹)vLM
"f×7l'ãUi›%ris
Ro=3Q
(b)
1.õí›`s
Ro=7.5Q
tttttt
p
,mygznldm
fr'.i._JE.'‹=z_..
e
~
"
i
z
1
sp
;
.é
.;
É
i
i
Ê
~
s
tm.
T'1F\¬I`
So__.U._V..¡.Cñ2..SÍ_.'
(c)
Ro=3Q
(d)
Fig. 3.7. Basic experimental verification
of the half bridge three
3.7.
0
É
fl'í“‹ív"“f'fi`)"§r`1`^l›'\`/"ñF<l'Yn|`~ri<i"`
_
Ro=7.5Q
of the self-balancing
level capacitor
clamping
ability
inverter.
Conclusions
Gating relationship of the two cells
clamping capacitor
stress
is
associated with the clamping voltage stability,
and the output Spectrum
for steady state stability, phase shift implies a
etc.
While equal duty cycle
is
required
compromise between clamping capacitor
stress
and output Spectrum. With
1:
phase
shift,
the output spectrum
is
optimal and
maximum RMS current of the load current value happens when the load is pure reactive.
Clamping voltage
load.
is
self-balancing under the given gating pattern with non-pure reactive
Time constant of the
first order dynamics
is
dependent on clamping capacitance,
modulation index and the load properties.
Dependent on the extent of non-ideals, typically resulted gating or switching mismatches,
clamping voltage
the self-balancing
is
balanced to a new operation point other than the nominal value, due to
mechanism counteracting such non-ideals.
Appendix
3.1.
PSPICE program for simulation under non-ideal situation
*Self-balancing under non-ideal situation
* pulse
pattem generation
v1 10 pulse (-10 10 .lu 50u 50u .lu 100u)
e2 2 0 value {-v(l)}
vmod 5 O sin(0 8 60 0 0 0)
vdri 42 0 pulse (0.2 -0.2 8.34m 0.1u 0.lu 8.34m l6.8m) * duty cycle difference
esul 6 0 table {v(1)-v(5)+v(42)} (-le-2,10)(1ei-2,0)
esdl 10 0 table {v(6,0)} (2,l0) (3,0)
esu2 7 0 table {v(2,5)} (-le-2,10) (le-2,0)
es_d2 ll 0 table {v(7,0)} (2,10)(3,0)
*main
`
circuit
su3 16 24 6 O sswitch
ds3 24 17 dmod
du3 17 16 dmod
su4 17 25 7 0 sswitch
dsu4 25 18 dmod
du4 18 17 dmod
sdl 18 26 11 0 sswitch
dsdl 26 19 dmod
ddl 1918 dmod
sd2 19 27 10 0 sswitch
dsd2 27 20 dmod
dd2 20 19 dmod
*device model
.model sswitch vswitch(ron=0.01 roff=1e6 von=4 voff=2)
.model dmod d(is=2e-15 bv=1500 tt=0 cjo=lp)
.
*DC link supply
vc2 16 40 400
vc22 40 20 400
*flying capacitance
c3 17 19 680u ic=400
*load and filter
lload 18 41 0.lmH
rload 41 40
cload 41 40
1
4uF
l0u 600m 0 l0u uic
.options vntol=l0m abstol=10m reltol=0.1 itl5=0
.probe i(lload) i(c3)'v(17,19)
.end
.tran
1
70
Chapter 4. True-PWM-Pole Three Level Capacitor
Clamping Inverter
Abstract: This chapter proposes a transformer connection
True-PWM-Pole
three level
capacitor clamping inverter. Besides the detailed description of the circuit configuration
and
operation, the specific features of this configuration are highlighted. Several topology
variations for multilevel case are illustrated shortly in the end.
4.1.
Circuit Configuration
The proposed
circuit is
shown
in Fig. 4.1. It consists
capacitor clamping inverter circuit and
SM)
assists the
cell (S2, S3)
two auxiliary branches. The first auxiliary branch (SM,
commutation of the first switching»
whereas the second auxiliary branch
of a main half bridge three level
(S32,
Sá)
and fonns the first pole;
cell (S,, S4)
assists the
commutation of the second switching
and forms the second pole. The two poles can be regarded independent from each
other so far as the clamping capacitor voltage
is
maintained
at Vdc/2.
I
Ê
ir >tP
‹_
C|
nn
S2
ic
_à
D_ 14
»
iuu
N¡ Õ
DID”.
~
Dsal Sal
N2
Í-‹rl4
O
Dal
H
+0
R
C2
í-
DS34
SM
*I
Cm
5:13
s:i3
Daz
Das
.NZ
N|
H
Saz
Dmz
Da2
_
0.!
`
D2 Cn
Ã_
_
A
[423
‹í
.
Da3
.
lload
i¡_¡¶3
,°¬|ÃS]
D3
Cr]
i
°i
S4
Ã:
Dó Cú
Í
Fig. 4.1.
The proposed True-PWM-Pole three
level capacitor
clamping
inverter.
71
4.2.
Circuit Operation
Prior to discussion of the commutation process, the following conditions are assumed:
im is flowing and remains constant during the cornmutation.
0
Positive load current
0
Capacitors C, and C2 are treated as voltage sources during the commutation. Clamping
capacitor voltage
0
is stabilized at Vdc/2.
Transfonner ratios are
rail level in
set to ensure sufficient
energy for the pole voltage to swing to the
the presence of commutation losses, as discussed in Chapter 2.
0
Circuit parasitics, device switching transients and transformer imperfections are neglected.
0
Main switch tum-off and auxiliary switch turn-on happen
the modulation
scheme discussed
at the
in Chapter 3, while the
,mauxiliary
mm
,,¡;.,...
.
_
Q,
.
zz
=雋‹»,,
universally constant covering the
-
-z
.¬
¬.
.-
Conduction intewal of the
maximum commutation
the commutation step diagrams for the first sampling cycle
N«vc
from
duration as
Refer to the theoretical waveforms for the entire switching cycle shown in Fig. 4.2, and
~
\
¬*~
is
instant decided
.gdiscussed in Chapter 2.
.,_,
_
,,..-¬,._
_,,,,,,,...
switch
same
main switch tum-on happens
until the detected voltage across the switch declining to zero.
.
~
commutation of the half bridge
steps:
in Fig. 4.3, the
inverter during the first sampling 'cycle consists of the next
_
Step I
(to-t1): Circuit
steady
state.
clamping capacitor Cm. Output Voltage
Step 2
and Cú,
C,3.
(t 1-tz):
Step 3
N, sees a voltage of
(t2-t3) :
is
Step 4 (t3-t5):
Step 5
kV,,c/2 after
state.
iL,23
may
tum-on of
S,2
and conduction of D,2 and
cause oscillation due to
its
S3
is
tumed on at
forward recovery as well as
of the paths.
falls to
zero at
t,
D4 and D, carry load
S4
D,2°.
_
allowing for tLn'n-off of S,2 at
current.
VA0=-Vdc/2.
(t5-t6):
the
on at tl, which starts a resonance between Lú,
vw rises to Vdc/2 at tz leading to conduction of D3. Then
stray/internal inductances
output voltage
S, carry load current discharging
V A0=0.
discharged.
zero voltage. Snap on of D3
another steady
D4 and
S2 turned off and Sa, tLu°ned
Cú is charged and Cú
`
shown
is
turned off and S,4
is
t4.
Clamping capacitor Cm
tumed on
at
ts,
Circuit reaches
is
floating.
And
leading to conduction of Da,
and DM”. Nz” sees a voltage of kVdc/2 which joins Vdc/2 enforcing current decreasing in D4
.
72
Step 6
(t6-t7):
im,
rises to the load current level at
Resonance among LM, CM and
CM
C,, is initiated.
t6
leading to blocking of D4.
charged while
is
C,,
current of D4 enhances the charging current and therefore facilitates the
Step 7
(t7-tg):
(tg-t9):
commutation process.
vw rises to Vdc/2 at t7 leading to conduction of D1. Then S, is turned on at
zero voltage. Rapid cmrent transfer from Cp, and C,, to D1
Step 8
discharged. Recovery
im,
falls to
load current at
ts.
may cause oscillation.
D1 stops conduction and
S, starts carrying
C
the load current.
Step 9 (t9-t]1): im, extinguishes at
another steady
voltage
state. S,
t.,
allowing for tum-off of SM at tm. Circuit reaches
and D3 carry load current charging the clamping capacitor Cm. Output
V A0=0.
In addition, the remaining two commutations in the second sampling cycle (D3 to S2 and
S, to
D4) can be analogously inferred.
'I_`o
summarize, for the proposed
«
.
circuit, the
main switch work with zero voltage turn-on
and capacitive tum-off, whereas the main freewheeling diode work with zero voltage turn-on
and zero current
the
turn-off. Superior to the conventional snubber, the capacitive
tum-off loss of
main switch can be rninimized by optimizing the resonant capacitor
to this end.
Meanwhile,-depending on its forward recovery property, the snap-on of the main freewheeling
diode does not introduce any considerable
Moreover,
all
the -auxiliary devices
loss.
work with zero
current tum-off.
And
yet voltage
is
only reapplied after tum-on of the opposite auxiliary switch. Besides, despite of the bridge
configuration, the
tum-on of the
auxiliary switch is actually
since the opposite freewheeling diode carries
recovery
is negligible.
Transformer excitation
snubbed by the resonant inductor
no current beforehand and thus
is reset
to zero after each
its
reverse
commutation and no
magnetic accumulation can happen.
In particular, by designing a transformer ratio less than 1/2, an auxiliary voltage of (1k)Vdc/2 higher than Vdc/4
pole to swing to the
is
becomes
rail voltage.
no longer necessary.
available
which
delivers sufficient energy for the resonant
Thus the “boost” stage and the associated control complexity
'
Designing aspects of the two poles have been discussed in Chapter
implementation of a 3kWlprototype .will be presented in Chapter
5.
2.
Detailed
À
4
l
l
ii
55mP¡¡"8 °Y°|@ TÍ2
Flfsl
eo
I
Sa;
_
Sa:
Second sampling cycle T/2
--.my
l
.
”l.
¡
s,_'|
fl
.
,
CID
5.1
ÍÇIIT”
l
/X
Vu:
il/Z]
VSa:
v.,,¢z
A
I
i
I
1
i
5
_`i"`_"'
V¢J2
Rr.
Sa,
¡z;í.í._-..._..._-.ê
1
E
Í
l
"rir-ln'
`
V
¡__
B
TI.
VC..
,~'
-
.
.-6»-11
Ç-le...-1.-___¬_
¢1E"`:^›\-*
.z*2.~r‹=~_-
..z.zr=.
~:
VSa‹
.âfíà
›.
›‹
vw*
TP*
'fi
«.
'
z
10
51°?
12 13
11
lí
14
uu
0
ilm
.
E
vdm
'í
~
›
i
V¿,/2
w
zu
"-1
v.,./2
16
s
19110
11 1a
el
i
7
‹.
w
Cm
‹-
M4
.
É'
1
S
rm
A
q
S15'
cn
D,
-_
ID
sz
°l
A
Cn
.
uu
in
VM
'I'
su
'E'
›
‹.
.
.
~
o
zw
DI
Ill
2: ¡Í'¡1
:
°-I
113
114
11s
111 11s 119120
116
ç
'í'
‹-
sn
1
Slcp
A
1-
›
hm
VM
'_'
'
i
O
uu
*I
4-
W
DI
SI
3: lz-r;
`
V
_...,z
___›
-
ru
I
Gl
:
¡ __
D, cn
.
su
Cm
A
°-I
cu
level capacitor
a entire switching cycle.
4L.
¡ _;
__¡g“Í
su
F
GI
:
in
-x°“"
~
1112
111
commutation wavefonns for the proposed True-PWM-Pole three
DI
SI
“HI
4-
:Vdm
l
5
5
clamping inverter
.
l
z
_
Í
l
Fig. 4.2. Theoretical
D"
Vúz/2
I]
Vw
u_u
.
E
"_"
Íuu
vz:
.
l-
‹Í~Í3À^'
l
i
fíeâ
J._......
Sa.
lload
=
(X
A
:
¡
:
‹
-
sn
':'
su
Cm
'Z'
1-_
¬
--›
I'
'
‹.
.›
.
su
U1
mz
::
cn
sz
I
‹
:
›
ou
74
S.” *u_u
H
+
.xm
D:
sn
A
cn
:
+
›
'>
uu
m
'
;
O‹
É
vdcn
cn
-
D..
'
~l
A,
V
°l
sà
_
‹
04
‹-
›~
um
vaca
í
_
_í
IIII
S tcp
WM D"
.‹,
,y
_
.
Cn
`
:
.
cn
na
.
-
-›A
l
°l
bu
À
_
Vaca
ml
_
tú
4.3.1.
cn
D,
›
.
..
r
i
F
ui
Dn
sn
Sm, 9_l9_l“
~
‹^
‹-
_
of
_
,›
g
‹_
.
CT!
_
-
_
.
ou
Di
1
I
-
eu
A
-›
V.z
Ill
_
VM2`
Išfl
_
:Eu
'
1
Cn
D7
un
O
.
DI'
‹,
,›¡
'
.
_-'
`
Í
.
|›z
,
í'
-›A
cn
|
‹ÀD :LI'z
°i
84
z
Dc
:
(.'fz
diagrams for the first sampling cycle.
Stabilization
.
_
self-balancing ability of the clamping voltage under the given modulation pattem
verified in Chapter 3
variation
A›'
'
Features
Clamping Voltage
The
Dl!
__
Dl
_
I-ë-Í
:
|›‹
is
strongly subjected to load properties. Destructive clamping voltage
may arise due to
such reasons as load change (load open, reactive load for example)
or triggering failure etc. Active control of the clamping voltage necessitates detection of the
clamping voltage as well as the load current direction, which tends to complicate the system.
The proposed True-PWM-Pole
three
level
capacitor
clamping inverter posses
charging/discharging paths for the clamping capacitor whenever perturbation occurs.
the clamping voltage gets
below the nominal value,
it
will be charged
When
by the up-capacitor
Dm, N2” and LM when S, is gated, as shown in Fig. 4.4(a); or by the downthrough S4, Dsaland LM when S4 is gated, as shown in Fig. 4.4(b). In the
(Vdc/2) through S,,
capacitor (Vdc/2)
meantime, when the clamping voltage gets above the nominal value,
the up-capacitor (Vdc/2) through D,,
Lr,,,,
A
'
_
"IU
Fig. 4.3. Operation step
4.3. Specific
‹A
Nf,
_
_
¿
Du
mz
O
cn
z
,
A
Vlkn
_
°-I
nl
Q-
__
Q
um
E
'
Nf,
ln:
cu
›
si
llzlg-(9
_
'Ê'
__
F
cn
_
Dl
'
Dn
g
_
`
Nf,
O __
cn
A
'
'
A
0,2,
34
D:
un
_
i‹.
››
O
um
_
cn
'__
_
H
+
.VM
m
m
S' °° 6:' " 47
'ri
D:
sl
1
m
Nf,
Cu
4
1
S! CP 7 Í7'8
Í
cn
:
Du
'
Lm
O
A
1
É
DJ__cn
!
Jaú/1
A
_
nm
um
H
'
.W
m
s|
smp 5:6."
Nƒand
S34
when
it
Sw, is gated, as
will
be discharged to
shown in Fig.
4.4(a);
75
or to the down-capacitor
(V de/2) through
Sal,
N2”,
LM and D4 when S,,
is
gated, as
shown
in
Fig. 4.4(b).
In other words, the charging paths arealways existing except for the gating space
between
and
S4.
However, the discharging paths become available only when the
auxiliary switches Sa, or
S,,,
are gated.
interval
S,
Taking into account the magnetic losses and the conduction losses in the
damped second
charging/discharging paths, the charging/discharging processes are a
order
resonance involving the clamping capacitance, resonant inductor and the auxiliary
transformer, which guarantees the clamping voltage to be stabilized at Vdc./2.
F
'
o
A *
_
D:
Ífl
rm
ÍII1
15,13%'
JM..
V
›
5%W
.
.
~
-
...,,
^
o
*“
uu
fi
Cn
:
ln
iu
¡
cn
_VM...
.
.
›
.
_
‹
,
!
.
.
A
-P
iu-u
:-
rt,‹¡D,
cn
‹
-
(a)
(b)
Fig. 4.4. Charging (discharging) paths for the
V
‹A
~
-1a
On
M:
um
+
_w‹f›
.
Ê
_?
E
DI
8:
:
H
+
.am
Q»
DI
8:
V
Clamping voltage through the auxiliary circuitry.
This feature in clamping voltage stabilization
transformer connection True-PWM-Pole circuits
is
is lost
when any of the modified
auto-
employed. The unidirectional auxiliary
switch offers only discharging paths preventing the clamping voltage from being higher than
the nominal value.
Note
that
when two
storage capacitors are used in the
DC
side, this feature
remains
tme only when the neutral potential is stable.
4.3.2.
Normal Auto-Transformer Connection of the Second Pole
As
discussed in Chapter 2, even though the normal auto-transformer connection True-
PWM-Pole promises attractive properties in terms of the
auxiliary switch current stress, auto-
transformer primary voltage stress and the auto-transformer secondary current stress, the
freewheeling current flowing in the auxiliary circuitry during non-commutation interval
renders
it
not applicable andthe transformer connection
is
preferred.
transformer connections need extra snubbing for the series diode.
The 'modified
auto-
76
For the proposed three level inverter,-the second pole
The
level structure.
can expect to
first pole (S2, S4, S3, and
S34),
and
a normal
S32) is
modified auto-transformer connection
two-level structure and transformer connection or
inevitable.
(S2, S3, S32
however,
is
quite distinctive
is
from a nonnal two-
Because of the existence of the clamping capacitance, no freewheeling current
flow
through either the auxiliary switch or the auxiliary diode, if the normal
autoz-transformer connection is used.
As shown
current
in Fig. 4.5, suppose that after the
flows through
Lr,4, N2°, S34, C3,
commutation for tum-off of S4, a residual
and D,. The clamping capacitance
C3, will
then get
discharged and a voltage difference between C, and C3, will arise, which tends to resist the
residual current until
it
Such being the
returns zero.
phenomenon discussed
case, the
specific configuration.
in Chapter 2
exists in this
And the normal auto-transformer connection True-PWM-Pole becomes
practically applicable for the first pole. This alternative
with essentially the same
current stress
no longer
'result as
was
the transforrner connection except
which is nearly halved.
__
D1lD
Í-ru
¡L¡H
sal
1:
al
í
5:13
.NI
+‹›
DSM SM
D¡¡z°.l
D3;
5:13
C"'
N2
D3,
°_l
SH
S
C2
the auxiliary switch
for.
Dz c,z
s
-fi
prototype
5?
Dl?
‹_
--C1
“_
O
3kW
'
-T-z=
Ã
also tested in a
.Nz
NI
H
S32 Dsflz
al
Lm
Ã:
A
4-
-
.
.13
›
Iload
I|_¡¡3
_
,°lZ§:
Cú
D3
S3
D
°-l
S4
:
.ZS
D4
Cm
'Í
Fig. 4.5.
Modified configuration of the True-PWM-Pole three level capacitor clamping
inverter,
with
transformer connection for the second pole and normal auto-transformer connection for the first pole.
4.4.
Topologies for Multilevel case (M>3)
Transformer connection True-PWM-Pole zero voltage switching scheme can be
extended to multilevel case (M>3). Fig. 4.6 demonstrates a four level True-PWM-Pole
capacitor clamping inverter, where
S23, S,3”
and
S1,
Sf;
S23, S23”
and
S2, S2”; S33, S33°and S3, S3”
I
:S1
S
W
I
'IS
N1'
,I
I
il
.__
Sm
°
No.
NO O
.
A
ll
ll
A
.l
A
A
A
Szwl
:s,
.__ s,
i
I
NZ'
S21: 0-I
S;
I
Sla
›z›~`-_,.z
J
¬«p,.....~.
z
t.
¡-
cóz.
IS¡
0-I
C
U
Fig. 4.6.
.,
Transformer connection True-PWM-pole zero voltage switching scheme extended
to multilevel capacitor
_
clamping inverter (M>3), example of four level case
e
.¬
1;
1-
S13'
sla
.Í
Í.
_
z
S23'
S2;
.Í
_Y_
.L
S33'
S35
Í.
Í.
T
.~
L
Fig. 4.7.
^|
ARCPI zero voltage switching scheme extended to multilevel capacitor clamping inverter
(M>3), example of four
level case.
78
form three poles. Each pole
is
independent- of the others provided that the clarnping capacitor
voltages are stable.
The operation of each pole
is
the
same as the normal transformer connection True-
PWM-Pole except for the separate inductor and discrete auxiliary switch. The auxiliary
blocks .the same voltage as the main switch which enhances
In
addition,
the
Sb' and
S2,
Sj;
S3,,
Q
(ARCPI)
is
also
A four level case is shown in Fig. 4.7, where S,,, Sm” and
S3,”and S3, S3'
auxiliary switches block half of the
4.5.
applicability.
Auxiliary-Resonant-Comrnutated-Pole-Inverter
extensible to multilevel case (M>3).
S,, S,'; Sza,
its
switch
form three poles each work independently. All
main switch voltage.
Conclusions
The proposed transformer connection True-PWM-Pole
inverter achieves zero voltage switching
three level capacitor clamping
of the main devices and zero current switching of
the auxiliary devices, withoutprovoking any voltage/current spikes across the
main or the
auxiliary switches, without yet requiring any additional current monitoring or controlling.
0
The proposalfeatures a interesting second merit
in stabilizing the
the existence of the charging/discharging paths established
by the
clamping voltage, due to
auxiliary devices for the
clamping capacitor. In the meanwhile, due to the clarnping capacitor involved in the
resonant current paths, the normal auto-transformer connection
True-PWM-Pole becomes
applicable in this case without the problems of the freewheeling current and the residual
current,
which achieves the same property as the modified auto-transformer cormection
True-PWM-Pole without any voltage
ø
spike across the auxiliary switch.
Both transforrner connection True-PWM-Pole and
multilevel case
PWM-Pole
ARCPI
(M>3) with
the
same performance
ARCPI schemes
are extensible to
as in the two-level case.
The True-
extension requires considerable magnetics and diodes, while in the case of
extension, center-taped storage capacitors must be used and additional monitoring
and controlling become necessary.
79
.
Chapter 5. Designing and Experimentation of the True-
PWM-Pole Three Level Capacitor Clamping Inverter
IGBT
Hardware
and relevant experimental
details
results are presented.
Prototype Specifications
A scaled laboratory prototype, as shown in Fig. 5.1, has been
of which are shown in Table
~,-e
.xi
,...,..
`
The specifications
Table 5.1. Prototype specifications
a
~›
set up.
5.1.
..¿.-
.fz
D.C input voltage
Vdc=700V
Output voltage
V‹,|,,,,,=l40V
Modulation index
M=0.62
Output power
P°=3kW
Load current
Im,,=2 1 .SA
Switching frequency
fc=6.5kHz
Í
..z_
.‹.z›z.›'-
half bridge
transformer connection True_-PWM-Pole three level capacitor clamping inverter
prototype.
5.1.
3kW
700V supply
Abstract: This chapter addresses a proof-of-concept
.-
«tm-.›
-.z.~.
I
"
sr
:_
C..
¡>'9
‹_
C1
ao
Du4
ic
_'
O
LH4
Dszl
Sm
NZ'
_;
'UN
'
cz
°-l
Cm
Szs
as
DM
Da3
IN2
Ni-0
Dal
›
D2I|
P*
Nr
H
Dm SM
H
Szz
mz
Daz'
Dí\2°‹'
Ã:
A
Lai,
‹_.
ima
D¡,3`°-I
S3
°l
S4
Fig. 5.1. Circuit
Lt
-_-P
__
'IM-1
à _-
CÍ
"›¡o
Vu
¿
D3 Cfl
_
.
C4
Dz
S
fl
Ã:
D4 Ca
Diagram of the 3kW half bridge laboratory prototype.
Ro
80
'
5.2.
Main
5.2.1.
Circuit Designing
Power Supply
Three 300V/5A
is
DC supplies are associated in series. An iron laminated l5mH inductor
put in series with the supply to suppress the ripple current.
5.2.2.
DC link Capacitor
The designing
i
capacitance
is
criterion in the laboratory case is the
given by
DC
voltage ripple across
(5.1):
1
( 5.1 )
AVdc
T
the switching period and Ip
where AVdc
is
peak
When maximum AVdc is set to be 3V, this gives C,=C2=
current.
the peak to peak voltage ripple,
In practice, the
between the
The
.
TI
c =
it.
DC
utility side
is
is
the load
1536uF.
link capacitance should be designed for transience de-coupling
and the load
Depending on the configuration of the rectifier side
side.
and the control of the whole system, the
result
can be quite
different.
The capacitors
C,=C2=3300uF, each with a nominal voltage of 350V.
in use are
_
H
5.2.3.
Clamping Capacitor
Sizing of this capacitor
V
is
two-fold.
voltage ripple, according to (3.10).
On the one hand, higher capacitance allows for less
And on
the other hand, smaller capacitance reduces the
clamping voltage transience duration, according to
(3.19).
Voltage ripple should be the major
designing criterion in practice. Further, capacitor intemal inductance and in particular
capacity to process the
The
heat
RMS current given in (3.9) must be taken into full account.
actual capacitance used
is
2750uF consisting of two 5500uF capacitors
each with a nominal voltage of 250V.
5.2.4.
its
in series
-
Output Filter
The primary designing
inverter'
objective
is to
output reduced to a given extent.
the dominant output voltage harmonic
is
have the dominant harmonic component
From
(3.5), for the
at the
given modulation index of 0.62,
calculated to be 0.35 of the
fimdamental component.
T
To keep
the
THD less than 5%,
With a second order low-pass
mb =
,/Lfcf
where
fc is
81
the dominant hamionic
filter, the cut-off frequency (ob
to
be
less than
can hence be decided by
= 2fi(2fc _ fm”0(2o1go.o3-2o1go.3s)/ao
the switching frequency and fm
Another designing objective
-
component need
is to
is
3%.
(5.2):
(52)
output fundamental frequency.
avoid possible resonance
at the output, especially in
a
closed loop system. For this purpose, the declining factor given by (5.3) must be considered.
L
ô=
zzao
Ii
(5 3)
cf
'
Defineô =0.65 and combine
`
The
talcewinto
.~
P
»»
..,¬›»
and
(5.3), the result will
be Lf=0.37mH and C,=4.5uF.
actual values used in the prototype are L,~=l .45mH and Cf=l2uF.
A practical
‹..
(5.2)
_
output filter designing, besides the preceding considerations, should also
account such other factors as load short circuit protection, load imush limiting, low
frequency voltage stress
etc.
..-‹‹.
¡›
‹.
5.2.5.
Main Switches
'
The main switches
SKM50GB123D.
S,-S4
IGBT modules
Ratings and the main electrical and thermal characteristics of which
(including the inverse diodes) -are
5.3.
used are two Non-Punch-Through
shown in Table
5.2.
Resonant Circuit Designing
5.3.1.
Resonant Components and Auxiliary Transformer
According to sub-section 2.4, the results of the designing are presented in Table
5.3.2. Auxiliary
Switches
(
Sa,-SM)
According to-Fig. 2.ll(a) and
maximum peak and RMS
Fig. 2.l2(a), for load with
currents of the auxiliary switch are
Blocking voltage of the auxiliary device
is
the
switch.
peak current of 30A, the
54.2A and 8.4A
respectively.
same with the main device.
Devices used in the prototype as auxiliary switch are
main
5.3.
SKM50GBl23D,
the
same
as the
Table
5.2.
IGBT module SKM50GBl23D
symbol
characteristics
values
conditions
O
Ic
TcaSe=25 C/80
Icm
O
SOA/34A
C
IOOA/6 8A
h
'T¢zse=25°c/ 80°C
Vces
l200V
TJ
-55°c- +15o°c
Vcesat
vge=15v, 1¢=5oA, Tj=2s°c / 15o°°
4.5V/3.5V(max.)
tdon/tr
vc¢=óoov,vge=15v, 1¢=5oA,
80nS/l 50nS
Rg‹›n=Rg‹›ff=3.3
Q ,Tj= l25° C
Vcc=600V,Vge=l5V, Ic=50A,
tdoff/tf
Rg‹›n=Rg‹›ff=3.3
VF(diode)
250nS/1 50nS
Q ,Tj= l25°C
2.9V
IF=5oA, vge=ov, Tj= 1 50°C
Qrr(diode)
s
trr(diode)
r¡=125°c
250nS
T,-=1z5°c
per
Rthjc
o.31°C/W
o.9°C/W
o.o5°C/W
IGBT
DIODE
Rthjc
per
Rthch
per module
0uC
l
20nH
Lce
Table
Resonant
1.
capacitor
loss
Resonant
I.
inductor
bobbin,
Transfo rm CI'
1.
5.3.
Resonant components and transfonner designing results
maximum tum-off
Capacitance: C,=0.1uF, 2. Type: low-loss polypropylene, 3. Estimated
lW.
Inductance: L,=l5uH,
3.
2. Structure:
36 tums
ISAWG
copper wire
wound on
air core
Current rate of changing l4A/uS.
60 tums twisted wire
ratio:
k =0.4,
2. Structure:
primary and 24 tums
tvvisted
wire (15 strands
Transformer
ferrite core, 3.
24AWG)
in the
(7 strands
secondary
Allowed equivalent loop resistance around 2.29.
24AWG) in the
wound on E65/29
83
5.3.3, Auxiliary
The
Diodes (Dsa,-DSM, DSM'-Dsa4°)
current stress of the auxiliary diodes
blocking voltage of the auxiliary diodes
Components used
the
in the prototype are
characteristics are given as following
I1=Av=30A,
is
is
k times of that in the auxiliary
switch.
The
same with the main device.
HFA30TA60C
in
:
VRwM=600V, VF1v1=l.2V; R1hj¢=0.85 ° C /
TO-22OAC
case, ratings and
W and trr.ma×=60nS.
Thermal Designing
5.4.
A
Thermal designing takes account of merely the conduction losses of the main devices.
Switching losses of the main devices as well
.as
auxiliary devices are neglected. This simplification
~
mz-~›
~›‹›
¬
is
the switching/conduction losses of the
reasonable in the prototype case.
For calculation of the conduction loss in the inverter instance, a conduction loss model
hasnheen recommended, which represents the device as a constant voltage drop in series with a
nonlinear resistive element during conduction [l39]. This nonlinear element
is
further
simplified to a linear element so that a closed form solution can be reached. Conduction loss
.
.-,za-Y
.
»_¬~›-~:--_~~--
z
-z-
of the four devices
is
then given by
(5.4):
.tw
= 4(Pon-s + Pon-D)
Plossw-on
where:
=
P,,,,_s
P,,,,_D
1
E
=
1
1,,Vce_,,(;
1
1
511,1/F(,(;
+
M zos 9) +
Í
M
- Tzosâ) +
Device models for the
(54)
'
«/É
M
1§Rce(íä + 5; cos â)
Jš
1f,Ra,,(š-\/;[¬-
IGBT and
M
5%-cosa)
(5.5)
(5.õ)
the reverse diode are given in (5.7) and (5.8)
respectively:
Vcesat
= Vce.o + [Rae
VF = VF_0 + IRak
(57)
(5.8)
84
VM and Vw are the IGBT and reverse diode voltage drops at zero current, and Ro. and
Where
Rak are the resistive elements of
IGBT and
SEMIKRON
From
diode.
data-sheet [140],
Vce_oS1.5+0.002(Tj-25°), RW=0.O25+0.000l(Tj-25°), Rak(125°)=22mQ and VF,0(125°)=l.2V.
According to
cos9 =
1, load
(5.5)
and
(5.6),
assume a modulation index M=0.62, load power factor
peak current Ip=30A and junction temperature Tj=125°, the loss distribution
and the total loss are calculated to be: Pon-s=l7.9W, Pon-D=4.04W, Ploss-on=87.8W.
Then, for a given junction temperature upper
heat-sink
is
required thennal resistance of the
given by (5.9) (four devices share a heat-sink):
-Ta -2(Pon _ +Pon _ D )Rthch -Pon _Rs thjc.s
sP
T: /max
Rthha
limit, the
where: Tjmax
(59)
loss-on
is
the given
maximum junction temperature.
Ta is the operation ambient temperature.
case thennal resistance per IGBT.
Rthjc.s is the junction to
Rthjc.D is the junction to case thermal resistance per diode.
~
the case to heatsink contact thermal resistance.
Rthch
is
Rthha
is 'the
Setting
heatsink to ambient thermal resistance.
Tjmax=l25 ° C and
substituting the
-
known parameters
one will
into (5.9),
get:
V
Rzhhz=1.o5°c/w.
For the prototype, a
200mm
square heat-sink
is
mounted
vertically
on a wooden base
accommodating the two main IGBT modules (with thennal compound). The two auxiliary
IGBT modules
(with thermal compound)
insulation layer
and thermal compound) are mounted on another heat-sink of the same size
together with the four diodes (with thin
assembled on the same base.
5.5.
mica
'
r
IGBT Driving Designing
5.5.1.
Main IGBT Module Driving
Intelligent single
device.
IGBT
driver
`
SEMIDRIVER SKHIIO
The main feature of this driver is summarized
is
as following:
used
for..
each main
IGBT
0
Improved output buffer enabling switching current up to 400A
0
Built-in soft tum-off mechanism enabling high
0
Built-in
at
20kHz.
-
DC bus voltage operation.
DC/DC converter (4kV insulation) easing the driving supply arrangement
0 Information transfer (driving, protecting) by
ferrite
transformer offering high dv/dt
immunity (75kV/uS).
0
Optional input signal level: 15V/SV.
0
Extemal
fault reset.
Electrical specifications
Table
5.4.
and
settings
of the SKHI10 driver actually used
is
given in
-
Table 5.4. Specifications and settings of SKHIIO driver
Electrical Characteristics
*V
.Z
C)
Value
Vs
supply voltage
15V
Is
supply current(max.)
0.5A
vG(‹›n)
tum-on gating voltage
l5V
VG(off)
turn-offgating voltage
td(on)
input-output tum-on propagation time
luS
td(oft)
input-output tum-off propagation time
luS
td(error)
error input-output propagation time
luS
VCEsat
Vce reference
5.2V
Rgon
intemal tum-on gate resistor
Rgoff
intemal tum-off gate resistor
tmin
fault indication delay
(R¢e=1s_1<
5.5.2. Auxiliary
Intelligent
each auxiliary
for fault indication
220
22
time
Q
1.5uS
Q ,c‹ze=33op1=)
fault indication outlet (pin J3' shorted)
low-logic
IGBT Module Driving
medium power double IGBT
driver
SEMIDRIVER SKHI23/ 12
IGBT driving. The major features of this driver are:
0
Output buffer enabling switching 200A
0
Soft tum-off enabling higher
0 Built-in
-8V
à
Error logic
0
°
Term
symbol
×.-
(Ta=25
at
20kHz.
DC bus voltage.
DC/DC converter for driving power supply.
Ferrite transformer information delivering enabling high dv/dt immunity.
0 'Built-in adjustable interlock circuit.
is
used for
86
0
Optional input signal level:
0
Automatic
fault reset
Electrical specifications
15V or 5V.
when both inputs are zero.
and
Table
settings
5.5.
of the driver are summarized in Table
5.5:
Specifications and settings of SKHI23/ 12 driver
Electrical Characteristics
(Ta=25
°
C)
Term
symbol
Value
Vs
supply voltage
15V
Is
supply current(max.)
0.5A
VG(on)
tum-on gating voltage
15V
VG(oft)
tum-off gating voltage
-8V
u
td(on)
input-output tum-on propagation time
l.4uS
td(off)
input-output tum-off propagation time
l.4uS
td(error)
error input-output propagation time
l.4uS
VCEsat
Vce reference
5.2V
Rgon
intemal tum-on gate resistor
Rgoff
intemal tum-off gate resistor
tmin
for fault indication
.fault indication
22€!
22
delay time
Q
l.5uS
(R¢e=1s1<Q ,c‹ze=33opF)
5.5.3.
Error logic
fault indication outlet (pin J2 shorted)
tTD
interlock time
(RTDl,RTD2
low-logic
not installed)
l0uS
Zero Voltage Detecting
According to Chapter
each main device voltage must be detected so that
2,
on at the moment when the voltage across
vzz
GDH
it is
zero.
R2 l.5kQ
1
3
Di lN4937
C
D|
D2 lN4l48
N| ZN 2907
SKHI l 0
High Current Driver
t:
R] 5609
5
ä
'
Goffl
E
2
o
I
I
Zero voltage detecting
Fig. 5.2.
Zero voltage detecting
circuit
circuit in the prototype.
it is
turned
87
The
circuit
used in the prototype
Gm, can only reach the output terminal
is
shown
in Fig. 5.2.
B when the
near zero (threshold decided by R, and R2).
The
PWM tum-on command at
device collector voltage VCE declining to
PWM turn-off command at Gm» is sent directly to
the output terminal B.
Note
that the
tum-on
altered with the adding
signal property (turn-on resistance etc.) of the driver
of the zero voltage detecting
circuit.
However, dissimilar
switching where turn-on performance (diode reverse recovery di/dt)
by the tum-on
signal property, the
would be
to hard-
significantly affected
is
tum-on performance under zero voltage switching
not
is
affected to any considerable extent.
Protection function of the
SKHIIO
driver
indication during the commutation resonance.
must be disabled to avoid
Device protection
is
false failure
then partly assumed by
the zero voltage detecting circuit. Characteristics of the protection, however, are changed.
5.6.,
Control Designing
Control Requirements
5.6.1.
To
0
-
p
generate the main switch gating signals according to the
indicated in Fig. 3.2.
and
(S,
S4, -S2
and
PWM modulation
A dead time must be introduced between the complementary signals
S3).
The minimum/maximum pulse width must be
auxiliary switch gating signals.
0
To
strategy
set higher
than the
V
.
generate the auxiliary switch gating signals according to Fig. 4.2, the width of which
should be set according to Fig. 2.l0(a).
0
To give distinguishable
The
fault
control circuit designed
5.6.2.
Control Diagram
memory as well as manual reset.
shown in Appendix
is
5.2
and
is
explained below.
'
'
Clock signal generator U1: To use 214 addresses generating the 50Hz output, the clock
frequency Should bez f,,,,,=(1/50)/ 214 =s33kHz. The
generate this clock, where
R1=l0kQ
vco embedded in cD4o4ó is used td
and C1=202pF. R2 and R3 serve to convert the
15V output to TTL 5V for the next stage, R2=l0kQ and R3=4.7kQ
.
CMOS
88
Address counters U2/U3:
Two CD4040s
are cascaded to generate the 214 address
signals.
An EPROM 27256M
Gating signals generator U4:
switching signals, the
BASIC program is
maximum commutation duration is
width
is set at
l4.4uS and the
listed in
1l.3uS. Based
Appendix
is
used to generate the eight
5.1.
According to Fig. 2.10, the
on which, the
minimum/maximum
auxiliary switch gating signal
PWM pulse widths are setat 28.8uS and
124.8uS respectively, with a modulation index of 0.62. Dead time of 2.4uS
that
C24-C3l
are imperative to suppress the
Signal level converter UI 1/UI 2:
to
15V
Note
EPROM output noise, each valued at l5nF.
Two SN7406s
5V
are used to convert the
when the
so that to enhance the noise immunity
drivers. Resistors
is inserted.
signal
back
switching signals are delivered to the
R4-R1 1 each valued at 2.2kQ are pull-up resistors for SN7406s.
Fault trip-ofl U5/U6: Six OR gates are used to enable shut-down in the case of fault.
Auxiliary devices fault
built
with a automatic reset
Thus extemal
memory U7: The double
after fault,
which
is
drivers for the auxiliary devices are
not favored in terms of fault identification.
memory U7 is offered as a remedy.
fault
Fault summing and manual reset U9/UIO: The whole prototype will be shut
the case of any individual device fault. Fault
at
Capacitors
5.7.
2.2kQ
in
memory can only be removed with manual reset
button. This designing enhances operation safety of the prototype. Resistors
valued
down
are extemal pull-up resistors for the fault indications
C2-C7 each valued at 100pF provide noise immunity
Rl2-R17 each
from the
drivers.
for the fault indications.
Experimental Results
Fig. 5.3
shows the output load
5.4
shows the three
the
main switch
side voltage and filter inductor current waveforms. Fig.
level output voltage VAO. Fig. 5.5
shows the
ZVS commutation process of
S3 during switching cycle. Further in Fig. 5.6, the details
i,0,d=21A are shown, for a predicted dv/dt of
90V/uS (averaged over
1,2
-tn) and
l4A/uS, the experimental values are about 90V/uS and l3A/uS respectively.
the details of tuming-off at i,°,d=24A are shown, for a predicted dv/dt of
over
t,
- t6 ), the experimental value is about 146V/uS.
of tuming-on
And
di/dt
at
of
in Fig. 5.7,
152V/uS (averaged
4
Besides the cornmutation processes of the switch, the main .freewheeling diode
commutation processes are also shown in Fig.
5.8
and Fig.
5.9.
lload
<l-
/Vo
/_\
/
-
J
»/
z
100V/Div; IOA/Div; 5mS/Div
Fig. 5.3. Experimental output voltage
and filter inductor current.
.Ill
M0
Illàlz
_ _|i_|i1›||1mlm||
Illllllllllllllllll
_¡_________
Illllllllflll
Hlllllllllllllllllll.
.
í lmnmmlilr
IIIIIIIIIIIIIIIIII |›|r|«||r||||
|ll|!|!|!
II”I'IlI'IlI'IiIIIIII
l0Ov/Div; 500uS/Div
Fig. 5.4. Experimental inverter output voltage.
--”'"/Fal
Vss
Mv»--â=
li
»¬"W~
v._~f¬//Fl'
Í
\\
V1;
ss
"____
l.00V/Div; l0A/Div; 20uS/Div
Fig. 5.5.
ZVS commutation of the main switch (S3).
__""^T\
VS3
\\
/ \/-/\ _vz¬¬z-z\/‹-›--É
\\
Ís3
«_
Í
100V/Div; IOA/Div; 2uS/Div
Fig. 5.6.
se
|
F"
Extended tum-on process of S3.
|" "W183
I
/\/\_/^»/"'°\|¿
V
/
›r\
/
VS3
_
100V/Div; IOA/Div; 2uS/Div
Fig. 5.7.
Extended tum-off process of S3.
L....'....L..¿.`....¡....
Í
....¡
Vss
_..¡¡II
í,
.-...
_...
zv-¬
.mm-_-.__________________._
É
d
51%
100V/Div;l0A/Diví; l 0uS/Div
.
Fig. 5.8.
1
›
Tum-on process of D, (L,=0.45mH,
I
1
C,~=l2uF).
2
91
.
.
.
.
.
.
..
ins
100V/Div; 1 OA/Div;5uS/Div
Fig. 5.9.
Fig. 5.10
i,0ad=22A.
Tum-off process of D,
(Lf=0.45m1-I, Cf=l2uF).
shows the ZCS commutation process of the
auxiliary switch (Sá/DS,3) at
For the predicated conunutation duration of 9.8uS according to Fig. 2.10(a), and the
predicated peak current of 46.3A according to Fig. 2.11(a), the experimental values are 9.5uS
and 46.5A respectively.
Fig. 5.11
shows the resonant inductor current waveform when
íhmd =0A.
For the
predicated commutation duration of 5.9uS and the predicted peak current of 24.1A, the
experimental values are about 5.5uS and 23.5A respectively. In the meantime, Fig. 5.12
shows the resonant inductor current wavefonn when
commutation duration and peak current
are about 9.5uS
Íhmd =22A.
The experimental
and 46.5A, which are in accordance
with the predicted values of 9.8uS and 46.3A according to Fig. 2.10(a) and Fig. 2.1
Jr
Vsê;
~
<*
Ísas
_
,_.-J-_---J¬¬~.^^
_l.
1
md
/"_|\
.LW
.
.
LL! ,L
-
-
100V/Div; l0A/Div; l0uS/Div
Fig. 5.10.
ZCS commutation
of the auxiliary switch (Su).
1(a).
92
`
/
_....__:F:__~_...,...=___.
___z,,l,.
/T\
.
\ I Lf23
\
n
7'|7À~0a;d_
FT
_¡_-:_
31:
l0A/Div; 2uS/Div
Fig. 5.1
Resonant inductor current waveform
l.
_/\
-
lload
z
I
|
1
1
M
/
_,
at ik,,,,=0A.
'
Lr23
'
.
~="'_“_'"'
<r
|
\t^Wzz_.t_
l0A/Div; 4uS/Div
Fig. 5.12.
5.8.
Resonant inductor current waveform
at i¡o,,,=22A.
Conclusions
The foregoing presentation of the experimentation justifies the following conclusions:
0
The proposed scheme ensures zero voltage tum-on and
capacitive tmn-off of the
switches, without causing any voltage/current spikes across these switches.
0
The proposed scheme ensures
main
`
inductive turn-on and zero current turn-off of the auxiliary
switches, without causing any voltage spike.
0
Main freewheeling diode works with
Oscillation
transfer
0
may
zero voltage turn-on and zero current tum-off.
occur during the diode forward recovery process due to the fast current
from the snubbing capacitors to the diode
Characteristic curves presented in Chapter 2 regarding the
inductor peak current and resonant inductor
bridge prototype.
RMS
commutation duration, resonant
current are verified
by the
3kW
half
93
Appendix
BASIC program for generating the gating signals in EPROM 2725 6M
5.1.
970 U = 1 'DATA OUTPUT LINES COUNTER
980 OPEN "A:SPWM.DAT" FOR OUTPUT AS #1
990 PRINT #1, ": 10"; 'FIRST DATA OUTPUT LINE FORMAT
1000 PRINT #1, "000000"; 'FIRST DATA OUTPUT LINE FORMAT
1010 FOR I = 0 TO 127: 'SELECT SWITCHING CYCLE
1020 RAI = 0: RA2 = 0: RA3 = 0: RA4 = 0 'DEAD TIME/AUXILIARY
1030 FORK = 128 * I TO 127 + 128 * I: 'SELECT ADDRESSES
1040IFO<=K-I* I28ANDK-I*
128
COMMANDCOUNTER
<=64THENVB=K-I* I28ELSEVB= 128-(K-I*
'TRINGLE VB GENERATOR
1050 VA = 64 - VB 'TRINGLE WAVE VA GENERATOR
1060 PI = 3.14159
1070 VC = 32 + 20 * SIN(2 * PI * K/ 16384) 'MODULATING
1080 IF VC > VA THEN SI1 = 1 ELSE SI1= 0
1090 IF SII = I THEN RAI =RAl + 1 ELSE RAI =RA1
1100 SI4 = I - SI1
128)
WAVE GENERATOR
1110IFVC<VAAND64<=K-I* 128ANDK-I*128<=127THENRA4=I+RA4ELSERA4=RA4
1120 IF VC < VB THEN SI3 =1 ELSE SI3 = 0
1130 IF SI3 = THEN RA3 = RA3 .+ ELSE RA3 =0
I
1140 SI2
1
=1- S13
I150IFVC>VBAND64<=K-1*128ANDK-I*I28<=127THENRA2=I+RA2ELSERA2=RA2
<= RAI AND RAI <= 2 THEN DA4 = ELSE DA4 = 0 'DEAD TIME
1170' IF <= RA2 AND RA2 <= 2 THEN DA3 = ELSE DA3 = 0 'DEAD TIME
1180_,IF <= RA3 AND RA3 <= 2 THEN DA2 = ELSE DA2 = 0 'DEAD TIME
1190 IF <= RA4 AND RA4 <= 2 THEN DAI = ELSE DAI = 0 'DEAD TIME
1200 IF <= RAI AND RAI <= I2'TI-IEN SA4 = ELSE SA4 = 0 'AUXILIARY SIGNAL WIDTH
1210 IF 1 <= RA2 AND RA2 <= 12 THEN SA3 = ELSE SA3 = 0 'AUXILIARY SIGNAL WIDTH
1220 IF <= RA3 AND RA3 <= 12 THEN SA2 = ELSE SA2 = 0 'AUXILIARY SIGNAL WIDTH
1230 IF <= RA4 AND RA4 <= 12 THEN SAI = ELSE SAI = 0 'AUXILIARY SIGNAL WIDTH
1160 IF
1
I
1
I
I
I
1
1
I
I
1
I
1
1
1
1240 S1 = SI1
DA4: S2 = SI2 - DA3: S3 = SI3 - DA2: S4 š S14 - DAI 'MAIN SWITCH COMMAND
-
1250A=SA4*2^7+SA3 *2^6+SA2*2^5+SAI *2^4+S4*2^3+S3 *2^2+S2*2^1+S1*2
^10
'
PRINT #1,
1260
1270
1280
1290
1300
1320
1330
1350
1360
1370
1390
1400
1420
1430
1440
1450
1460
1470
1480
1490
1500
1510
1520
S1;
SAI; S2; SA2; S3; SA3; S4; SA4; VC; VA; VB; K; A
K = U *16 THEN
=
U U+
IF
1
IF
TOTAL < 255.5 THEN
IF TOTAL < 15.5 THEN
PRINT #1, "00"; HEX$(TOTAL)
ELSE
PRINT #1, "0"; HEX$(TOTAL)
END IF
ELSE
PRINT #1, HEX$(TOTAL)
A
END IF
TOTAL = 0
PRINT #1,
IF K <
-
":";1-IEX$(K/(U
16 THEN
PRINT #1, "000";
ELSE
IF
K < 256 THEN
PRINT #1,
ELSE
IF
"00";
K < 4096 THEN
PRINT #1,
END IF
END IF
"0";
-
1));
V
94
1530
1540
1550
1560
1570
1580
1590
1600
1610
1620
1630
1640
1650
1660
1670
1680
1690
1700
END I1=
PRINT #1, I~IEx$(I<);
END IF
TOTAL = TOTAL + A
IF A < 15.5 THEN
"00";
PRINT #1, "0"; P1Ex$(A);
ELSE
PRINT #1, HEx$(A);
END IE
NEXT K
NEXT I
IF TOTAL < 256 THEN
PRINT #1, "0"; HEX$(ToTAL)
ELSE
PRINT #1, HEX$(ToTAL);
END IE
cLosE
END
__
___
l_
D
____
EE
AMM
°_
š
ÚMW
I
âš
J
__
E
V
_!
__'
V!
Qëgi
“__
EE
flw
ë
___
E
EÉ
“MH
“Mw
Í
*_
_
__
À
/š_
_
E
E
E
H
imã
_
“___
/`
\.|
_
_
_
_;
_
__
H
À;
/*__
›
MÊÊÊO
il”
U
›
â
__
_í
8
U
_!
E'
têaäã
E__§
025
_
__
1
Á
___
__'
_
_
3
__
äüifãg
_
__
'_
E
š
š
/
É
~
_
_
“H
_!
:__
_
I
_
__
:_
_
:_
u
_
U
p
E
2o^:\/Säimzë
E
|
¡
|¡
¡_
|||
“WWW
mg
E
š
n
_'
_
_
H
_
_
_
É
I”
_¡
V
E
___*
:__
aw
_
_
E
___
gw
_
É
:S
:EW
E
:___
šã
_
_
EW
__!
:S
:___
§_`_%
E
_U
_
'_'
__
BÊWÊV
R
Bbgo
H
_
_5
E0
E5B50
_
“Nú
Uá
__
š
E
/_\
2 É
___
_‹
3 2 É
__
É E E EE
8E
_;
_;
_;
__,
E
_ _ _
__
II
:Il
l
ššmwgnâ
›
_
E
II
_
_
_
I
i¡
~.
~.
E8883 E
H
E
5
_
r
_"
__"
E
5
E
“_
___
II
II ll
›
É
8
"_
E H 5EE3
E0
L¬__í_ÊÊ_š_m
5
_
__
__
_
E É
__
__
›
_
š
tb
/_\
É l`
_
x
R
H
É E
É
É
E
'_
n E
__!
5 5É
u
_!
E
`
N"
I
K
_
__
/_\
UÉ¡a
Ê
ll..
_
E
›
1
__”,
É
'
É
E
96
Chapter
6.
Operation of the Neutral-Point-Clamped (NPC)
llnverter
Abstract: This Chapter explores the neutral potential stability of the Neutral-Point-
Clamped (NPC)
inverter.
Steady
state stability,
dynamic
state stability
along with the stability
under non-ideal conditions are studied. The analyses are verified by PSPICE simulations.
6.1.
Sub-Harmonic
PWM Modulation of the NPC Inverter
shows the half bridge NPC
Fig. 6.1
and negative when
positive, zero
principle of sub-harmonic
S,
and
inverter circuit.
S2, S2
and S3 or
The output potential
S3
and S4 are
is
connected to
ON respectively.
PWM modulation is shown in Fig. 6.2. By intersecting a sinusoidal
reference mod(t) with two vertically shifted triangle carriers, a three level voltage
sinusoidal envelop
is
obtained at the output, which
-
ii
_E“
C2
vdz
rl
ó-v
__
D1
VAO =
>
S4
V ¿
D3
V A
D4
-
¡
(6.1)
A
sw
É
sw;
(val
SW=\.V/\o=V‹1|
SW=0_V^0=0
v^“
Leg Switching Function SW:
sw=|z s| ON, sz oN
sw=oz sa oN, sz ou
sw=-1: s4 oN, ss ou
Fig. 6.2.
Sub-harmonic
Sw;¡
V^‹›=-V.|z
.
PWM modulation for NPC inverter.
(sw-l)sw
___Í_'vd2
can be rearranged as
VAO =
od(t)=Msin(nml
llmld
Half bridge NPC inverter configuration.
(l+sw)sw
vdl
2
(6.1):
l
.
Fig. 6.1.
vw with
°2
A
0
Vd°
A
S1
___
Vzu
expressed by
is
'
¡
C|
The
(6.1)
(6.2):
+vz12) Jr? (val
Tvâz)
(Õ-2)
97
6.2.
Neutral Potential Steady State Stability
Under steady
state, vd,=vd2=Vdc/2, the
output voltage vAo is simplified to (6.3):
Vzz
vw = sw _”
( 6.3 )
2
where the leg switching function sw can be given in Fourier form by (6.4):
sw =
Z Aksín (kwmt)
(64)
lc
keK=l,3,5,...
where A k
is
the amplitude of the kth order harmonic, com
the load current im,
z...
'\
...sa
is
the fundamental frequency.
Then
written as (6.5):
is
äsin (kwmt _ ek)
l!oa‹ÍÍ.=
keK=l,3,5,...
where Z k Á âk
is
load impedance at harmonic order of k.
On the other hand, the current flowing out of
._._.
_ lo
ln
lload
_.
_
lload (1
_ sw z_.
)
,load
n
=-Vd_°{zzA A
4 k 1 k
k,l E
'
¢‹›s[(k~1)w
K,L
=
A
m 1]-22,4
k
k 1
which
'
in is
given by
(6.6):
(6 6)
_
further expressed
¢‹›s[(1‹+1)w
is
by (6.7):
z-0)
"
m z1}zísz'n(kw
k zh
concemed, only the
i
is
given by
"'
(6-7)
l,3,5...
When the neutral point potential
est,
in is
:_ sw 2.lload
Substitution from (6.4) and (6.5) in (6.6),
z'
the neutral potential
(6.8):
DC component in in is of inter-
98
z
z
n.dc
21,-
da m 0
"
O
From
‹õ.8›
.
perpendicular property, integration (6.8) equals zero. This result ímplies the neu-
tral point potential will
current flowing
6.3.
be stable under normal sub-harmonic modulatíon, because of the zero
fiom the neutral potential during the fundamental cycle.
Self-Balancing under Ideal Condition
When dynamic state is concerned,
after
suppose that the neutral potential diverges from zero
a perturbation, the output voltage will then be given by
(6.2).
While the first part repre-
sents the steady state voltage output, the second part of this expression, represents the output
voltage variation
AV»
=
T
wi
AVA0
resulted
from the neutral potential
drift,
_
_
in (6.9):
Wal _ Vaz)
(Õ-9)
Substitution from (6.4) in (6.9), AvA0 can be detailed
Av,,(,
which is rewritten
v -v
-4l4;dl{%§AkA¡ cos [(1z-uwmz]->¡š§AkA¡
'
k,l e
From
K,L
(6.10),
=
by (6.10):
( 6.10 )
cos [nz +1)ú›mz]}
l,3,5...
even numbered harmonics appears
at the output after the perturbation. In
the meanwhile, the load current response to this variation, recorded as
Aibad
,
is
given by
(6.11):
Azload =
_
ízí
vd1'Vz12
k,l e
where zj¿ gj
is
{š
K,L
Âkfíz
A/(A1
Éšcos [(k-l)a›m t-0k_¡]-š%]%cos[(k+l)‹um t-0k+¡]}
=
l,3,5...
the load impedance at harmonic order of j.
(611)
99
On the other hand, the current variation flowingout of the neutral potential is inferred to
be given by
^«"n
=
_ Aflozzd =
^"‹›
where Aio
especially
...ndo
(6.12):
is
^"1‹›zzâ(1
' SW2) ' ^"lz›zzz1 =
the neutral path current variation.
concemed, only the DC component of
z
(612)
-SW2^"1‹›zzd
When the neutral point potential
Ai" is
variation
of interest, which is given by (6.13):
(613)
A,-,,z(.,m,,
Based on perpendicular property,
Aim
can be simplified to
v -v
(A A )2
(A A )2
zíü
'“{zz---k
cosak-I +22-_-k
cosa
n.dc
k+l
(6. 14):
(614)
»
Ai
1
15
k,I e
kl
K,L
z
=
1
kl
/‹-1
Z
}
/z+1
I,3,5...
(6.l4) demonstrates that the sign of Ain_dc
(v dz - v dl ), the value of which
means
is
is
further dependent
is
always dependent on the sign of
on the part within the
bracket. This result
that after perturbation, a corresponding variation arises simultaneously in the current
flowing out of the neutral point, which rejects the perturbation.
From
(6.14), the following conclusions
ability in the half-bridge
can be drawn conceming the self-balancing
NPC inverter under ideal condition:
0
Self-balancing exists so long as the load
0
Time
constant of the dynamics
is
is
not pure reactive
((-)k_¡
¢1
š ,6k+¡
dependent on the following components:
1.
Modulation index: The higher the longer.
2.
Load impedance amplitude and angle: The greater the longer.
3.
DC link capacitances: The larger the longer.
_
¢:
š ).
100
The output voltage
Fig. 6.3 illustrates the mathematical process conducted above.
sponse (AVAO) to the perturbation
(vdl-vdz) leads to
reflected back to the neutral potential
M.
V‹1i"'z12
(1/dl
(Ain), rejects
the original perturbation.
1
-sw*
--
Av""
1
2
-Vd2)' =
^¡1""z1
¡¿0¡
Ai"
-SW2
recovers to
result is
its
shown
Table
^”"'¬”'”+
,
Vz1i'Vz¡2
1
is
mechanism
in the
NPC inverter.
been verified by PSPICE simulation. Refer to Fig. 6.1 and
and parameters for the simulation are given in Table
in Fig. 6.4. For a initial state drift
6.1.
of 100V, the neutral poten-
400mS. The dynamics
steady state after about
system characteristic which
6.1 gives the
that the neu-
Vz11'V‹12
Fig. 6.2, the circuit specifications
tial
_
0
self balancing ability has
The simulation
1
z“íÍAz,.dz
+
2
Fig. 6.3. Illustration of the self-balancing
The
So
when
kept constant.
tral potential is
+
load current variation (Aim), which
re-
exhibits typical one-order
similar to the case of the capacitor clamping inverter.
Appendix
PSPICE program for this simulation.
6.1. Specifications/parameters for
DC link
Vdc=800
PSPICE simulation of the self-balancing under ideal condition
Filter pa-
Lf=0. lmH
Operation
voltage
V
rameters
C¡=4uF
frequency
DC link
C,=4000
Load re-
R°=lQ
Fundamental
capacitances
C2=4000
sistance
fl=l0kHz
Modula-
M=0.4
tion index
f,,,=l00Hz
Initial
frequency
voltages
Vdl=300
Vdz=500
(V)
(UF)
Oahlfhm mn:
520V
'mdtihvcl uofmnnañon
ÀHLDÍÀIÂD
;
\/W
Vaz
"W
A
amv
Om:
Fig. 6.4.
=
V(I0,20}
rom:
MMMMMMMMMMMMMMMMMM
200m
PSPICE simulation result of the self-balancing
:icons
ability in the
400":
50011:
NPC inverter under ideal condition.
101
6.4.
.
Self-Balancing under Non-Ideal Condition
u
Analysis in section 6.3 has been conducted neglecting any circuit non-ideals which are
always inevitable in practical
circuit operation.
For the half bridge
NPC
concemed,
circuit
asymmetrical charging/discharging during the positive/negative output voltage semicycle will
lead to neutral potential
Such asymmetry can most probably be resulted from
drift.
gating/switching diversities or load transience
In an extreme case,
-
DC
etc.
`
component involved
in the sinusoidal reference causes
consistant charging/discharging unbalance over the neutral potential. However, while the
neutral
potential
drifts
away from
the
zero,
self-balancing
mechanism
simultaneously which tends to recover the drifted neutral potential.
depending on the load properties, modulation
index,
Up
is
activated
to certain extent
DC link capacitances etc.,
the neutral
point potential will be stabilízed at an new operation point other than zero where new
balance
r
reached. This conclusion has been verified with
is
specifications and parameters for the simulations are
are
shown
in Fig. 6.5
and
which corresponds
Fig. 6.6,
shown
to
PSPICE
simulations. Circuit
in Table 6.2. Simulation results
DC biases of 0.5V and -0.5V to the
reference respectively (carrier amplitude 10V, reference peak 4V). For the
400-V across C, and C2, Vd, and
\/dz
are eventually balanced at
,¬..
'z
ordër dynamics, which
simulation
is listed in
means a
Appendix
initial
280V and 520V
neutral potential drift of 120V.
voltages of
after the first
PSPICE program
for this
6.2.
.
Similar to the case of the capacitor clamping inverter, dead time does not affect the
balancing ability of the neutral potential. The influence in one semicycle
same influence
is
self-
cancelled by the
in the other semicycle.
Table 6.2. Circuit specifications/parameters for simulation of self-balancing under non-ideal condition
DC link
Vdc=800
voltage
V
DC link
C,=4000
Load re-
capacitances
C2=4000
sistance
(ur)
L,=0. lmH
pa-
Filter'
Operation
Q=l0l<Hz
Modula-
M=0.4
C
rameters
,
Í
C,~=4uF
frequency
Ro=lQ
Fundamental
frequency
tion index
f,,,=l00Hz
Initial
voltages
‹v›
vd|=4()0
v,,,=4oo
102
4sov
400V
-Z
350V
›-
°°°"
to
250V
Vd2
MWVW“^WVV\fvW\/\Am\/vvv\/vv\A/\/vwv
.
:
Own
100m;
50":
:
:
:
250ma
20011:
1501!:
:
35mm
:
3001!:
:
:
40011:
450m9
.
Tine
Fig. 6.5. Simulation result of the self-balancing ability
.W
-
/\/\WWWW\
under non-ideal condition, positive bias 0.5V.
MNmWWM~up
f
Àsov
Vaz
~
400V
350V
.
uma
:
:
200m:
|00ms
:
300m;
400m:
500m;
.
Tine
Fig. 6.6. Simulation result of the self-balancing ability under non-ideal condition, negative bias 0.5V.
6.5.
Self-Balancing in Three Phase NPC Inverter System
For a three phase system, actually the same mathematical procedure as the half bridge
case can be followed except for that the load neutral potential
analysis.
With a primitive perturbation
now must
at the neutral potential,
flowing into the neutral potential will arise simultaneously, which
Ainda:
3(v
"Vdz )
01216
cosâk
zh
'“"
(z2A,A.+,-ZA,A,(_,-J
be included to the
a variation in the current
is
given by (6.l5) [60]:
2
(6.l5)
103
keK=2,4,8,l0,l4,...
From
(6.l5), for
leL=l,3,5...
any perturbation of the neutral
current variation always has 'an appopriate sign
keeps the neutral potential from
6.6.
potential, the resultant neutral point
that rejects the original perturbation
and
drift.
Conclusions
1.
Neutral potential of the
NPC
inverter is self-balancing under the sub-harmonic
PWM modulation with non-pure reactive load. The time constant of the first order
dynamics
is
capacitances
2.
dependent on the load properties, modulation index and the
DC
link
etc.
Depending on the extent of asymrnetry,
typically resulted
mismatches, the neutral potential will be balanced to an
from gating or switching
new
operation point other
than zero, due to the self-balancing mechanism counteracting such asymmetry
once
it
arises.
104
Appendix
-
6.1.
PSPICE
simulation program for self-balancing under ideal condition
*Self-balancing under ideal condition
*triggering signals generating
vl 10 pulse (0 10 .lu 50u 50u .lu l00u)
e2 2 O value {v(l)-l0}
vmod 5 0 sin(0 4 100 0 0 0)
esul 6 0 table {v(l)-v(5)} (-le-2,10) (le-2,0)
esdl 10 0 table {v(6,0)} (2,l0) (3,0)
esu2 7 0 table {v(2)-v(5)} (-le-2,10) (le-2,0)
esd2 11 0 table {v(7,0)} (2,10)(3,0)
*main circuit
su3 16 24 6 O sswitch
ds3 24 17 dmod
du3 17 16 dmod
su4 17 25 7 0 sswitch
dsu4 25 18 dmod
du4 18 17 dmod
sdl 18 26 10 0 sswitch
dsdl 26 19 dmod
ddl 19 18 dmod
sd2 19 27 ll 0 sswitch
dsd2 27 20 dmod
dd2 20 19 dmod
dcl 40 17 dmod
dc2 19 40 dmod
*device models
.model sswitch vswitch(ron=0.01 roff=le6 von=4 vof%2)
.model dmod d(is=2e-15 bv=l500 tt=0 cjo=l p)
*DC link initial voltages
vdc 16 20 800
c2 16 40 4000u ic=300
c22 40 20 4000u ic=500
*load parameters
lload 18 41.1m
rload 41 40 1
cload 41 40 4u
2u 600m 0 2u uic
.options vntol=1m itl4=100 abstol=lm reltol=0.l
.tran
.probe v(40,20) i(dcl) i(dc2)
.end
itl5=0
b
u
Appendix
6.2.
PSPICE simulation program for self-balancing under non-ideal condition
*PSPICE
simulation under non-ideal condition
*triangle carriers and sinusoidal reference
vl 10pulse(010.1u 50u 50u .lu 100u)
e2 2 0 value {v(1)-10}
-
_
vmod 5 0 sin(0 4
100 0 0 0)
*sinusoidal reference bias
erro 42 0 value {-0.5}
*triggering signals generating
esul 6 0 table {v(l)-v(5)-v(42)} (-le-2,10)(1e-2,0)
esdl 10 0 table {v(6,0)} (2,l0) (3,0)
esu2 7 0 table {v(2)-v(5)-v(42)} (-le-2,10)(1e-2,0)
esd2 11 O table {v(7,0)} (2,l0) (3,0)
'
*main circuit
su3 16 24 6 0 sswitch
ds3 24 17 dmod
du3 17 16 dmod
su4 17 25 7 0 sswitch
dsu4 25 18 dmod
du4 18 17 dmod
sdl 18 2610 0 sswitch
dsdl 26 19 dmod
ddl 19 18 dmod
sd2 19 27 11 0 sswitch
dsd2 27 20 dmod
dd2 20 19 dmod
dcl 40 17
dc2 19 40
dmod
dmod
*device models
.model sswitch vswitch(ron=0.01 roff=le6 von"-=4 voff=2)
.model dmod d(is=2e-15 bv=1500 tt=0 cjo=1p)
'
*DC link initial voltages
vdc 16 20 800
c2 16 40 4000u ic=400
c22 40 20 4000u ic=400
*load parameters
11oad18 41.1m
rload 41 40 1
cload 41 40 4u
2u 600m 0 2u uic
.options vntol=1m itl4=100 abstol=1m reltol=0.1
.tran
.probe v(40,20) i(dc1) i(dc2)
.end
itl5=0
_
106
Chapter
7.
True-PWM-Pole Neutral-Point-Clamped (NPC)
Inverter
True-PWM-Pole
Abstract: This chapter introduces a transfonner comrection
inverter. After
discussed.
a brief review of the existing work, the proposed circuit and
The True-PWM-Pole and
the
ARCPI
its
NPC
operation are
are then further extended to the diode
clamping multilevel inverter (M>3). Experimental
results
from a
3kW
half bridge True-
PWM-Pole NPC inverter are given finally.
7.1.
Review of the Existing Work
Literature review
shows
inverter with soft switching. Earlier
auxiliary
network
work may be
network must be established to
shows the
and
NPC
traced back to the thyristor times
when
(NPC)
tum-off of the thyristor switches. Fig. 7.1
assisted
by the McMurray commutation
NPC
which can be regarded as zero current switching
meaning. Auxiliary thyristors A4 and A2
assist S2
assist the
thyristor three state inverter
[33],
have associated the
that several previous publications
S4.
However, auxiliary
voltage, rather than half of it as the
assist the
thyristors
Vdc/1
i
S'
az
4
^*
vA
¡Ioad›
O
S.
“"°"
S2
I
1'
Fig. 7
.
1.
and S3 while A3 and A4
A4 and A4 have to block the whole
I
C|
thyristors S,
main thyristors do.
fl
-
main
inverter in the present
^4
A
_
v~
I
Circuit diagram of the three state thyristor inverter.
DC
link
107
DC
Besides zero current switching, both resonant
zero voltage switching methods have been considered for the
NPC
inverter [l43], as
shown
in Fig. 7.2,
while A3 and A4 assist S4 and
S2. C,23
A1 and A2
and resonant pole [143]
link [142]
NPC
commutations of
assist the
S3
1/z
and
serves as snubbing capacitor for the center
switches S2 and S3. All the auxiliary switches A,-A4, however, have to see 3/4 of the
voltage, rather than
ARCPI
inverter. In the
S,,
main
DC link
by the main switches.
VA
_-
S1
Cn
W
1
Vga
í^z‹^.z A
4
VA
S4
W`
_"__.
Y
Fig. 7.2. Circuit
z‹
Note
that
,..
when
the
NPC
diagram of the
ARCPI NPC
9
Cr4
inverter.
structure is utilized for insulated'
DC/DC
conversion, soft
switching has been successfully achieved [144] [145] which promises wide application in
high voltage area. The operation of which resembles the phase-shifted resonant bridge [l03].
7.2.
Proposed Circuit Configuration
The proposed transformer connection True-PWM-Pole NPC
Fig. 7.3,
which
consists of the
commutation of the first switching
True-PWM-Pole; whereas
in
cell (S¡, S3)
and fonns
the second auxiliary branch (S,2, SM) assists the
commutation of the second switching cell
(S2, S4)
Provided that the NPC neutral potential
the
shown
NPC main inverter circuit and two auxiliary branches. The first
auxiliary branch (S32, S,3) assists the
the first
inverter circuit is
and forms the second True-PWM-Pole.
is stable,
and in particular, the coupling between
two poles can be neglected, the operation of the two True-PWM-Poles are then
independent from each other and each pole works as in the two level case.
actually
108
n
n
D.1|Dzo'
,
Sm
_ LW:
O
Dm:
‹^
ZS
Cl
im:
O N2
N10
A
E ze
Dai! Dal'
O
í
C2
ele
Ã
9:12 Dad'
Vd0/2
Sal
DSM
sad
Ni;
N2
.
ÃDM
'
Y
}z
ä›
V
.
¿
S4
ð-l
Dn2`
Í
Dszú
5:12
Cri
'-ll&'1g'›
A
D3
De
Lr'24
Í
Fig. 7.3.
_
A
51
The proposed True-PWM-Pole NPC
Cú
inverter circuit.
7 .3. Circuit Operation
According to the switching
first pole
is active,
state
of the main NPC inverter shown in Table
the second pole will be at rest (S2
ON,
S4 OFF
and
7.1,
when the
vc,,,=V,,,/2, vc,2=0).
Four
commutation processes can hence be distinguished:
Table 7.1. Switching State of the main NPC Inverter
Vâ«/2
0
-W2
(a) Positive
S.
Sz
Sz
S4
ON
ON
ON
OFF
OFF
OFF
OFF
OFF
ON
ON
OFF
load cturent, Dc¡+S2 to S,+S2 commutation;
(b) Positive load current, S¡+S2 to Dc,+S2
commutation;
(c)
Negative load current, D2+D, to S,+Dc2 commutation;
(d)
Negative load current, S3+Dc2 to D2+D¡ commutation.
For simplicity, only cormnutation
following. For
(a)
NPC
details for processes (c)
which the next assumptions
neutral potential
is
stable during
the commutation interval.
(b)
ON
are
made
and
(d) are detailed in the
first:
nomial operation. Load current
signal is released
constant during
.
Main switch tum-off and auxiliary switch tum-on happen at the same
tum-on
is
when
instant.
Main switch
the detected voltage from the voltage monitor installed for
109
.each
main switch declines
commutation
(c)
to zero. Auxiliary switch conduction duration covers the
whole
interval.
Transformer
ratio is set to ensure the pole voltage
swinging to the
rail
value during the
V
commutation, as discussed in Chapter 2.
Refer to the relevant theoretical wavefonns shown in Fig. 7.4 and the operation step
diagrams shown in Fig. 7.5 and Fig.
7.6, the
Process(c): Negative load current,
Step]
(tg-t 1): Circuit
steady
commutations proceed in the following
D2+D,
state.
steps.
to S3+Dc2comrnutation:
D2+D,' carries the load current. Output voltage
VA0=Vdc/2.
Step2
(t 1-tz):
Tum
on
S,,
and tum off
conduction of Da, and D,,”, magnetization of
kVdc/2
4
is
S¡ at
t,
simultaneously, which causes the
and current decreasing in D,. Voltage of
L,,3
reflected on N, setting-up a voltage source of Vdc(1-k)/2 forcing the resonance
followed.
Step3
.
is
(tz-t3):
charged while C,3
Step4
signal
is
D,
is
is
blocked
at
discharged.
(t3-t4): C,, is fully
tz
when im, rises to the load current level.
After which
Cfl
-
charged to Vdc/2
at
t3.
Dc, begins conduction.
And
S3 gating
released.
Step5
(t4-t5): L,,3 current
reaches load current at
t4,
after
which S3+Dc2 begins carrying
current.
Step 6
(t5-t6):
load current.
Sa,
output voltage
Current through/voltage across N, extinguish at
S3+Dc2 carries the
gating signal can be withdrawn. Circuit then reaches another steady
VA0=0.
Process(d): Negative load current, S3+Dc2 to
Step7
t5.
(t6-t7):
state.
full
The
D2+D, commutation:
Tum on Sa, and tum off S3 at tô simultaneously which causes conduction
of Da, and Dá”. Voltage of kVdc/2
is
therefore established
on N2 resulting in a voltage source
of Vdc(1-k)/2 forcing the resonance. Load current moves from S3+Dc2 to D2 charging
C,3
and
discharging CH.
Step8
(t7-tg): C,, gets fully
discharged at
tq
after
which current flowing
transfers immediately to D,. S, gating signal is then released.
in C,,
and Cg
110
Step9
D2+D,
(tg-t9):
Voltage across/current through
carries the full load current. S,3 gating signal
in the proposed circuit, the
from which instant
can then be withdrawn. Circuit arrives
main switches work with
voltage switching) and snubbed tum-off, while the
work with zero
ts,
at
V A0=Vdc/2.
the original steady state. Output voltage
To summarize,
out at
L,,3 dies
soft turn-on (zero
main diodes (freewheeling and clamping)
current turn-off and zero voltage turn-on. Unlike the case in the conventional
snubber where the snubbing capacitance
is
limited
by the snubber
loss,
the parallel
capacitance in the present case can be optimized for the switch turn-off loss. However, the
main diode
is characteristic
which
of snap-on
is
conventional snubber. The loss accrued in such process
similar to the system assisted with
dependent on the wiring inductance
is
and the diode forward recovery property.
In the meantime,
soft
all
the auxiliary devices including both switches and diodes
Moreover,
tum-off (zero current switching).
auxiliary devices, the
Upon
tum-on of these devices are
work with
despite the bridge configuration of the
actually snubbed
by the resonant inductor.
turn-on of an auxiliary switch, the opposite freewheeling diode carries no current and
its
reverse recovery contribution can be neglected. Transfonner excitation are reset
to zero after
each commutation and causes no magnetic accumulation. In particular, the extra
therefore
freedom in synthesizing the auxiliary voltage source for the resonance offered by the
transformer greatly simplifies the control.
Designing of the auxiliary branches has been discussed in Chapter 2.
Switching period: T-I/fc
A
Commutation process
Sa;
Commutation process
(c)
\
l
Sal
S3
V
51
I
z
yyyyyyyyyyyy
l
¡
(Vs:/il)
I
.
ls'/D'
'M3
Vw
__
hm
*-1
5
V-W
__
_
H
__________
N 7 __
5....
V-;....
ts
main and the
auxiliary switches
t7
t
1
P
Vèlloed
F/*W
Ê
'
iload
Igú
¿;._
W
¡
de/2
__
_
›
›
l
.
s
Fig. 7.4. Switching sequence of the
¡
¡
É
›l
(d)
tg
Vdc/2
Í
P
tg
and the relevant waveforms.
lll
I
I
Dz11Dz3 Sa:
ð_|
ZS
J”
Cl
íí
‹¿
E ze
o
N2?›
Dz2Dz14`Sz4
Dm
C
"VO
___...
2:
DM
‹A
z:‹›4
c
5:12
u
0
n
DâlDz3` Szs
__
30.1
Cl
0
‹¿
1: to-t,
Sz14
.
'í'
ZS
ZS<>-i
DM Dzzz`
Szz
u
u,
_
,
_
Dal Dai'
f
Cl
Li*/2
Í
5:13
z:‹›4
‹A
à fe €~
D113Dz11`
°
Ã
Szn
S14
D.«zDz..z'
Cz
___""°'“
Z3°`¡
ZS
23°-I
Das Dzz'
I
Í
Szz
.
v
A
SM
CM
1.
z:‹›1
f
Cr
3:12
ÍLH3
›
D°
'
Dsal
'
'
T›
1.124
Dâzz
v
A
L
O
z
<^
Deu
S1
Nz*›
Dz1zDz4`
Suõ
Dszó
ÃDM
ZS°~I
Dn' Szz
0
.
É
Dal Dal' sa!
zs
z:‹›4
A
O
__
O
N10
K
Sul
Dzzzvzc
szz
Nr.
ZS
Dm
0
23°-I
Daz'
i
5:12
0
Fig. 7.5. Operation step diagrams for
Usa]
vs*
Í|__¡›¡3
Nz
Dz.-14
commutation process
(c)
'
'
"
nc
'
Nz*
‹4Dm
step 6:
t,,-ts
Cn
_'_›
A
014
t,-t4
nm
EM ‹^
ZS
CM
.
D|
°
22°*
D1úDz1'
Cz
Vudl
1.114
‹ADzz
‹~
^
Dcz
Sa
Cl
*'›
A
'
1-v2^
v
. N,
Ã
V_“^"n
^`
D
Del
Dsal
NI..
I
im:
5111
vz./1
°“
V
DV
t,-tz
Dz3D1z1`
Cz
Cn
,S4
.
step 5:
1
DS:|2
0
N10
E
»
Da
11.114
¢¿
2:04
cl
___"*'°/2
z ~
Y
S4
V0.
0
Dz1DaJ'
Sa;
.
.
N 2'
O
Daá Dal'
'c
0
A
'
^À"2^
Dm
"VO
2:
"í›
A
Dcl
‹› Dm
step 4:
F'
.
Dz1zD114'
tz-t,
‹^
‹A
5111
Vad!
Cm
S4
DSa3
Nf.
Da3D‹1|'
U
0 Nz
N10
í
,
step 3:
Í
'
Lm
‹A um
o
Íuu
Nz*›
0
Cz
Dez
NZ.
N 10
Cn
S1
step 2:
1~2.
Dm
NI..
'
im:
Cz
vúaz
54
S1
A
Dz1zDz4'
1
^
‹À
Ã.,¬|
zz
¿k¿›
.
›
Dm:
1^
Sal
T
1
Dm
Sa:
(step 9: ts-t9)
Nz_'_›
DzúD111'
v¿
TP
0
N10
Ã
H
Y
Dcz
Dsal
,
T
VM
,
11.114
step
J'
A
NZ'
O
Daly
ii
¢^À"2^
Den
Vãzfl
Cl
.
Del
l
Dz1Dz1`
_ LM
I
Í1.ru
Sal
Dz13Da1`
l
Cr
51
0
N10
1
Dâzs
mó
V
A
L
54
°"
*-7
A
Cr:
.
ts-tá
D,+D2 to S,+DC2 commutation.
112
n
1
Dzn Dzú' Sa:
Ã
C.
Í
qNm
"*'°”
À
-
Dall
:El
Ã
C2
_V°°'2
Dsnl
‹¿
à za 1.
I
S32
'
~¿
'
`
.
É í
N|`o
D¡¡4D;¡2'
¡
SM
Z§°-I
Í
Â
Del
Sal
Diz DM'
1
Nz_'-'›
o
A
V
S1
¡,,,,
_
Ás'
-
°
‹¿
3,4
1
Dm
V
-TP
¿
S4
[X14
Usa!
Z:
c.
'
___
_
°
sa
3°-I
C1
____Vd°n
Dsnl
‹A
zz
DM
0
za 1.
Da2`
I
5a2
N2`
(d)
'
-se
-
D2
ÚL
VÀ
A
W
rn
Dsa2
step 8:
commutation process
A
E
U Ez
Dzzâ
É í
"lb
Cn:
_
Â
Del
Sal
D.¬z DM'
ZS
¡,,,,
Cn
'
-
Da'lDnl'
A
7
S1
1
É mí*
EH
2*
1
Dm:
0
Nzo
A
1+
í
‹¿
t,-t7
Fig. 7.6. Operation step diagrams for
a
7
>
9s
t2-t3
S3+DC2 to D,+D2 commutation.
Topologies for Multilevel Case (M>3)
'Zero voltage switching for multilevel diode
by
_V“°'*
°_|
Í
step 7:
7.4.
I
n
Dal Das' Szú
Cri
(M
>3) can be achieved
an auxiliary network based on either the whole multilevel leg or each two level
installing
switching cell of it.
7.4.1.
clamping inverter
`
Zero Voltage Switching on the Per-Leg Basis
Both True-PWM-Pole and
ARCP
methods are applicable for multilevel case. For the
True-PWM-Pole method, the auxiliary branch is established by the same multilevel
main
leg, as
assisted
by
shown
in Fig. 7.7,
S,,, Sa2, S,,3, S,,°, S,,2'
Transfonner
ratio
where the commutations of
and
S83'
S,, S2, S3, Sl”, S2”,
respectively and three
True-PWM-Poles
leg as the
and
S3” are
are formed.
should be set less than' 1/6 to ensure zero voltage switching.
In the case of ARCP method, the auxiliary branch can be established by the sub-circuit
of a
M+l
assisted
level leg, as
by
in Fig. 7.8.
S,,, S,2, S,3, Sal”, S,2”
Each main switching
as in the
shown
two
cell
and
level case.
In this approach,
its
and
The commutations of S,,
S,3°
S2, S3, S,', S2”,
ARCP
respectively and three
and
S3' are
poles are formed.
corresponding auxiliary switching cell work in the same
way
_
all
the poles share the
same resonant inductor and transformer.
However, resonant current always flows through three devices in
inner auxiliary Switches are indirectly clamped as the
main
series. In addition, all the
switches.
113
R
_
A
*rl
-BP:
OJJ*
Sal'
7
Ç
.
À
A
A
¡
‹A
S3
Sa]
A
À
‹^
sl.
A
saz
A
‹A
S2.
H A
Szú
‹4
S1'
A
H ¡
su
A
9.1
À
U
I
A
.
Fig. 7.7.
Al
xl
The
A
auxiliary switches block l/3 of the
M
(4
zz
1
í
=
___
T
transformer connection True-PWM-Pole four level diode clamping inverter leg.
:_"'
Fig. 7.8.
SI
Ã
ZS
ZX
à à Ã
2:
à
H
DC link voltage, same as that by the main switches.
A
Szú'
¿
Sal
°-l
lS1
^:fl‹›
az
Â
¿
‹^
‹¿
_
s,
'
SI.
7
zé
S”
~
Ã
H ‹^
sai'
°-l
Sfl
€^
°-ln
T
S3.
An ARCP four level diode clamping inverter leg. The auxiliary switches block
voltage, half of that
by the main switches.
1/6
of the
DC link
114
7.4.2.
Zero Voltage Switching on the Per-Cell Basis
Zero voltage switching of the diode clamping multilevel inverter can also be achieved
based on each two level switching
with True-PWM-Pole or
cell
approach, individual two level auxiliary branch
in Fig. 8. 11 for the case
ARCPI
methods. In this
for each switching cell, as
is installed
shown
of True-PWM-Pole and Fig. 8.12 for the case of ARCP.
In comparison with the previous approach, each pole has
its
own
resonant inductor.
However, resonant current flows through only one auxiliary switch, which avoids the problem
of indirect clamping in the auxiliary network.
7.5.
Experimentation
The experimental IGBT half bridge prototype,
two
sinusoidal modulating signal and
modulation, as discussed in Chapter
instead
is
parameters are given in Table 7.2:
Í
DMF
Dal
Cl
Sa]
Dzz
Dzzz'
5.14
3°*
Z*
z1
__V“'/2
1
ZS
DM
Í
05.4
N2'
_í
ÃO-l
Dflz'
Í
‹A
Saz
A
Du
Dsnl
o
N1`o
___'
_"`›
‹A
Sal
'
l|_¡»¡3
Dsaz
Fig. 7.9. Circuit diagram of the
D°
í
LY24
A
A í›
Cr
51
0 Nz
Daft Dal'
D2
Cr3
ilond
A
Cr,
'
t
àL
54
Lf
D,
O
cf
“›
io
W”
L
Cr4
3kW half bridge laboratory prototype.
Table 7.2. Prototype specifications and parameters
Parameters
circuit
neutral potential is not actively controlled
Dsafl
‹À
N iu
_V_**""1
Ã
Specifications
employs a
main
-
ZS
O
in Fig. 7.9,
and
on the inherent self-balancing mechanism. Specifications and
stabilized counting
_
shown
vertically shifted carriers for the
The
6.
as
P0=3.2kW, V,,,=720V, V°_,m,=l40V, I°,m,=22.8A
k=0.45, T=l53.6uS, C,=0.luF, L,=l5uH,
M=0.62
r
115
IGBT modules (SKM50GBl23D,l200V/SOA) are employed as the main and
auxiliary switches. Eight ultra-fast HFA30TA60C (600V/30A) diodes work as the auxiliary
diodes. Two storage capacitors C, and C2 each rated at 360V/3300uF form the center tap.
Four
Output second order
filter:
Lf=6.5mH,
Cf=12uF. For each main switch, a zero voltage
detecting circuit as discussed in Chapter 5
Under the given
The width of
9.4uS.
Minimum/Maximum
2.4uS
cell.
conditions, the
is
is installed.
maximum commutation
the auxiliary
switch gating signal
duration
is
set
is
at
calculated to be
12uS, and the
pulse widths are set at l4.4uS and 96uS respectively.
Dead time of
introduced between the gating signals for the two main switches in each switching
Gating signals for the main and auxiliary switches are created in
Appendix 7.1
lists
Fig. 7.10
and current
the
EPROM
27256M.
BASIC program.
shows the three
level output
after filtering. Fig. 7. l2(a)- (d)
of the
inverter. Fig. 7.11
shows the output voltage
show the typical four commutation processes.
¡
¡
'¡¡ VAO
-=
'V
“À
__-*__
___.íi._.._z
-_.__.._..___....--_--
100V/Div; 200uS/Div
Fig. 7.10.
The three
,~
level output
of the NPC
inverter.
Vo
Áefl~
100V/Div; 20A/Div; 5mS/Div
Fig. 7.1
1.
Output voltage/current
after filtering.
f
~
Vs:
,_
¡Dc!
l
T ¡ v. v `¬.-..¬---_-¬_...-..-¬__
100V/Div; SA/Div; l0uS/Div
(a) Positive load current
vsz
commutation
Dc, to S,
,
"ll
afll
i
À¡fl@-._
ãlll
¬
,,
V- '-›' _-¬.¬- _'-.v_..¬.-__"-¬._.._ .._.___.._.__
il.
_
,,
V
-._~;quqn.¿_-_.-_-pppçgç 2
:.pqv9n.-^ :_:p-9-:_-_'
_
l00V/Div; SA/Div; l0uS/Div
commutation
(b) Positive load current, S, to Dc,
VS3
EJune
Í
=
_.
J.
_
_
_
.
._
'
..
._
¬
_
_
q
l
100V/Div; SA/Div; 2uS/Div
(c)
Negative load current, S3 to D, commutation
117
V
t
ss
1
:
Dcl
I'
100V/Div; SA/Div; I0uS/Div
(d) Negative load current,
Fig. 7.12.
Fig. 7.13
load current
shows the
ikm,
=8A.
D, to S, commutation
-
Four typical commutation processes of the first resonant pole.
auxiliary switch voltage and resonant inductor current
waveforms
at
For switch to diode commutation, with a theoretical commutation
duration of 4.6uS and a resonant peak current of 17.5A, the experimental values are 4.luS
and l4.5A respectively. For diode
to switch commutation, with a theoretical
commutation
duration of 7 .3uS and a resonant peak cLu'rent of 32.5A, the experimental values are 7uS and
27A respectively.
Vszn
-O
'ms
100V/Div; 10A/Div; 20uS/Div
Fig. 7.13. Auxiliary switch voltage
and resonant inductor
current.
7
6.
Conclusions
The foregoing
analysis and experimentation justify the following conclusions:
The proposed scheme ensures zero voltage tum-on and
capacitive turn-off of the
main
switches, without causing any voltage/current spikes across these switches.
The proposed scheme ensures inductive turn-on and zero
current turn-off of the auxiliary
switches, without causing any voltage spike.
Main freewheeling diode works with
Oscillation
transfer
may
zero voltage turn-on, zero current tum-off.
occur during the diode forward recovery process due to the fast current
from the snubbing capacitors
to the diode
Characteristic curves presented in Chapter 2 regarding the
inductor peak current and resonant inductor
commutation duration, resonant
RMS current is verified.
Both transfonner connection True-PWM-Pole and
ARCPI schemes
multilevel diode clamping multilevel inverter, achieved either
the per-leg basis.
flows through
The
on the
per-cell circuit requires multiple magnetics,
are extensible to
per-cell basis or
its
on
resonant current
only one auxiliary device. In comparison, unique magnetics are used in the
per-leg circuit, however, the resonant current
flows through multiple auxiliary devices.
119
Appendix
U=
BASIC program for generating the gating signals in EPROM27256
7.1.
'DATA OUTPUT LINES COUNTER
OPEN "A:SPWMNPC.DAT" FOR OUTPUT AS #1
990 PRINT #1, ":10"; 'FIRST DATA OUTPUT LINE FORMAT
1000 PRINT #1, "00O000"; 'FIRST DATA OUTPUT LINE FORMAT
1010 FORI = 0 TO 127: 'SELECT SWITCHING CYCLE
1020 RA1= 0: RA4 = 0
1030 FOR K = 128 * I TO 127 + 128 * I: 'SELECT ADDRESSES
1040IFO<=K-I* 128ANDK-I* 128<=64THENVA=K-I* 128+64ELSEVA= 128-(K-I*
+ 64'TRINGLE VB GENERATORIOSO VB = -64 + VA 'TRINGLE WAVE VA GENERATOR
1050 VB = VA - 64
970
980
1
'
1060 PI=3.14159
1070 VC = 64 + 40
A
*
SIN(2
* PI *
K/
16384)
'MODULATING WAVE GENERATOR
128)
›
1080IFVC>64ANDVA<=VCANDVC<=VA+2AND64<=K-I*128ANDK-I*128<=127
THENMMP=0ELSEMMP=MMP+l
1090 IF VC > 64 AND <= MMP AND MMP <= 12 THEN MINP = ELSE MINP = 0
1100 IF VC>VA ANDO<=IANDI<= 63 AND MMP>= THEN SI1 = ELSE SI1 =0
'
.
1
1110 SJ1=SI1
1
1
ORMINP
1
1l20SJ3=1-SJ1
<=MMPAND MMP<=2AND SJ1 = AND VC>64 THENDA3 = ELSE DA3 =0
<= MMP AND MMP <= 10 AND SJ1= AND VC > 64 THEN SA3 =1 ELSE SA3 = 0
1150IFSJl =0ANDO<=IANDI<=63ANDVC>64ANDO<=K-I* 128ANDK-I* l28<=63 THEN
1130 IF
1140 IF
1
1
1
1
1
RA1=RA1+1ELSERA1=RAl
1160 IF <=RA1 AND RA1 <=2THEN DA1 = ELSEDA1 =0
1170 IF <=RA1 AND RAI <= 10 THEN SA1 = ELSE SA1 =0
1
1
1
1
11s011=vE<=vcANDvc<=vB+2AND0<=1<-1*12sAND1<-1*12s<=63 THENMMN=0ELSE
MMN=MMN+1
1190
1200
1210
1220
1230
vc < 64 AND <= MMN AND MMN <= 12 THEN M1NN = ELSE MINN = 0
vc < VB AND MMN >= THEN S14 = ELSE S14 = 0
SJ4 = S14 011 M1NN
IF
IF
1
1
1
S12
IF
1
12401F
1
1
=1- SJ4
<= MMN AND MMN <= 2 AND SJ4 = 1 AND vc < 64 THEN DA2 = 1 ELSE DA2 = 0
<= MMN AND MMN <= 10 AND SJ4 = 1 AND vc < 64 THEN SA2 = 1 ELSE SA2 = 0
12s01F S14 = 0 AND vc < 64 AND 64 <= K -1*12s
RA4=0
1260 IF
1270 IF
1280
1
1
AND K -1*
<= RA4 AND RA4 <= 2 THEN DA4 = 1 ELSE DA4 = 0
<= RA4 AND RA4 <= 10 THEN SA4 = 1 ELSE SA4 = 0
128
<=127 THENRA4 = RA4 +1 ELSE
-
Sl=SJ1-DA3:S2=SJ2-DA4:S3=SJ3 -DAI: S4=SJ4-DA2 'MAIN SWITCH COMMAND
1290A=SA4*2^7+SA3*2^6+SA2*2^5+SA1*2^4+S4*2^3+S3*2^2+S2*2^1+S1*2
^0
1300
1310
1330
1340
1350
1360
1370
'
PRINT #1, I; S1; SA1;
IFK=U*16THEN
U=U+
S2;
SA2; S3; SA3; S4; SA4
1
IF
TOTAL < 255.5 THEN
IF TOTAL < 15.5 THEN
PRINT #1,
ELSE
"00";
HEX$(TOTAL)
120
1380
PRINT #1, "0"; HEx$(TOTAL)
END IP
1390
1400
ELSE
1410
PRINT #1, HEx$(TOTAL)
1420
END IF
1430 TOTAL = 0
1440 PRINT #1, "z"; HEx$(K / (U - 1));
IP K < 16 THEN
1450
1460
PRINT #1, "000";
1470
ELSE
1480
IF K < 256 THEN
PRINT #1, "00";
1490
ELSE
1500
1510
IP K < 4096 THEN
PRINT #1, "0";
1520
1530
END IP
END IP
1540
END IF
1550
1560 PRn×IT #1, HEx$(K); "00";
1570 END IE
1580 TOTAL = TOTAL + A
1590 II=A< 15.5 THEN
1600 PRINT #1, "0"; HEx$(A);
1610 ELSE
1620 PRINT #1, HEx$(A);
1630 END IE
1640 NEXT K
1650 NEXT I
1660 IF TOTAL < 256 THEN
1670 PRINT #1, "0"; HEx$(TOTAL);
1680 ELSE
1690 PRINT #1, HEx$(TOTAL);
1700 END IE
1710 CLOSE
1720 END
A
Chapter 8.
A New Diode Clamping Multilevel Inverter
121
Abstract: This Chapter proposes a new diode clamping multilevel inverter, which rids of
the series association of the clamping diodes in the conventional multilevel inverter.
new
Operation fimdamentals as well as the snubbing methods for the
inverter are discussed.
Experimental results from a 3kW half bridge prototype are also presented.
8.1. Series
Association of Diodes in the Conventional Inverter
In a conventional diode clamping multilevel inverter [35][36], voltage rating of each
clamping diode
is
dependent on
position in the inverter. For each leg, one can
its
diodes each sees reverse voltage stress
Vdioâe
=
where
M
M-
of:
-K
Ífvdc
is
l
the
_
number of inverter levels, k goes from
C1
D¡
~Q
D3
D2
‹^
A
4
O
D5
__;
A
D4
‹^
4
S2'
A
...|
l
M-2, Vdc
to
D5¡
|
Dsz
S.
|
C4
í'
A
ø-|
DC link voltage.
S
›
l
S.
.|
'sí
III
›
.Q
v
.._
,
Us
_
`
>
C7
52
:_
1__.
_
'
[__
MA
M Q..
re
-v
[ff
'
Dsz'
Vm
‹¿
Vw'
3
IVD1
|
VD3
VD2
'
.-1.
'
'
VD4
V
S4'
^
°"l
‹A
054'
.
Vpó
vD5
E,
I
Fig. 8.1. Conventional diode
inverter leg,
is
I
_l_
Dó
the
~fi
A
_
S]
C3
(3-1)
.
Q
find two
clamping five level
where clamping diode has
high voltage.
to block
Fig. 8.2.
Clamping diode voltage
stress in
association with the switching state in the
conventional inverter.
122
For a five level case, as shown in Fig.
8.1,
D, and D6 see Vdc/4, D3 and D4 see
and D5 see 3Vdc/4, whereas each main device see only Vdc/4. Fig. 8.2 shows
voltage
is
related to the switching state.
While in a practical
hence difficult to have
situation the
fast
2V,,c/4,
D2
how the blocking
'
.
main device voltage
rating is always fully utilized,
it is
tum-off diode in the market with multiple voltage rating and yet
comparable performance. In high voltage P-N junction designing, larger breakdown voltage
is
always accompanied by higher on-state loss and longer turn-off transience.
The common
The five
solution to this problem
level case is
in series, is
shown
put appropriate number of diodes in series.
Diodes in
in Fig. 8.3.
by no means an optimal
is to
solution.
series,
Unequal
though
less problematic
than
GTOs
or dynamic voltage sharing can
static
happen, due to the diversity of switching characteristics and stray parameters of the diodes in
series.
Measures to prevent the potential over-voltage problem by providing large snubber
capacitor and high power resistor network lead to an expensive and voluminous system.
8.2.
Operation of the New Inverter
.
_
A new diode clamping multilevel inverter has been proposed. For the five level case, as
shown in Fig.
8.4,
a total of 8 switches and 12 diodes are used, the same amount as that in the
conventional inverter. The pyramid structure
is
extensible to infinite
otherwise practically limited.
~A
DI
C2
o
C
__..3
D1
A D2 4
S3
A D3 A
S4
Dl]
A
D3
D9
^
D4
^ Dn
.
D5
C4
.
S1
C-
A
DIO
D5 A
°"|
‹e-
ir
‹À
D*
1
Ds
5
A
‹A Dzz
‹^
C2
D2
0
D3
C3
D4
054
S2
°.'|
Dl
_
‹^
53
s
°›
D52
S1'
S4'
Fig. 8.3. Conventional diode
number of levels unless
Du'
D5
y
.
Dsfl
.
C4
S2
A
A
Á
°-l
inverter with diodes in series.
Fig. 8.4.
‹A
‹,
D1
A
D3
A
A
‹A
D9
A
A
A
Dio
‹A
À
D6 A
‹›-1
€A Usa'
clamping multilevel
‹~
DS'
052
DS3
DS4
A
psy
11,2'
^
sz'
Dza'
54'
€A Dn'
Proposed new diode clamping multilevel
inverter.
8.2.1.
123
Switching Cells of the New Inverter
The new
inverter can
be decomposed
into two-level switching cells
which
constitute
basic operation units. For the ifive level leg, one can define (5-1) switching cells as
Fig. 8.5 (a), (b), (c)
In the
same
and
(d).
In cell
sense, the output
or the reverse in cell
(c),
moves from
and from -Vdb/2
S'
C1
the leg output
(a),
D”
_
D
Vdc/4 to 0 or the reverse in cell (b),
o
D
D
4
A
›
D-‹
‹4
D5
A
z
54
{›
DS4
~
A
A
D;
D2
o
D3
C3
‹
1
1
'
'
D
H
S4'
(G)
Fig. 8.5.
A
Dsli
DS3'
DS4'
S4
sl
C1
Ds2
DS 1
'
C4
1^
.
Dsl
0*
C2
Ds4
(b)
S1
Cl
Ds3
Ds2'
D6 ^
C4
(a)
G'
‹
1
1
-
__C_3
.gzäpäzà
Dx2
,
¡
O
ri!!!
D
C4
C2
.A
.¿
C3
D1
=
Dn
SL*
'*
^
from 0
to -Vdc/4 or the reverse in cell (d).
C1
|
D¡
C2
D2
o
D3
DS4
'A
.
C3
.
4
A
A
D4
D9
I
DS]
.
Ds]
‹A
Ds2
‹¿
DS3
A
€D
‹
q
¡
sl
'
C4
‹›
954
D3 A
D5
Ds2
in
moves from Vdc/2 to Vdc/4 or the reverse.
a.
C2
shown
its
v
DBZ'
\
Ds3'
DS4'
S4'
Ds-1'
(d)
The four switching cells of the new diode clamping multilevel
inverter.
to -Vdc/2
124
To
further illustrate
how each switching
cell
works as a two
and freewheeling paths for the up/down arms of
cell(b) are
level inverter, the
shown
in Fig. 8.6(a)
forward
and
(b)
Current paths for the other cells can be analogously found.
C1
D¡
D3
o
‹›
52
‹-
~
D2
C2
S1
D8
A
-
I
D4
C3
A
D9
A
.¡
.
I
D5
A
S3
‹A
Q
(a)
21A
Ds]
‹A
DS4
¢^ Ds:
DS4
C4
z
D8
A
A
_¿
D9
¿
4
°fi
~
.
É
À
›-A ‹
A
.n
D5 A
A
DSI
A
~
ll
‹^ Ds:
ST*
,
forward/freewheeling paths for the up arm
‹^
(b) forward/freewheeling paths for the
down
arm
2
Fig. 8.6.
A
i
I
Wi.
Dsz'
0:'
D2
D4
--C3
Dal'
Dsl
‹.
D3
0
‹A
»-
,
A
S4
i
cz
DS4
1^
A
DIO
D6 A
C4
Diz
ves
'A
S
Cl
|
D3
D7
^
DS
Forward and freewheeling paths for cell (b).
The above decomposition presumes
that the output dv/dt is constrained to
a single
device dv/dt, which has been regarded as one of the most notable attribute of the multilevel
inverter over the plain series of devices.
must only involve one switching
cell.
To work within this constraint, each switching
Simultaneous switching of more than one switching
runs no difference with direct series 'association and
8.2.2.
cell (a) for
example. In this
work altematively connecting
switches of the leg,
forbidden in operation.
S2”, S3'
and
shown in Fig.
cell, S2, S3
and S4 are always ON, while
the output to Vdc/2 or Vdc/4 respectively.
S4” are
and each blocks zero voltage
the state of S1”, as
S1
and
S,°
The remaining
always OFF. Thus D2, D2 and D,2 must be in clamping
ideally.
Moreover, D,, D2 and Dn each must always follows
8.5(a).
In the same sense, for cell
state
is
cell
Switching State of the Diode Network
Take
state
action
(b),
D, and D9 follow the
of S2, as shown in Fig. 8.5(b); for
cell (c),
state
D, follows the
of
state
S2”
while D2 follows the
of S3”, D4 and D8 follow
the state of S3, as
shown
Table
shown in Fig.
in Fig. 8.5(d).
8.1,
which
is
The switching
8.1.
0:
Output
S,
‹
'
S,
8.7.
Device blocks zero voltage
‹
Device blocks Vdc/4 voltage
S2'
S2
S3'
S,
S4'
S.,
Diode state
Dl: D7: Dil
level
-¬
shown in Fig.
Switching State of the Diode Network verses the switch state
1:
state
Dm and Dn follow the state of S4, as
(d), D6,
of the diode network can thus be summanzed in
state
further graphically
Table
Switch
and in cell
8.5(c);
Vdc/2
1
O
Vdc/4
0
li
0
0
l
'Vdc/4
0
1
'Vdc/2
O
l
D2
D3:
V0
l
D9
D4›
0
l
D8
D5
l
O
1
O
l
D
1
il
lvl
017,0
0.170
0
_
D6: DI0›
l
0
l
l
0
P1!
A
.
VAO
Vac
P
,_|-J
|
.i
im
S2'
rn B!-
U
muzmm
;
YYY
àuw-
I
m bz
|
lT
vi àz
-__
|ñVsi'/Di/D7/ou
I*
VVS2'/D3/09
'
Vss'/Ds
'
I
li*
Vs4/Dó/mo/D12
Vs:/D4/Ds
Vsz/D2
I
,
_
V
U
Fig. 8.7. Illustration
.
VVV
of the switching
I
_
7
V5¡'
state in the
new
YVVVVY
_
_
diode clamping multilevel
inverter in relation to the output voltage level.
126
8.2.3.
Switch and Diode Clamping Mechanism
Refer back to Fig. 8.5
while
S,' in series
with D2,
Further, D,, in series with
(a).
D,,
and D,2
D2 and
clamped by Ds, and D,2, while D,
Suppose that when
D2,
Obviously, S,
S2”, S3'
is
clamped by
is directly
S,,”
clamped by D,
is directly
clamped by
D,, is
and
'
D,,, D,2, DS3
D,,, D,2
DS3;
turn-off,
DS., after its
tum-off.
D, in
are all
OFF, and each of them blocks Vdc/4 voltage,
mechanism can be witnessed with
are all clamped.
clamped. In
cell (c), S3”,
clamped while
clamped.
Among which
D3 and
cell (b),
S3, D,,,
D4 are
all
clamped.
clamped. In
for the proposed
Among
clamped
to
are indirectly clamped.
S2”, D3,
D9 as well as
new inverter,
them, the 8
lateral
Among which D,,, D,
and
cell (d), S4'
Among which S,,”, D6 are directly clamped while
clamping diodes.
where
all
S2,
D2
D2, D3 are directly clamped while S2”, D,, S2 are _indirectly
S3”, S3, D,, are indirectly
As a result,
is
clamped by D,,.
Among which S,, D, are directly clamped while S,”, D,, D,,
Similar
with D2
series
D,2 each will then block zero voltage. Then, S, and S,°, D,, D2, D,, are
D,,,
Vdc/4.
S,,, D,,,,
S,,,
D6,
are directly
D,,,,
D,2 are
all
D,2 are indirectly clamped.
not only the switches are clamped, so are the
components
( S,, S4”,
D6) are directly clamped, the remaining devices, however, are
D,, D2, D3,
all indirectly
D,,,
D3, and
clamped.
Over-Voltage from Indirect Clamping
8.2.4.
Considering the commutation process from
(a).
and
and
it°s
after
After the turn-off of
S,”, the
shown
D2
to D,,, DS3, D,2, Ds, in cell
demagnetization of the parasitic inductance LS in the
clamping path causes over-charging of S,°
S4” (stray capacitances), as
S,”, D,2, D3,
(stray capacitance)
in Fig. 8.8.
and discharging of S2”, S3” and
Such over-charging and discharging will be
maintained because the discharging/charging paths are blocked by D2,
Consequently,
and D2,
D,,,
S,°
D,,
and
D,2.
blocks higher than Vdc/4 while S2”, S3”, S4” together block less than 3V,,2/4
D,2 together sees the voltage difference between VS,» and Vdc/4. In the meanwhile,
D,, sees Vdc/4 plus VD2 plus VD8, D, sees Vdc/4 plus VD2, while D, sees Vdc/4.
The
S2, S3'
and
Due
indirect
S3,
clamping and the subsequent over-voltage problem holds also for
and S,, together with their relevant diodes in cell(b),
to the fact that the stray capacitance
cell(c)
and
S2”
and
cell(d).
of the neighboring outer switch experiences
once more discharging, the neighboring outer device (switch and
its
relevant diodes) always
blocks less voltage while the inner device always blocks more voltage. The innermost device,
of course,
is
always exposed to the highest voltage
stress.
127
Over-voltage problem arising from the indirect clamping exists with any diode clamping
multilevel inverter. Measures such as refined construction and appropriate snubbing are
believed to be helpful in mitigating this problem. Moreover,
clamping paths are made bi-directional by
anti-paralleling to
can be eliminated
it
if the
each clamping diode a small-
rating switch.
Cl
+
1,
S.
D1
À
51.4
Dzi
52
Dsz
°'|
cz
D2
Q
9› 5
C3
D4
D1
.
>J>b-I
Í
,_ __
D5 A
:I
C4
.›
.F5
P
:Há
D9
r¡;`¬
A
‹4¬
q" 52'
‹›¬
zz 5
»«
S4
Fig. 8.8. Illustration
8.3.
of the over-voltage across
E
S,?,
.
¡ S3.
‹-i DS4,
D, and D,, due to demagnetization of Ls.
Snubbing/Soft Switching of the New Inverter
The
true attractiveness
installation
where
designing plays a
inverter
GTOs
role.
are
of the multilevel inverter consists in the expanded capacity of an
most
Hence snubber
likely the choice as the switching element.
However, snubbing techniques
(M>3) have not beencovered
until the
for the diode
most recent
clamping multilevel
in the literature, probably
due to
the underlying difficulty in arranging efficient turn-on snubbers for the inner switching cells
with bi-directional busses. Non-polarized turn-on snubbers are especially inefficient.
When GTOS
the snubbing
are not the choice of device, the clamping
scheme shown
scheme shown
in Fig. 8.10 shall apply. In Fig. 8.10, instead
limiting di/dt over the full load range, saturable reactors are used
the right
moment to limit the diode reverse recovery overshoot.
in Fig. 8.9
of
and
linear reactors
which go out of saturation at
V
128
F
É
i
‹~
Fi
z
'*='=¡~§<~
‹›
_" gl
‹‹›-lp
|ü,‹
-
~
"
__
Fig. 8.9.
»
LE..
'
Clamping scheme
for the
1.
_'
‹›
Í"
new diode clamping
new
shown
inverter, as
in Fig. 7.7
switching
and Fig.
in Fig. 8.11
A
~
-
~
-
4:-
‹~
1.
~
-Dl
.
*Q
Fig. 8.10.
True-PWM-Pole and ARCPI
shown
‹›-|
vê
~
Snubbing scheme for the new diode
clamping multilevel
multilevel inverter, extensible to any level.
In addition, both
this
=
__
‹.
‹.
*A
inverter, extensible to
soft switching
any
level
methods are applicable to
and Fig. 8.12. In comparison with the arrangements
7.8, the auxiliary
branches are installed based on each individual
7
cell.
__i
1 ›
A__
A
l L
Aí P Z
A
A
A
A
A
›
inililninlnnrlnilni
ÉÉHHÉH
A
P
Í
.L
L
'HHHHHH
›
¡¡¡¿
t
Fig. 8.11.
AAA
True-PWM-Pole ñve
each switching
cell.
‹¿_ T
°_' ‹¿`
°_¡
_
P
A
level diode
.
I
¿_
è
L
€A
L
L
¿_
4.
‹›_|
°-I-I»
clamping multilevel
Main circuitry ZVS
e
i.
fl
.I
.
inverter. Auxiliary
switching, auxiliary circuitry
branch
is
arranged for
ZCS switching.
129
4?
‹f<§--
`_'*-_;¡_
_€_
‹¿
L
.zgg
Q.
A
-
mÉ
°*
_2F,'-.
‹¿
ARCPI five level diode clamping multilevel inverter. Auxiliary branch is arranged for
each switching
-«nz»~
1
.
Í-
1
IG*
1
Fig. 8.12.
-
cell.
Main circuitry ZVS
switching, auxiliary circuitry
ZCS switching.
8.4,¿Experimentation
A scaled half bridge prototype has been built for verification of the new inverter. Four
120V DC power sources each in series with a 10mH inductor establish the four separate DC
supplies for the DC link. A 8mH inductor in series with a l2Q resistor are comiected at the
shown in Fig.
vv
output, as
5.
and-'the 7th
in
harmonic
is
Fundamental frequency modulation scheme eliminating the 5th
8.13.
implemented. The
BASIC program
for generating the gating signals
EPROM 27256 is listed in Appendix 8.1. Experimental results are shown in Fig. 8.14.
'
P
5¡..¡
Cl
sz°-l‹^
¡ó|+iazDl55
C2
O
D7
.a1+|s
'd3+'d4m
_
C3
D2
__
_"~
D 4
D5
id5+id6
Dó ^
Q
D8
s3.›4
4
DH
¿ 94
S4
¡au+¡‹u
D9
DS z
Ds;
A
D54
30114
a
.
S¡o¬|
¡ó9+¡‹1|o
Dsl
DH,
.¡l›
I
F3
‹A Ds2'
Á
DIO
s3'°'¡
C4
s4'
'
O
‹^ D
5 3'
H ‹A
DS4'
N
Fig. 8.13. Experimental set-up of the proposed diode clamping inverter.
C1=C2=C3=C4=3300uF, D1-D12: HFA30TA60C,
Sl-S4':
SKM50GBl23D.
j~¬¿`Í'~¬
l
Oifiiffi
f
f
7'f_1*I*í
iao
100V/Div; 20A/Div; 4mS/Div
Fig. 8. l4(a).
Output voltage and load current waveforms.
Vao
M
¡ô1+â‹12
í
100V/Div; 20A/Div; 4mS/Div
Fig. 8. l4(b).
Sum of Dl and D2 currents in relation to the output voltage.
Vao
P'
1! id
+id
Í'
100V/Div; 20A/Div; 4mS/Div
Fig. 8. l4(c).
Sum of D3 and D4 currents in relation to the output voltage.
Y
Vac
100V/Div; 20A/Div; 4mS/Div
Fig. 8. l4(d).
Sum of D5 and D6 currents in relation to the output voltage.
Vao
v
id7+id
-‹.
l00V/Div; 20A/Div; 4mS/Div
Fig. 8.14(e).
Sum of D7 and D8 currents in relation to the output voltage.
'Vao
V
id9 idl0
100V/Div; 20A/Div; 4mS/Div
Fig. 8.l4(f).
Sum of D9 and Dl0 currents in relation to the output voltage.
Vao
`
i‹111+¡ 12
100V/Div; l0A/Div; 4mS/Div
Fig. 8.l4(g).
Sum of Dll
and DI2 currents
Vao
in relation to the output voltage
.
Vs4
100V/Div; 4mS/Div
Fig. 8.l4(h).
S4 blocking voltage
in relation to the output voltage.
Vao
Vs3
l00V/Div; 4mS/Div
Fig. 8.l4(i).
S3 blocking voltage
in relation to the output voltage.
-É
Vao
Vs2
`
l00V/Div; 4mS/Div
Fig. 8.l4(j).
g
S2 blocking voltage
in relation to the output voltage
Vao
_
Í
r
'Í
Vsl
`
"Í
I
I
L.-Id
l00V/Div; 4mS/Div
Fig. 8. l4(k). Sl blocking voltage in relation to the output voltage
Vpa
7"'
I
_,
f
___
_.___
_
_
l00V/Div; 4mS/Div
Fig. 8.l4(l).
Up-ar1n(Sl+S2+S3+S4) blocking voltage.
134
8
5.
Conclusions
Due to the multiple blocking voltages, series
associations of clamping diodes are needed in
the conventional diode clamping multilevel inverter,
voltage sharing problem
among
which
the diodes in series. Large
results in static
and dynamic
RC network dealing with this
problem leading to voluminous and expensive system.
The proposed new diode clamping
multilevel inverter
is
structured with built-in clamping
components in the new
for all the
clamping diodes in the clamping network. Thus
circuit are
clamped. The problem of series association of clamping diodes with the
conventional diode clamping multilevel inverter structure
is
all
solved.
Over-voltage across the inner devices as a result of indirect clamping
the conventional inverter and the
new
inverter. Current
'
is
inherent with both
loop inductances play the key role
in exciting the problem. Reasonable efforts in layout designing, device selecting (low
internal inductance) as well as snubber positioning are helpful in mitigating the problem.
Appendix
BASIC program for generating the gating signals in EPROM 27256M
8.1.
1120 U = 1 'DATA OUTPUT LINES COUNTER
1130 OPEN "A:MULTD.DAT" FOR OUTPUT AS #1
1 140 PRINT #1, ": 10";
'FIRST DATA OUTPUT LINE FORMAT
1150 PRINT #1, "000000"; 'FIRST DATA OUTPUT LINE FORMAT
1160 FORK = 0 TO 16383
1170 IF K <= 5498 ORK>= 10883 AND K <=16383 THEN S11 = 1 ELSE S11= 0
1180 IF K>= 5500 AND K <= 10881 THEN S1=1 ELSE S1= 0
1.190 IF K <= 4340 OR K >= 12041 AND K <=16383 THEN S22 = 1 ELSE S22 = 0
1200 IF K >= 4342 AND K <= 12039 THEN S2 = 1 ELSE S2 = 0
1210 IF K <= 3847 OR K >= 12534 AND K <=16383 THEN S33 = 1 ELSE S33 = 0
1220 IF K >= 3849 AND K <= 12532 THEN S3 = 1 ELSE S3 = 0
1230 IF K <= 2689 OR K >= 13692 AND K <= 16384 THEN S44 = 1 ELSE S44 = 0
1240 IF K >= 2691 AND K <= 13690 THEN S4 = 1 ELSE S4 = 0
135
4
1250A=S22*2^7+S11*2^6+S4*2^5+S3*2^4+S44*2^3+S33*2^2+S2*2^1+S1*2^
O
'
PRINT #1,
1260
1270
1280
1290
1300
1320
¢›
133.0
S1; S11; S2; S22; S3; S33; S4; S44; K;
16 THEN
IFK=U*
U=U+
1
IF
TOTAL < 255.5 THEN
IF TOTAL < 15.5 THEN
PRINT #1,
ELSE
PRINT #1,
"00";
"0";
HEX$(TOTAL)
HEX$(TOTAL)
1350
END IF
1360
ELSE
1370
PRINT #1, HEX$(TOTAL)
1390
END IF
1400 TOTAL = 0
1420 PRINT #1, ":"; HEX$(K / (U - 1));
1430
IF K < 16 THEN
1440
PRINT #1, "000";
1450
ELSE
1460
IF K < 256 THEN
1470
PRINT #1, "00";
1480
ELSE
1490
IF K < 4096 THEN
PRINT #1, "0";
1500
1510
END IF
1520
END IF
1530
END IF
1540 PRINT #1, HEX$(K); "00";
1550 END IF
1560 TOTAL = TOTAL + A
1570 IF A < 15.5 THEN
1580 PRINT #1, "0"; HEX$(A);
1590 ELSE
1600 PRINT #1, I-IEX$(A);
1610 END IF
1620 NEXT K
1630 IF TOTAL < 256 THEN
1640 PRINT #1, "0"; HEX$(TOTAL);
1650 ELSE
1660 PRINT #1, HEX$(TOTAL);
1670 END IF
1680 CLOSE
1690 END
O
136
A
Chapter
This thesis
is
General Conclusions
9.
dedicated to the soft switching techniques of the multilevel inverters.
Included are also the background treatments as regards the main circuits.
Chapter 1 of
this thesis deals
with the ftmdamentals of the multilevel inverters. The
existing approaches for implementing high voltage high
power
inverters utilizing device
association or cell association are inspected first. While series association of devices offers
advantage in terms of redundancy, the output waveform and dv/dt are not favored from the
multiple devices. Converterpassociation, on the other hand, necessitates insulation either
the
AC
side or the
evolved from
DC
side
cell association,
The diode clamping
clamping diodes
(NPC)
inverter
series
which
which means additional magnetics. The multilevel inverters
however, generate multi-step outputs without heavy magnetics.
multilevel inverter suffers from indirect clamping, potential drift,
and snubbing problems etc; Except for the Neutral-Point-Clamped
is free
from the
last three
problems, practical application can hardly be
realized before relevant solutions are verified. Theoretically, the inverter is relieved
potential drift
on
problem when pure reactive power
The capacitor clamping
inverter is
is
from the
transferred.
exempt from the above problems. However other
shortcomings arise such as the parasitic inductances resulted from the clamping capacitors, as
well as the heat capacity required for these capacitors.
It
seems more applicable than the diode
clamping inverter in the high level case especially when active power transfer is involved.
This chapter also reviews the snubber schemes reported for the
which snubbers
for two-level inverter are compared.
such objectionable problems as snubber
as the adverse effects
NPC
Before
The use of dissipative snubber leads
loss, voltage/current spikes, series reactor loss as
to
well
from the snubbing diodes. These problems become more pronounced for
multilevel inverters. For regenerative snubber, even though the snubber loss
expected increase in operating frequency
circuitry,
inverter.
is
is
recovered, the
limited by the complexity of the recovery
while the other problems remain.
Chapter 2 assesses the reported two-level inverter
proposes the transformer connection True-PWM-Pole
Resonant-DC-Link-Inverter (ACRLI)
is
soft switching techniques
circuit.
and
While the Actively-Clamped
not regarded suitable for power level beyond
300kW
because of the cost, size and cooling issues of the resonant inductor, the Auxiliary-ResonantCommutated-Pole-Inverter (ARCPI) suffers from the measuring and controlling difficulties to
guarantee the zero voltage switching especially
when the DC
137
center tap potential drift
is
taken
into account.
The transformer comiection True-PWM-Pole
circuit guarantees zero voltage switching
of the main device without any of the problems associated with the conventional snubber and
without any additional measuring or controlling. In the meanwhile, zero current switching of
the auxiliary device
is
simultaneously attained without the affliction of voltage spike due to
the bridge configuration,
baby snubber
is
which is a significant advantage over the regenerative snubber where
always required for the recovery chopper in hard switching. Depending on the
designing, the auxiliary device can be rated at about 1/4 of the
loss
due to the resonance transition
is
main
device.
The duty cycle
comparable to that of the conventional snubbed
inverter.
The transformer comection True-PWM-Pole circuit is verified by a 5kW prototype.
Besides transformer connection, auto-transformer connection and capacitor connection
True-PWM-Poles
.W
.._,.,
are also discussed.
halved, the freewheeling current
Even though the auxiliary device
current stress
flow during the non-comrnutation interval
is
further
evolved from the
,-'ya
magnetizing current renders the normal auto-transformer connection hardly applicable before
practical
measures are found.
.
The freewheeling current problem
family,
which
is
verified
by a
is
solved in the
5kW prototype. A
modified auto-transformer connection
simple snubbing
is
needed for the
series
diode to suppress the voltage spike. The variations of this family allow for further reduction in
the auto-transformer voltage/current rating or the resonant inductor current rating, which are
H
also tested in the laboratory.
The capacitor connection circuit, on the other hand, eliminates the magnetics
of the
fairly
at the price
augmented resonant circuit stress.
In Chapter 3, the clamping voltage stability in the three level capacitor clamping
inverter is explored.
the inverter load
is
Under sub-harmonic modulation,
the clamping voltage
The time constant of which
dependent on the load properties, modulation index, clarnping capacitance
When
etc.
asymmetries are taken into account, typically gating and switching mismatches,
the clamping voltage
result
stable as far as
not pure-reactive, due to the inherent feedback mechanism. The clamping
voltage response exhibits typical one-order system characteristics.
is
is
is
balanced at a
new
operation point other than the nominal value, as a
of the joint effects of the self balancing
ability
and the asymmetry. In addition, dead
138
time
is
to the
not expected to cause any clamping voltage
two switching
drift,
because of its symmetrical influence
cells during the local switching cycle.
With sub-harmonic modulation,
active control over the clarnping voltage
necessary can be realized by vertically shifting
oneof the
triangle carriers according to the
Clamping voltage
deviation direction and the load current direction.
where
adjusted
is
on the
switching cycle basis.
The
self-balancing ability
is
proved in a half-bridge three level prototype system.
Chapter 4 introduces a True-PWM-Pole three
installing the transfonner connection
voltage switching for
all
the
True-PWM-Pole
level capacitor
to
clamping
inverter.
each of the two switching
main devices and zero current switching .for
all
cells,
By
zero
the auxiliary
devices are secured, with the same performance as that in the two level inverter.
In particular, the proposed
True-PWM-Pole arrangement
further guarantees the stiffness of the
for the outer switching cell
clamping voltage due to the damped second order
charging/discharging paths established by the auxiliary circuitry.
auto-transformer connection
True-PWM-Pole
is
because the freewheeling current path in this case
now
is
Most positively,
the normal
applicable to the outer switching cell
blocked by the clamping capacitor.
The transformer connection True-PWM-Pole technique along with the AuxiliaryResonant-Commutated-Pole-Inverter (ARCPI) both are extensible to the capacitor clarnping
multilevel inverter (M>3).
Two
general zero voltage switching topologies for the capacitor
clamping multilevel inverter (M>3) are obtained.
In Chapter 5, the
clamping inverter
is
modules each rated
3kW
experimental set-up for the half bridge three level capacitor
described in details.
at
The prototype employs four
1200V/50A driven by four
two main modules and two double
SEMIKRON IGBT
single intelligent drivers
intelligent drivers
(SKHI23)
(SKHI10)
for the
two
auxiliary modules.
is inserted.
Gating signals are
for the
Between the
driver and device, a zero voltage detecting circuit
generated in
EPROM 27256M, and time durations including the auxiliary gating signal width
and the main gating signal width are
set as discussed in
Chapter
2.
The proposed circuit and the analyses are well verified through the experimental
results
from this prototype.
Chapter 6
is
concemed with the
neutral potential stability in the
sub-harmonic modulation, the neutral potential
reactive,
is
NPC
inverter.
Under
stable as far as the inverter load is not pure-
due to the inherent feedback mechanism. The neutral potential response exhibits
139
The time constant of which
typical one-order system characteristics.
properties, modulation index,
When
joint effects
is
dependent on the load
DC link capacitances etc.
asyrnrnetries are taken into account, typically gating
the neutral potential
is
balanced
a
at
of the self balancing
new
ability
expected to cause any neutral potential
and switching mismatches,
operation point other than zero, dependent on the
and the Vasyrnmetry. Similarly, the dead time
drift
is
not
because of its symmetrical influence to the two
switching cells during the ftmdamental cycle.
When Space-Vector-Modulation (SVM) is used, the need for appropriate distribution of
the redundant states of the small vector arises, active control over the neutral potential
becomes indispensable. On the other hand, with sub-harmonic modulation,
when needed can be
effected
by
vertically shifting the
deviation direction and the operation
,
¿¿¡«
M,-4.
".*l'2'
,
zz
modulating reference according to the
mode (rectifying or inverting).
Self-balancing under ideal and non-ideal conditions are verified by
Chapter 7 proposes a True-PWM-Pole three
level
NPC
PSPICE simulations.
all
secured, with the
ú
¿¿_¡_
the
main devices and zero
current switching for
same performance as that in the two
By
installing the
cells,
zero voltage
inverter.
transformer comrection True-PWM-Pole to each of the two switching
switching for
active control
all
the auxiliary devices are
level inverter.
,
The transformer connection True-PWM-Pole technique along with
the Auxiliary-
Resonant-Commutated-Pole-Inverter (ARCPI) both are extensible' to the diode clamping
The
multilevel inverter (M>3).
basis.
The
auxiliary circuitry can be
configured on the
per-cell or per-leg
per-leg structure needs only one resonant inductor and one auxiliary transforrner,
while in the per-cell case, each
structure suffers
from the
cell
needs an inductor and a transforrner. However, the per-leg
indirect clarnping
problem also
in the auxiliary circuitry,
and
moreover, resonant current flowing involves multiple devices in the path.
Such extension leads
clamping multilevel
T
Finally, in
to four general zero voltage switching topologies for the diode
inverter.
Chapter
8,
a
new
diode clamping multilevel inverter
is
proposed, which
solves the problem of series association of diodes in the conventional diode clamping inverter.
However, the other aspects of operation remain the same as the conventional one.
In summary, the following conclusions are drawn from this thesis:
140
-
0 Multilevel inverters enable high voltage operation
and multi-step output without
requiring any magnetics insulation.
The clamping voltage
0
clamping inverter and the neutral potential in
in the capacitor
diode clamping inverter are both self-balancing under sub-harmonic modulation so long as the
load
is
not pure reactive.
0
The use of snubber
leads to the reduction of the switching stress but not necessarily
any significant increase in the switching frequency.
0
›
Transformer connection True-PWM-Pole technique offers an altemative of the
ARCPI
and enables high frequency high power operation.
Transformer connection True-PWM-Pole technique
_0
inverters with the
same performance
as in the
two
level case,
is
extensible to multilevel
which
facilitates
high voltage
and high power conversion at high frequency and high efficiency.
0
The new diode clamping
clamping diodes and
To
is
multilevel inverter
works
free
of the series association of
hence more applicable in practice.
the best of the belief of this thesis, the soft switched multilevel inverter
legitimate contender against the well-entrenched hard switched or
is
the
snubbed counterpart
especially for high performance applications, even though they face greater obstacles than at
the two-level
low power levels.
'
Looking ahead, several subjects deserve
further specific investigations:
0 Identification of potential problems, comparison of its variations, optimization of designing
and evaluation of performance of the modified auto-transformer connection True-PWMPole family under practical circumstances.
0 Possible clamping voltage drift of the capacitor_clamping inverter
drift
0
and neutral potential
of the diode clamping inverter under load unbalance or load transience conditions.
Solutions to the problems of the diode clamping multilevel inverter (M>3), including
H
indirect clamping, potential drift
0
and turn-on snubbing
Comparison of the diode clamping
etc.
inverter, the capacitor
bridge cascade inverter for different applications.
clamping inverter and the H-
141
References
[1]
G. Kaplan, “Industrial Electronics”, IEEE Spectrum, January 1997, pp. 79-83.
[2]
H. Stemmler, “High-Power Industrial Drives”, Proceedings of the IEEE, Vol. 82, No.
8,
`
pp. 1266-12s6,Augus1 1994.
'
.
H. Stemmler, “Power Electronics in Electric Traction Applications”, Record of IEEE
[3]
IECON,
1993, pp. 707-713.
Y. Sekine, K. Takahashi and T. Hayashi, “Application of Power Electronics Technology
[4]
Bulk Power Transmission
to the 21st Centu1y°s
Energy Systems, Vol.
[5]=:P;
No.
17,
3, pp.
in Japan”, Journal
of Electrical Power
&
181-193, 1995.
Hofer, N. Karrer and C. Gerster, “Paralleling Intelligent
IGBT Modules
with Active
Gate-Controlled Current Balancing”, Record of IEEE PESC, 1996, pp. 1312-1316.
Ch. Keller and Y. Tadros, “Are Paralleled
[6]
1
_
[7]
Better Choice ?”, Record of EPE Conference, 1993, pp. 5.1-5.6.
P. Steimer, H. Gruning, J Weminger, P. Dahler and G. Linhpfer, “Series Connection of
.-
-GTO
High Power
Thyristors for
1996, pp. 14-20.
[8]
C. Schauder,
Systems”,
Static
Frequency Converters”,
_
E. Stacey, T.
Lemak, L. Gyugyi,
H. Suzuki, T. Nakajima, K. Izumi,
S.
10,
No.
1997.
5,
T.
W. Cease and A.
Edris,
“
Trans. on
Power
3, pp.
1486-1496, July 1995.
Sugimuto, Y. Mino and H. Abe, “Development and
Testing of Prototype Models for a High Performance
IEEE
Review, No.
MVAR Static Condenser for Volatge 'Control of Transmission
IEEE Trans. on Power Delivery, Vol.
Converter”,
ABB
.
M. Gemhardt,
Development of A -100
[9]
IGBT Modules or Paralleled IGBT Inverters the
300MW Self-Commutated AC/DC
Delivery, Vol. 12, No. 4, pp. 1589-1601, October
`
[10] P. K. Steimer, H. E. Gruning,
J.
Weminger,
E. Carroll, S.
Klaka and
S. Linder,
New Technology for High Power Low Cost Inverters”, Record of IEEE IAS,
“IGCT - a
1997, pp.
1592-1599.
[11] C. Gerster, P.
Hofer and N. Karrer, “Gate-Control Strategies for Snubberless Operation
of Series Connected IGBTS”, Record of IEEE PESC, 1996, pp. 1739-1747.
142
[12]
Sigg,
J.
M. Bruckmann and P.
Turkes, “The Series Connection of IGBTs Investigated by
Experiments and Simulation”, Record of IEEE PESC, 1996, pp. 1760-1765.
[13] S. Mori,
K. Matsuno, M. Takeda and M. Seto, “Development of a Large
Using Self Commutated Inverters for Improving Power
Power Systems, Vol.
8,
No.
IEEE
Trans. on
February 1993, pp. 371-377.
1,
D. Wuest, H. Stemmler and G. Scheuer,
[14]
Stability”,
VAR Generator
Configurations for an Advanced
Static
“A Comparison of
Different Circuit
Var Compensator (ASVC)”, Record of IEEE
PESC, 1992, pp.521-529.
[15]
K. Matsui,
“A
Pulse Width 'Modulated Inverter with Parallel Connected Transistors
Using Current-Sharing Reactor”, Record of IEEE IAS, 1985, pp. 1015-1019.
and M. Morozowich, “30-
[16] R. Hoft, T. Khuwatsarnrit, A. Foldes
Auxiliary Power Supply for People Mover, Part
App., Vol. 19, No.
[17] T. A.
5, Sep./Oct.
I-
Power
kVA Transistor Inverter
Circuit”,
IEEE
Trans.
on
Ind.
1983, pp. 717-724.
Megnard and H. Foch, “Multilevel
Converters. and Derived Topologies for
Power Conversion”, Record of IEEE IECON, 1995, pp. 21-26.
[18] T. Salzmann, G. Kratz, C. Daubler,
High
'
“High Power Drive System with Advanced Power
Circuitry and Improved.Digital Control”,
IEEE
on
Trans.
Ind. App., Vol. 29,
No.
1,
Jan./Feb. 1993, pp. 168-174.
[19] P. G.
Kamp, “High Power Water. Cooled Three-Level
GTO
Modules
for the Static
Frequency Converter Muldenstein”, Record of EPE Conference, 1995, pp.l. 847-1. 851.
[20] H.
Stemmler, P. Guggenbach,_“Configurations of High-Power Voltage Source Inverter
Drives”, Record of
[21]
EPE Conference,
W. Schminke, “High Power Pulse
Medium Wave
[22]
Step Modulator for
Short
Vol. 72, No.
Wave and 600KW
5,
1985, pp. 235-
1
M. Marchsoni, M. Mazzucchelli and
for
500KW
Brown Bovery Review,
Transmitters”,
240.
1993, pp. 1.7-1.14.
Plasma
Stabilization”,
IEEE
S.
Trans.
Tenconi,
“A Non-conventional Power Converter
on Power Electronics, Vol.
5,
No.,2, April 1990,
pp. 212-219.
[23] T. Ghiara,
M. Marchesoni, L
Puglisi
and G. Sciutto,
“A Modular Approach to Converter
Design for High Power AC Drives”, Record of EPE Conference, 1991, pp. 4.477-4.482.
[24] P.
W. Hammond, “A New Approach to Enhance Power Quality for Medium Voltage AC
Drives”,
IEEE Trans on Ind. App., Vol.
33,
No.
1,
Jan./Feb. 1997, pp. 202-208.
143
N. Schibli and Ch. Briguet, “Direct Coupled 4-Quadrant Multilevel Converter
[25] A. Rufer,
for 16 2/3
Hembert,
F.
[26]
HZ Traction Systems”
Le Moigne and
P.
Record of IEE PEVD, 1997.
P.
J.
Cambromie, “Series Association of VSI in High
Power Active Filtering”, Record of IEEE PESC, 1996, pp. 759-764.
F. Z. Peng,
[27]
Separate
S. Lai
J.
and
J.
McKeever, “A Multilevel Voltage Source Inverter with
DC Sources for Static Var Generation”, Record of IEEE IAS,
1995, pp. 2541-
2548.
Fang Zheng Peng and Jih-Sheng
[28]
Lai,
“Dynamic Performance and Control of A
Static
VAR Compensator Using Cascade Multilevel Inverter”, Record of IEEE IAS, 1996, pp.
1009-1015.
and
[29] D. Perreult
J.
Kassakian,
“An Assessment of
Converter Systems”, Record of the
15'
Intemational
Cellular Architectures for Large
Power Electronics and Motion
Control Conference (IPEMC), 1994, pp. 70-79.
[30] T. A.
Meynard and
P.
'
Davancens, “Current Balance in Paralleled Commutation Cells”,
Record of PCIM, 1995.
Barbi,
“A New Technique for Parallel Connection of Commutation
Cells: Analysis, Designing
and Experimentation”, IEEE Trans. on Power Electronics,
[31] H. A. C.
_
Braga and
Vol. 12, No. 2,
[32]_._¡
A. Nabae,
Holtz and
J.
March
1997, pp. 387-393.
Takahashi, and A. Akagi,
I.
IEEE Trans.
[33]
I.
Ind. App., Vol. 19,
S. Stadtfeld,
“A New Neutral-Point Clamped PWM
No. 5, Sep./Oct. 1981, pp. 518-523.
“An Economic Very High Power PWM
Inverter”,
'
Inverter for Induction
Motor Drives”, Record of EPE Conference, 1985, pp. 3.375-3.380.
[34]
J.
M. Andrejak and M.
Lescure, “High Voltage Converters Promising Technological
Developments” Record of EPE Conference, 1987, pp. 1.159-1.162;
,
[35]
N.
S.
Choi,
Inverter”,
[36]
M.
J.
G. Cho, and G. H. Cho,
“A
_
General Circuit Topology of Multilevel
Record of IEEE PESC, 1991, pp. 96-103.
Carpita, S. Tenconi,
“A Novel
Multilevel Structure for Voltage Source Inverter”,
EPE Conference, 1991, pp. 1. 90-1. 94.
Yuan and I. Barbi, “A New Structure for Multilevel
Record of
[37]
X.
INEP-UFSC,
[38]
T.
Brazil,
Mamyama
March 1997
Inverter”,
Research Report,
.
and M. Kumano,
“New
Record of IPEC, 1990, pp. 870-877.
PWM
Control for
A
Three-Level Inverter”,
144
[39] T.
Meynard and H. Foch, “Multi-Level Conversion: High Voltage Choppers and Voltage
Source Inverters”, Record of IEEE PESC, 1992, pp. 397-403.
[40] G. Carrara, S. Gardella,
PWM
A
Method:
M. Marchesoni R.
Theoretical Analysis”,
Salutari
IEEE
and G.
Trans.
Sciutto,
“A New Multi-Level
on Power Electronics, Vol.7,
No.3, July 1992, pp. 497-505.
[41]
Shen and N. Butterworth, “Analysis and Design of a Three Level
J.
System
[42]
for
Railway Traction Applications”, IEE Pro. Elec. Power App., Vol. 144, No.
5,
Sep. 1997, pp. 357-371.
J.
Holtz, “Pulsewidth Modulation in Electronic
IEEE, Vol. 82, No.
[43]
H.
PWM Converter
8,
Power Conversion”, Proceedings of the
August 1994, pp. 1194-1214.
W. Van Der Brock, H.
C. Skudelny and
J.
V. Stanke, “Analysis and Realization of a
Pulsewidth Modulator Based on Voltage Space Vectors”,
Vol. 24, No.
1,
IEEE
Trans. on Ind. App.,
Jan./Feb. 1988, pp. 142-150.
Holmes, “The Significance of Zero Space Vector Placement for Carrier Based
[44] D. G.
PWM Schemes”, Record of IEEE IAS, 1995, PP. 2451-2458.
[45]
Y. Tadros,
Saluma, and R. Hof, “Three Level
S.
IGBT Inverter”, Record of IEEE PESC,
1992, pp.46-52.
[46]
M. Koyama,
PWM
Method
IECON,
[47]
S.
T. Fujji, R.
Uchida and T. Kawabata “Space Voltage Vector Based
for Large Capacity Three Level
GTO
Thyristors”,
Tamai, M. Koyama, T.
EPE Conference,
J.
Fujii, S.
Mizoguchi and T. Kawabata, “3 Level
1993, pp. 45-50.
Motor Drive”, Record of
PWM Control of a Three Level Inverter”,
_
Vol. 7, No. 3, July 1992, pp. 487-496.
M. Marchesoni, “High Performance Current Control Techniques
Multilevel High
Vol.
7,
No.
[50] F. Z. Peng,
Power Voltage Source
1,
Jan. 1992, pp. 189-204.
J.
S.
Lai and
J.
GTO
_
Steinke, “Switching Frequency Optimal
IEEE Trans. on Power Electronics”,
[49]
Record of IEEE
1992, pp. 271-276.
Converter-Inverter air System for Large Capacity Induction
[48]
New
Inverters”,
IEEE
Trans. on
for Applications to
Power
Electronics,
MeKeever, “A Multilevel Voltage-Source Converter System
with Balanced DC Voltages”, Record of IEEE PESC, 1995, pp.1144-1150.
F. Z.
[51]
Peng and
J.
145
“A
S. Lai,
Static
Var Generator Using a
Staircase
Waveform
Multilevel Voltage Source Converter”, Record of Power Quality Conference, Sep. 1994,
I
pp. 58-66.
[52]
R.
W. Menzies,
and
P. Steimer
J.
D
Induction Motor Drives”,
IEEE
K. Steinke, “Five Level .GTO Inverter for Large
Trans. on Ind. App., Vol. 30, No. 4, -July/Aug. 1994, pp.
938-944.
[53] Y. Chen, B.
Mwinyiwiwa,
Z. Wolanski and B. T. Ooi,
(UPFC) Based on Chopper
“Unified Power Flow Controller
Record of IEEE PESC,
Stabilized Multilevel Converter”,
A
1997.
G. Sinha and T. A. Lipo,
[54]
“A Four
Level Rectifier-Inverter System for Drives
Applications”, Record of IEEE IAS, 1996, pp. 980-987.
[55]
G. Sinha and T. Lipo, “Rectifier Current Regulation in Four Level Drives”, Record of
IEEE APEC,
[56]-
1997, pp. 320-326.
C. Hochgraf and R. Lasseter,
Employing a Multilevel
“A
Inverter”,
Transformer-less Static Synchronous Compensator
IEEE
Trans. on
Power Delivery, Vol.
April 1997, pp. 881-887.
[57] Y. Chen, B.
Mwinyiwiwa,
I
,.
[58] B.
No.
2,
No.
2,
«
Z. Wolanski and B. T. Ooi, “Regulating and Equalizing
Capacitance Voltages in Multilevel
12,
12,
STATCOM”, IEEE
Trans. on
Power Delivery, Vol.
April 1997, pp. 901-907.
Mwinyiwiwa, Z. Wolanski, B.
T.
DC
_
Ooi and Y. Chen, “Multilevel Converters as Series
VAR Compensators”, Record of IEEE PESC, 1997.
[59] O. Pollakowski, H. Pouliquen
and W. Schumacher, “State-Space Analysis of Diode-
Clamped Multilevel Voltage Source
EPE Conference,
[60] G. Scheuer
Inverters for Static
Var Compensation”, Record of
1997.
-
and H. Stemmler, “Analysis of a Three Level VSI Neutral Point Control
Fundamental Frequency Modulated
Conference on AC and
SVC Applications”,
for
Record of the 6th Intemational
DC Transmission, London, March 1996, pp..303-310.
_
[61] R. Rojas, T. Ohnishi and T. Suzuki,
“An Improved Voltage Vector
Control Method for
Neutral-Point-Clamped Inverters”, IEEE Trans. on Power Electronics, Vol. 10, No.
Nov., 1995, pp. óõó-672.
6,
146
[62]
M. Koyama, H. Okayama,
GTO
Controlled Three Level
“High Performance Vector
T. Tsuchiya and Y. Kinpara,
Inverter for Electric Traction”,
Record of IPEC-
Yokohama, 1995, pp. 766-771.
[63]
S.
Ogasawara and H. Akagi, “Analysis and Variation of Neutral Point Potential
Neutral-Point-Clamped Voltage Source
PWM Inverters”,
in
Record of IEEE IAS, 1993,
pp. 965-970.
[64]
C.
Newton and M. Sumner,
“Neutral Point Control for Multilevel Inverters: Theory,
Design and Operational Limitations”, Record of IEEE IAS, 1997, pp. 1336-1343.
[65] H.
Okayama etc., “Large
Capacity High Performance 3-Level
Record of IEEE IAS, 1996, pp. 174-179.
Steel Rolling Mill Drives”,
W. McMurray, “Resonant Snubbers with
[66]
App., Vol. 29, No.
[67]
2,
GTO Inverter System for
Auxiliary Switches”,
IEEE
Trans.
on
Ind.
March/April 1993, pp. 355-362.
H. Okayama, T. Tsuchiya and M. Kimata, “Novel Gate Power Supply Circuit Using
GTO
Valves”, Record of
EPE
G. L. Skibinski and D. M. Divan, “Design Methodology and Modeling of
Low
Snubber Capacitor Energy for Series Cormected
Conference, 1997.
[68]
Inductance Bus Structures”, Record of EPE Conference, 1993, pp. 5.98-5.105.
[69] E. Clavel,
IGBT
J.
Roudet and Y. Marechal, “Design of a Commutation Cell of a High Power
Inverter
-
The Contribution of the Simulation”, Record of IEEE IAS, 1997, pp.
1014-1021.
[70]
I-I.
'
Miyazaki, H. Fukumoto,
S.
Sugiyama, M. Tachikawa and N. Azusawa, “Neutral-
Point-Clamped Inverter with Parallel Driving of IGBTS for Industrial Applications”,
Record of IEEE IAS, 1997, pp. 1292-1299.
[71] T.
Meynard and H. Foch, “Multi-Level Choppers
Journal of EPE, Vol. 2, No.
[72] F.
Hamma, T. A. Meynard,
1,
F.
P. Carrère, T.
Meynard and
Leg”, Record of
[74] T. A.
High Voltage
Applications”,
March 1992, pp. 45-48.
Tourkhani and P. Viarouge, “Characteristics and Design of
Multilevel Choppers”, Record of IEEE
[73]
for
J.
PESC, 1995, pp. 1208-1214.
P. Lavieville,
EPE Conference,
“4000V-300A Eight-Level IGBT
Inverter
1995, pp. 1106-1111.
Meynard, M. Fadel and N. Aouda, “Modeling of Multilevel Converters”, IEEE
Trans.
on Ind.
Elec., Vol. 44,
No.
3,
June 1997, pp.
1-9.
147
IEEE
A. Steimel, “Electric Railway Traction in Europe”,
[75]
Industry Applications
J
Magazine, Nov./Dec. 1996, pp. 7-17.
W. McMurray,
[76]
Transistors Switching Converters”,
IEEE
July/August 1980, pp. 513-525.
[77]
Clamps
“Selection of Snubbers and
Trans.
on
to
Optimize the Design of
Ind. App., Vol.
No.
4,
_
M. H. Pong and R. D. Kackson, “Computer Aided Design of Power
Snubber Circuits”, IEE Proceedings, Vol. 134, Part B, No.
T. Undeland, F. Jenset, A. Steinbakk, T.
[78]
16,
Configuration for Both Power Transistors and
Transistor Inverter
March 1987, pp. 69-78.
2,
Ronge and M. Hemes, “A Snubber
GTO Inverters”,
Record of IEEE PESC,
1984, pp. 42-53.'
[79]
R. Marquardt, “High Power
ICE”, Record of
EPE Conference,
W. Runge and A.
[80]
GTO
Steimel,
Converters for The
New German
High Speed Train
1989, pp. 1.583-1.588.
“Some Aspects of
Circuit Design of
High Power
Converters”, Record of EPE Conference, 1989, pp. 1.555-1.560.
[81]
W. McMurray,
“Efficient Snubbers for Voltage Source
Power Electronics, Vol.
[82] V. Gilblas
and
F. Favo,
2,
No.
3,
GTO
V
GTO Inverters”, IEEE Trans. on
July 1987, pp. 264-272.
“Low Losses New Snubber Circuit for High Power GTO Inverter
Application: Tests and Results”, Record of EPE Conference, 1991, pp. 2-534-2.539.
[83]
W. W.
Fuhrer, R. Marquardt and G. Papp, “Water Cooled
for Electric Traction”,
[84]
M.
GTO Converters
Record of EPE Conference, 1993, pp. 5.294-5.298.
Jung, “Improved Snubber for
Passive Network”, Record of
[85]
High Power
GTO
Inverters with
EPE Conference,
Energy Recovery by Simple
1987, pp.15-20.
A. Brambilla and E. Dallago, “Snubber Circuits and Losses of Voltage Source
Inverters”,
IEEE Trans. on Power Electronics, Vol.
[86] B. Snyners, Ph. Lataire, G.
Voltage Source
_
7,
No.
1,
GTO
Jan. 1992, pp. 231-239.
Maggeto, B. Detemrnerman, and
J.
M. Bodson, “Improved
GTO Inverter with New Snubber Design”, Record of EPE Conference,
1987, pp. 31-36.
[87] B.
W.
Williams, “High Voltage High Frequency Power Switching Transistor Module
with Switching Aid Circuit Energy Recovery”, IEE Proceedings, Vol. 131, Part B, No.
1,
Jan. 1984, pp. 7-12.
[88] J A.
.
Tarfiq and Y. Shakweh, “New Snubber Energy Recovery Scheme
1
Traction Drive”, Record of IPEC-Yokohama, 1995, pp. 825-830.
for
High Power
148
[89] G. Fregien,
H. G. Langer and H. C. Skudelny,
GTO Inverter”, Record of IEEE
1988, pp. 498-505.
“A New Snubber Energy
Irokawa, T. Kitahara, F. Ichikawa and T. Nakajima,
S.
[90]
PESC,
“A Regenerative Snubber for A 200KVA
Recovery Method for Voltage Source Self-Commutated Converters”, Record of IPEC-
Yokohama, 1995, pp. 1572-1577.
Scharnbock and K. Schiftner,
[91] H.
Recovery by an Active/Passive
[92]
J.
“
“A New Snubber
Circuit”,
Holtz and S. Salama, “Megawatt
for
GTO
Applications with Energy
Record of EPE Conference, 1989, pp. 707-711.
GTO
Inverter with Three Level
PWM Control and
Regenerative Snubber Circuits”, Record of IEEE PESC, 1988, pp. 1263-1270.
[93]
J.
D.
Kim and
Inverters”,
[94] H.
G. H. Cho,
“A
Regenerative Snubber for Three Level High Power
EPE Conference, 1991, pp. 2.474-2.479.
Tsuchiya, “A Novel Regenerative Snubber
GTO
Record of
Okayama and
T.
Circuit for Three Level
GTO Inverters”, Mitsubishi Electric ADVANCE, June 1997, pp. 24-26.
[95] F. C. Zach, K. H. Kaiser,
J.
W. Kolar and F.
J.
Haselsteiner,
“New Lossless Tum-on and
Turn-off (Snubber) Networks for Inverters, Including Circuits for Blocking Voltage
Limitation”,
[96] A.
IEEE Trans. on Power Electronics, Vol.
Agbossou,
I.
Rasoanarivo and B. Davat,
1,
No.
“A Comparative
2, April 1986,- pp. 65-75.
Study of High Power
IGBT
Model Behavior in Voltage Source Inverter”, Record of IEEE PESC, 1996, pp. 56-61.
[97] A. Millner, S. Keir,
J.
Wen
and R. Galante,
“A High Power DC-AC
Staggered Regenerative Recovery Circuit”, Record of IEEE
[98]
K. B. Hughes, C. D. Schauder, M. G. Gernhardt and E.
Circuit Parameters
on the Tum-off Spike of Large
GTO
J.
APEC,
Inverter with
1995, pp. 973-976.
Stacey, “Effect of Snubber
Thyristors”,
Record of IEEE
IAS, 1993, pp. 1280-1285.
[99]
M. A. E. Andersen, “Comparison of Three IGBT Inverters, One Hard-Switched and Two
with Snubber Circuits Using
A Minimum Number
of Components”, Record of
EPE
Conference, 1993, pp. 3.306-3.311.
[100] L. Fratelli and G. Giannini, “Dual-Voltage
Power System
in
Heavy
1996, pp. 1414-1419.
[101]
I.
Traction, Using
High Power Converter
for a Distributed
High Voltage IGBTs”, Record of IEEE PESC,
_
Barbi and A. Ferrari de Souza, “Comutação Suave”, Postgraduate Course-INEP-
UFSC,
1995.
[102]
W. McMurray, “Power
149
Electronics in the 1990s”, Record of
IEEE IECON,
1990, pp.
839-843.
[103] R. L. Steigerwald,
Power
[104]
J.
“A Review of Soft
Supplies”, Record of IEEE
Petzoldt, S.
IECON,
J.
G. Cho,
J.
Full Bridge
DC
1995, pp.1-7.
Bemet and T. Reimann, “Comparison of Power Converters with DC and
AC Link”, Record of EPE Conference,
[105]
Switching Techniques in High Performance
Sabate, G.
Hua and
1993, pp. 3.189-3.195.
F. C. Lee,
“Zero Voltage and Zero Current Switching
PWM Converter for High Power Applications”,
Record of IEEE PESC,
`
1994, pp. 102-ros.
[106]
W. McMurray,
'
_
“Thyristor Commutation in
DC
Choppers
-
A
Comparative Study”,
IEEE Trans. on Ind. App., Vol. 14, No. 6, Nov./Dec. 1978, pp. 547-557.
[107] A. Abbondanti and P. Wood, “A Criterion for Performance Comparison Between High
Power
z
I
Inverter Circuits”,
IEEE
Trans. on Ind. App., Vol. 13, No. 2, March/April 1977,
pp. 154-160.
_
'
[108] G. K. Dubey, “Classification of Thyristor
Commutation Methods”, IEEE Trans. on
Ind.
App., Vol. 19, No. 4, July/August 1983, pp. 600-606.
[109] N. H. Kutkut, D.
,
M. Divan, D. W. Novotny and R. Marison, “Design Considerations
and Topology Selection for
IEEE PESC,
A l20kW IGBT
Converter for
EV
Charging”, Record of
1995, pp. 238-244.
.
[110] F. Forest, J Gonzalez and F. Costa, “Use of Soft-Switching Principles in
.
Inverters Design”, Record of EPE Conference, 1993, pp. 3.5-3.10.
[111] D.
M. Divan and G.
PWM Voltage
A
Skibinski, “Zero-Switching-Loss Inverters for
High-Power
Applications”, Record of IEEE IAS, 1987, pp. 627-634.
[112]
M. H. Kheraluwala and D. M. Divan, “Delta Modulation
Inverters”,
[113] D.
Strategies for
Resonant Link
Record of IEEE PESC, 1987, pp. 271-278.
M. Divan, “Low-Stress Switching
for Efficiency”,
IEEE Spectrum, Dec. 1996,
pp.
33-39.
[114]
I.
T. Wallace, N. H. Kutkut, S. Bhattacharya, D.
M. Divan and D. W. Novotny,
“Inductor Design for High Power Applications with Broad Spectrum Excitation”,
Record of IEEE PESC, 1995, pp. 1057-1063.
[115] G. Venkataramanan and D.
M. Divan, “Pulse Width Modulation with Resonant
Link Converters”, Record of IEEE IAS,l990, pp. 1215-1221.
DC
150
M. Divan and G. Venkataramanan, “Comparative Evaluation of Sofi Switching
[116] D.
Inverter Topologies”,
Record of EPE Conference, 1991, pp. 2.013-2.018.
[117] L. Malesani, P. Tenti, P.
Tomasin and V. Toigo, “High Efficiency Quasi-Resonant
PWM”, Record of IEEE APEC,
Link Three Phase Power Inverter for Full-Range
DC
1992,
pp. 472-478.
[118] S. Salama and Y. Tadros, “Novel Soft Switching Quasi-Resonant 3-Phase
Inverter”,
[119] F.
Record of EPE Conference, 1995, pp. 2.95-2.99.
Mendes de Seixas and D.
J.
C. Martins, “The
ZVS-PWM Commutation Cell Applied
DC-AC Converter”, IEEE Trans. on Power Electronics, Vol.
to the
IGBT
12,
No.
4, July 1997,
pp. 726-733.
[120]
H. Foch, Y. Cheron, M. Metz and T. Meynard, “Commutation Mechanism and Soft
Commutation
[121] P. P.
Mok, R.
in Static Converters”,
Spee, H.
J.
Record of COBEP, 1991, pp. 338-346.
Beukes and
J.
H. R. Enslin, “Control Complexities Related to
A
High Power Resonant Inverters”, Record of IEEE PESC, 1996, pp. 1040-1046.
[122] G. Bingen, “Utilisation de Transistors a Fort Courant et Tension Elevee”, Record of
EPE Conference,
[123] H.
J.
Beukes,
J.
1987, pp. 1.15-1.20.
_
Converter Topologies in Utility Applications”, Record of
522.
Inverter”,
[125] H.
IEEE PESC,
1995, pp. 517-
'
W. De Doncker and
[124] R.
AC/AC
H. R. Enslin and R. Spee, “Experimental Evaluation of
J.
J.
P.
Lyons, “Then Auxiliary Resonant Commutated Pole
Record of IEEE IAS, 1990, pp. 1228-1235.
Beukes,
J.
H. R. Enslin and R. Spee, “Integrated Active Snubber for High Power
IGBT Modules”, Record of IEEE APEC,
[126] K. Iida, T. Sakuma, A. Mechi, H.
Conducting Inductance
1997, pp. 161-167.
Matsuo and
in the Auxiliary
F.
Kurokawa, “The Influence of the
Resonant Commutated Pole Inverter”, Record
of IEEE PESC, 1997, pp. 1238-1245.
[127] F. F. Protiwa and
J.
KOB, “A 20
_
kVA Auxiliary Resonant Commutated Pole Converter-
Design and Practical Experiences”, Record of EPE Conference, 1995, pp. 2.111-2.116.
[128] F. R. Salberta,
kHz
J.
S.
Mayer and R.
Auxiliary Resonant
pp. 1246-1252.
T. Cooley,
“An Improved
Control Strategy for a 50-
Commutated Pole Converter”, Record of IEEE PESC, 1997,
.
151
[129] H.
Beukes,
J.
J.
H. R. Enslin and R. Spee, “Performance of the Auxiliary Resonant
Commutated Pole Converter
in Converter
Based
Utility Devices”,
Record of IEEE
PESC, 1996, pp. 1033-1039.
[130]
I.
Barbi and D. C. Martins,
Additional
“A True PWM Zero Voltage
RMS Current Stress”, Record of IEEE PESC,
Switching Pole with Very
Low
1991, pp.261-267.
kVA Soft Switching PWM Type AC Auxiliary
Power Supply System of the Electric Railway Rolling Stock Using an Improved ARCP
[131] H. Matsuo, K. Iida and
Harada, “210
Three Phase Inverter with SI Thyristor Switches”, Record of IPEC-Yokohama, 1995,
pp. 831-836.
[132] R. L. Steigewvald, R.
DC-DC
Power
No.
32,
[133]
J.
P.
W. De Doncker and M. H. Kheraluwala, “A Comparison of High-
Soft-Switched Converter Topologies”,
5, Sep./Oct.
1996, pp. 1139-1145.
IEEE
Trans.
on
Ind. App., Vol.
_
b
Gegner and C. Q. Lee, “Zero-Voltage-Transition Converters Using an Inductor
A
Feedback Technique”, Record of IEEE APEC, 1994, pp. 862-868.
[134] S. Frame, S. Dubovsky, Q. Li, D. Katsis, C. Cuadros, B. Borojevic and F. C. Lee,
“Three-Phase Soft-Switching Inverters for Electric Vehicle Applications”,
VPEC
Seminar, 1995, pp. 45-52.
[135] G. Moschopoulos, P. Jain and G. Joos,
Converter”, Record of IEEE
“A Novel Zero-Voltage Switched PWM BOOST
PESC, 1995, pp. 694-700.
[136] H. Stemrnler and T. Eilinger, “Spectral Analysis of the Sinusoidal
,
PWM with Variable
Switching Frequency for Noise Reduction in Inverter-Fed Induction Motors”, Record of
'
[137]
IEEE PESC,
J.
Shen, J
1994, pp. 269-277.
A
.
Taufiq and A. D.
Characteristics of Traction
No.
2,
.
Mansell, “Analytical Solution to Harmonics
PWM Converters”, IEE Pro.-Elec. Power App.,
March 1997, pp. 158-168.
[138] A. Weschta,
W. Weberskirch,
Vol. 144,
'
.
“Nonlinear Behavior of Voltage Source Inverters with
Power Transistors”, Record of EPE Conference, 1989, pp. 533-537.
[139]
J.
S. Lai, R.
Evaluation of
W. Young,
a'
G.
W.
Ott and
J.
W. McKeever, “Efficiency Modeling and
Resonant Snubber Based Soft-Switching Inverter for Motor Drive
Applications” , Record of IEEE
PESC, 1995, pp. 943-949.
[140]
SEMIKRON Data-sheet, Oct.
[141]
IGBT Designer°s Manual, Intemational Rectifier,
1996, pp.
B 6.17- B 6.22.
1996, pp. E105-E115.
152
-
[142] 'W.
Yi and G. H. Cho, “Novel Snubberless Three-Level
GTO Inverter with Dual Quasi-
Resonant DC-Link”, Record of IEEE PESC, 1991, pp.880-884.
[143]
J.
G. Cho,
W. Back, D. W. Yoo and
J.
Commutated Pole Inverter
for
»
C. Y.VWon, “Three Level Auxiliary Resonant
High Power Applications”, Record of IEEE PESC, 1996,
H
pp.1019-1026.
[144] J QR. Pinheiro and
Voltage
[145]
I.
Barbi, “The Three Level
PWM Converter-A New Concept in High
DC to DC Conversion”, Record of IEEE IECON,
H. Song,
Inverter
I.
S.
B. Yoo, B. S. Suh and D. S. Hyun,
Topology
for
High Voltage
1992, pp. 173-178.
“A Novel Three Level ZVS
DC/DC Conversion with Balanced Voltage
PWM
Sharing
1
and Wider Load Range”, Record of IEEE IAS, 1996, pp. 973-979.
[146] G. Botto,
IGBT°s
for
M.
and
S.
Tenconi, “Series Connected Soft Switched
High Power, High Voltage Applications: Experirnental Results”, Record of
IEEE PESC,
[147]
Carpita, E. Gilardi
1997.
M. Delnnlow, K. Heumann, H. Jorgensen and G.
in
-
SpieB, “Series Connection of IGBTS
Resonant Converters”, Record of IPEC-Yokohama, 1995, pp. 1634-1638.