TECHNOLOGYupdate
JON MARK HANCOCK
Principal Engineer AC-DC Applications
Infineon Technologies, Inc.
Applications Key In Selecting
Super-Junction MOSFETs
Application differentiation and market needs will
likely see a wide range of power MOSFET offerings in
varied cost and performance available, addressing
different system needs and customer budgets.
T
he decade-long evolution of super-junction
MOSFETs has seen the silicon limit broken, the
ongoing reduction of area specific RDS[ON]
and continued chip size reduction leading
to attendant cost/performance improvements
[1]. Yet, these improvements have not solved
all the power designer’s problems!
In fact, success in attacking some performance issues
around gate charge have led to new challenges in completing
a robust design, particularly if good layout practices are not
understood [2]. This is where understanding the underlying
application issues and how they relate to the MOSFET electrical characteristics becomes quite important, because we
can dig deeper into optimizing high voltage MOSFET behavior through knowledge of specific application issues. Then,
patterns begin to emerge about the performance and characteristic changes needed for different topologies and classes
of operation. Keeping that concept in mind, we will explore
the continuing evolution of super-junction MOSFETs in the
10
9
8
C6
C3
QGS
7
Gate Voltage
CP
QGD
6
5
4
3
2
1
0
0
10
20
30
40
50
60
70
80
90
C3, C6, CP Gate Charge, nC
Gate charge comparison for 190 mohm devices at ID=20 A,
CoolMOS C3, C6, CP
Fig. 1. Gate charge comparison for 190 mΩ devices at ID=20A, CoolMOS C3, C6, CP.
14
Power Electronics Technology | November 2010
011PETOPDupdate.indd 14
industry, as pioneered by CoolMOS™ 10 years ago, and
looks at the directions for continued development.
First, area-specific RDS[ON] has improved significantly
compared to the technology highlighted 10 years ago
in PCIM. In 2005, production CoolMOS technologies
improved area specific RDS[ON] by about 35%, reducing
the on-state resistance from 39 mΩ/cm2 to about 25 mΩ/
cm2 [3,4]. This technology step also included substantial
reductions in QGD switching charge of the MOSFET- overall as much as 60-65%. Fig. 1 compares gate charge characteristics of three 190-199 mΩ FET families – C3 (2003),
CP (2005) and C6 (2009) – switched at 20A load current.
Coupled with significant reductions in COSS output capacitance, which is a primary loss mechanism in hard switching,
switching efficiency of the CP generation was substantially
improved over that of C3 [3, 4, 5]. All of this is very well
and good, but is this the answer to everyone’s performance
prayers? If we delve more deeply into other application
requirements, we may see that’s not the case.
SWITCHING TOO FAST?
While there are many application topologies and possible
operating modes, we will focus on just a few popular ones
very commonly used. A major category long in service is the
single-ended hard switching topology, whether direct or indirect mode (forward or flyback or boost), either in DCM (discontinuous conduction mode), CrCM (Critical Conduction
mode), or CCM (Continuous Conduction Mode). The first
two run triangular current waveforms with zero initial current and low turn-on loss; the performance requirement is
for minimum conduction resistance and low turn-off loss at
high current. Here, the SJ concept MOSFET works well,
because of the area specific RDS[ON] and the non-linear
capacitive snubber effect of the output capacitance [3, 4].
Low COSS also leads to low EOSS at turn-on, aiding DCM
performance. In these topologies, the quasi-ZVS mode turnoff lends efficiency advantages, with the conduction channel
turning off quickly and the output capacitance merely being
charged by inductive load current at turn off.
The low gate charge of CoolMOS CP is a function of low
gate-drain overlap capacitance, which improves switching
speed but lowers “control” of di/dt. In most of these topologies, especially when transformer coupled, this doesn’t
usually pose a problem, as intrinsic circuit impedances tend
www.powerelectronics.com
11/3/10 2:20:15 PM
PCB layout. Fig. 2 illustrates the nature of the configuration of MOSFET and PCB parasitics, which if not in the
right proportions can lead to oscillatory behavior at turn-on
and turn-off. Besides the internal drain-to-gate feedback
capacitance, there is an external capacitance largely determined by the MOSFET package and the PCB foil layout.
Worse yet, the external capacitive influence is coupled
through parasitic inductances, leading to some additional
phase shift. Minimizing the external drain to gate coupling
capacitance is the key, coupled on occasion with palliative
measures such as ferrite beads with substantial resistive loss
at 100 MHz, on the order of 30-50 Ω [1]. Then clean fast
switching is obtained; in fact, very fast switching. For some
topologies and applications, it will be too fast.
Drain
Lead + bond
wire inductance
Resonant
circuit
External parasitic
coupling
capacitance
Cgd
Rg int
Rg
External
Lead + Gate
bond wire
inductance
Cds
Cgs
Lead + bond
wire inductance
Source
Fig. 2. Understanding the MOSFET and PCB together - internal capacitances and
external influences.
to limit di/dt and dV/dt. With circuits like the PFC boost
converter, the low circuit impedances and potential for high
di/dt and dV/dt requires more care by the designer. The flip
side of low gate charge is low CRSS, and more sensitivity to
A MEASURED APPROACH
So, while this class of application is well served by the very
fast switching and low turn-off loss of CP, in other applications, a literally more measured approach is necessary. This
was a significant component of the development thrust for
the C6/E6 series introduced in 2009, where controlled di/dt
and dV/dt were mandated over a wide load current range.
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011PETOPDupdate.indd 15
November 2010 | Power Electronics Technology
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SUPERJUNCTIONmosfets
Id (A)
Why was that needed?
60
Looking at applications like totem pole D
F
C
5
6
N
7
4
W
_P
S
IIDS_SPW47N65CFD
Qrr C3 = 20 µC
3
C
5
6
N
7
4
W
P
S
_
s
d
IIds_SPW47N65C3
inverter stages with or without reactive curTrr C3 = 729 ns
D
F
C
8
0
R
5
6
IIds_IPW65R080CFD
40
rent flow through the body diode, a focus ds_IPW
on controlled switching speed is a neces20
sary approach, even when the MOSFETs
Qrr C6 CFD = 1,40 µC
Qrr C3 CFD = 2 µC
are quite rugged at high speeds. This is
Trr C6 CFD = 189 ns
Trr C3 CFD = 189 ns
0
driven by the limitations of the majority of
floating drivers or half-bridge configured
driver products, which often have CMRR
-20
di/dt = 100 A/µs
(Common Mode Rejection Ratio) upper
limits in the range of 15-40V/ns. While
-40
reducing output capacitance lowers turnon losses, it also leads to higher dV/dt.
-60
-0,3
-0,1
0,1
0,3
0,5
0,7
0,9
1,1
Reasonably fast voltage/current crossover
time (µs)
speed for controlled losses needs to be
Improved body diode commutation behavior for CFD devices
with lower Qrr and softer slope current turn-off
combined with controlled di/dt and dV/dt
over a wide load current range, so that as
load current increases, a controlled switch- Fig. 3. Improved body diode commutation behavior for CFD devices with lower Qrr and softer slope current
ing rate is maintained. This requires care turn-off.
in engineering the gate overlap capacitance
and providing gate control of switching rates over a wide
super-junction MOSFETs lies not in the conceptualizadrain current range up to typical maximum link voltages,
tion of the necessary structures, but in the development of
usually in the range of 400V.
feasible manufacturing processes- achievable in commercial
For applications requiring body diode conduction and
quantities and yields, with high process Cpk. At the heart
hard commutation recovery of the body diode, the applicaof this difficulty is the fundamental physical relationships
tion has even stricter requirements. A carefully engineered
required for low area specific RDS[ON]: the column aspect
approach to the intrinsic body diode as well as the gate
ratio, which limits the doping that may be used for a given
capacitance overlap is required to enable consistent robust
blocking voltage target.
performance in these high power bridge type applications, as
Super-junction column aspect ratio ASJ = tSJ/WSJ,
well to control di/dt and peak overshoot voltage during comwhere tSJ is the height of the charge compensation columns
mutation recovery. This dictates the inclusion of an opti(p columns under the main p-wells), and WSJ is the cell
mized lifetime killing process to reduce body diode Qrr [6].
pitch. Then for a SJ MOSFET: RDS[ON].A∝1/ASJ. The
This is even more critical for the super-junction MOSFET
implication of these relationships is the necessity to fabricate
with its compensation structure columns, because typical
high aspect ratio columns with consistency and the required
behavior of the compensation columns is to limit the diode
charge balance, with relatively high doping profiles. Fig.
voltage rise until essentially all carriers have been swept out
4 documents some of the area-specific RDS[ON] results
of the lower epitaxy near the substrate. This typically results
of published research efforts, mainly using a trench filling
in an abrupt collapse in current and high di/dt at the end of
approach borrowed from DRAM fabrication, instead of
the commutation interval. The high collapsing di/dt then
the multi-epi growth with annealing used for most existing
causes dv/dt through the inverter loop inductance, with the
generations of commercial products. Recent papers [7] even
potential to develop over-voltage spikes and avalanche. Fig.
focus on newly developed measurement and analysis tech3 highlights improvements possible in total Qrr and recovery
niques needed to evaluate structures and process developend slope possible with improved design and processes.
ment, in order to develop the control needed for commercial
processes. Other process approaches such as high-energy
implant have demonstrated laboratory feasibility, but have
ROOM FOR IMPROVEMENT
drawbacks for use as a production process [8].
These application concerns highlight that there is more
While Izak Bencuya expected significant advances in
to HV MOSFETs than just area specific RDS(ON). Yet,
production devices as long ago as 2005 [9], these have been
the race is clearly on for improvements in that metric, as
slow to materialize in commercial volume, probably due to
a sampling of the available published papers shows in Fig.
the difficulties in implementing trench filling processes with
4. These publications are just the tip of the iceberg of the
commercial yields. Still, the historical trends of development
developments underway at industry leaders.
as outlined by Bencuya would indicate we’re overdue for
The challenge for improving area specific RDS[on] of
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Power Electronics Technology | November 2010
011PETOPDupdate.indd 16
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11/3/10 2:20:22 PM
Specific on-resistance RonA (mΩcm2)
100
51 mΩ/cm2
42 mΩ/cm2
39 mΩ/cm2
39 mΩ/cm2
27 mΩ/cm2
20 mΩ/cm2
21 mΩ/cm2
16 mΩ/cm2
15.0 mΩ/cm2
10
only high performance applications where some extra cost
is acceptable, not the likely much higher pricing anticipated
to be seen for SiC and GaN solutions predicted for the 2011
to 2012 time frame. Application differentiation and market
needs will likely see a wide range of product offerings in
varied cost and performance available, addressing different
system needs and customer budgets.
Si-Limit
10 mΩ/cm2
9.0 mΩ/cm2
4.8 mΩ/cm2
1.5 mΩ/cm2
1
100 V
Fairchild ISPSD 2005
Deboy IEDM 1998
Philips ISPSD 2005
Mitsubishi ISPSD 2000
Deboy ISPSD 2004
HE Implant
Fuji 2006 ISPSD 2006
Toshiba ISPSD 2006
Denso/Toyota ISPSD 2006
Shindengen ISPSD 2003
Toshiba ISPSD 2009
REFERENCES
1. J. Hancock, F. Bjork, G. Deboy, “AN-CoolMOS-CP-01 Application Note
CoolMOS CP”, published by Infineon Technologies, AG, Austria.
2. L. Lorenz, I. Zverev, J. Hancock, “Second Generation CoolMOS Improves
on Previous Generation’s Characteristics”, PCIM Magazine, Nov. 2000.
3. J. Hancock, “Meeting the Challenge for OfflineSMPS Through Improved
Semiconductor Current Density”
4. J. Hancock, “Superjunction FETs BooST Efficiency in PWMs”, Power
Electronics Technology Magazine, July 2005.
5. J. Hancock, “Bridgeless PFC Boosts Low-line Efficiency”, Power Electronics
Technology Magazine, February 2008.
6. G. Deboy, J. Hancock, M. Puerschel, U. Wahl, A. Willmeroth, “Compensation
devices solve failure mode of the Phase Shift ZZVS Bridge during light load
operation”, Proceedings APEC Conference 2002.
7. S. Ono, L. Zhang, H. Ohta, M. Watanabe, W. Saito, S. Sato, H. Sugaya,
and M. Yamaguchi, “Development of 600V-class trench filling SJ-MOSFET
with SSRM analysis technology”, ISPSD 2009.
8. M. Rub, M. Bar, G. Deboy, F.J. Niedernostheide, M. Schmitt, H. Schulze,
Al. Willmeroth, “550V Superjunction 3.9 Ω/mm2 Transistor Formed by 25 MeV
Masked BoRDS[on] Implantation”, ISPSD 2004.
9. I. Bencuya, “The Future of Power Semiconductors”, APEC 2005 Plenary.
1000 V
Lowest Ron*Area at a glance, Trench filling SJ in published works
Fig. 4. Lowest Ron×Area at a glance, trench filling SJ in published works.
some significant advance in commercial devices. But the
difficulties of fabrication and likely process complexity may
position these components as an intermediate solution for
High Power RF MOSFETs
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