ISAR - International Journal of Electronics and Communication Ethics - Volume 1 Issue 1, 2016
RESEARCH ARTICLE
OPEN ACCESS
IMAGE PROCESSING TECHNIQUES USING FPGA FOR DETECTING
SPEEDING VEHICLES
1, 2, 3
Jaydev.M.Bhavsar1, Abhishek Pohekar2, Nikita Gaikwad3
(Dept. of Computer Engineering, D.Y.P.I.E.T., Savitribai Phule Pune University, Pune)
Abstract:
As the traffic problems in urban areas are getting augmented, traffic surveillance systems based on video are
fascinated over past years. This study aims to develop speed violated vehicle detection system with image
processing method using FPGA. Image processing is a technique to change an image into digital form and perform
some operations on it, in order to get an improved image or to extract some useful information from it. It is a kind of
signal dispensation in which input is image, like video frame or photograph and output might be image or
characteristics linked with that image.
Keywords — Image Processing, Field Programmable Gate Array, Real Time, Pedestrian protection.
1. INTRODUCTION
In the past few years, there has been a massive
progress in the field of embedded system. The
developing requisite for image processing applications
mandatory researcher across the world to come up with
pioneering design methods that can meet the want for
these kinds of applications. Maximum of these designs
use high level programming languages, a lot of them use
Matlab utilities, which make researchers capable to form
an application with a couple lines of coding and in some
circumstances, and they use C/C++ languages for
forming the image processing applications. though this
applications works in Matlab environment, they are not
yet progressive sufficient to create a system that can run
on a hardware, for the reason that Matlab use matrix
algorithms and this algorithms cannot be instigated on a
hardware that do bit by bits processing. It is a similar
story with applications inscribed with higher level
programming languages like C/C++. Some of this
programs still could be run on a CPU inside a hardware
like microprocessors or CPU inside a FPGA chip, but
maximum of them infringe one of fundamentals of real
image processing applications, this applications want to
be Real Time, for the reason that software accomplishes
in a sequential manner where hardware can perform
entirely parallel . One of best approach of implementing
this kind of applications is using pure hardware chips,
we can usage Application Specific Integrated Circuit
(ASIC) or Field Programmable Gate Array (FPGA) for
this purpose, but ASIC are not apt for image processing
purpose, ASSIC take longer time to form and it is not
variable. The main reason is, for most of Image
Processing applications designer want to change the
design for any alteration in the environment like change
ISSN: Under Process
of location, angel or any other physical changes occurs
in the background. This is where FPGA can come in, for
the reason that it has a high performance of ASIC and
litheness of Microprocessors. FPGAs chip can be
reconfigured simply if any modification wanted, but this
is not the case for ASIC designs.
The purpose of this task is to implementing a
Vehicle Speed Detection that use output of Traffic
Cameras that installed in numerous highways across the
world as input and with some algorithms that will
identify locations of cars in each frames. By having car
locations in each frames and knowing the time amid
each frames it is likely to compute speed of cars, the
approach will be fully conferred later.
Image processing chiefly comprises the following three
steps.
 Importing the image with optical scanner or by
digital photography.
 Analysing and manipulating the image which
comprises data compression and image
improvement and spotting patterns that are not
to human eyes like satellite photographs.
 Output is the last stage in which result can be
changed image or report that is based on image
analysis.
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ISAR - International Journal of Electronics and Communication Ethics - Volume 1 Issue 1, 2016
FPGA (Field Programmable Gate Array):
FPGAs are programmable semiconductor
devices that are based around a matrix of Configurable
Logic Blocks (CLBs) connected through programmable
interconnects. FPGAs can be programmed to the wanted
application or functionality necessities. Using HDL ie
hardware descripting language like VHDL, VERILOG,
etc. Logic blocks presented below are made up of simple
gate preparation which makes a multiplexer type design
with some precise lookup table (Truth table), and this
truth table is fed to logic blocks using HDL.
Methods for Image Processing:
The objective for the image processing is to excerpt info
about the location of the vehicle from an image of the
road. This info is then used as comment to produce
steering commands that will keep the vehicle on the
correct track on the road. Two dissimilar methods for the
image processing part have been examined and will be
clarified in detail in this section:
• A straight forward method based on the intensity of
pixels in the captured image. This method includes
computing an intensity profile of the image.
• A method that takes into account the correspondence
among the two-dimensional image plane and the threedimensional real world. The edge detection functions are
used in this method.
The reason for having two diverse methods for the
image processing is that the method was implemented
first due to its simplicity. Though it was later found to be
inadequate and lacking the essential performance for
automated driving and therefore the second method was
instigated. In both methods it is expected that there
exists a visual reference on the road to guide the vehicle.
In this case, the orientation has the form of a continuous
middle marker. This marker has to appear brighter on
the video image than the surrounding road to make it
simply recognizable. It is further assumed that the road
is flat (no hills), has only small arcs and that there are no
difficulties or other moving objects on the road. Note
that image processing for automated driving is not
constrained to a reference in the form of a middle
marker. Additional possible references are markers on
one or both sides of the road or the boundaries of the
road itself. The only norm is that the reference has to be
visually recognizable.
ISSN: Under Process
Typical FPGA architecture that has basic building
blocks
FPGA Design Flow
Below fig shows the FPGA design flow that
comprises subsequent steps: Functional specification of
the system, design entry in hardware description
language Such as VHDL or Verilog, design synthesis,
design implementation (place and route), Device
programming, and lastly in circuit verification. Design
verification, which comprises both functional
verification and timing verification, takes places at
diverse Points during the design flow.
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ISAR - International Journal of Electronics and Communication Ethics - Volume 1 Issue 1, 2016
Five Major Blocks and Memories Block Diagram
Frame Read:
Like all the memories, the output of design will be
an address to this memory an input will be a data. This
data is value of a pixel in definite frame, for the reason
that of FPGA limitations that stated formerly, my each
frame size is 120x160, and there is 100 frame of image
METHODOLOGY
For implementation of Vehicle Speed Detection in external memory, the data in the external memory is
on FPGA, based on studies used some known algorithm one-dimensional, and address 0 is first pixel of first row
for some parts and urbanized some appropriate and first column of first frame. Address 1 is in first
algorithm. There are five key blocks in the design, that frame and first row and second column, and so on.
each do particular task, each of these blocks write Afterwards 160 data, we get to second row data and so
produced data to a memory, and next block uses on. Considerate of data order is vital for reading this
preceding blocks memory to do what it is supposed to do. data from external memory and handling addressing, to
The Fig below displays the five key blocks and guarantee reading correct pixel value.
Memories.
Background:
1. Frame Read, that get raw grayscale image for each The chief purpose of background block is background
frame, and segment the image and write it to segment approximation, as stated earlier, in the design, the
memory.
algorithm used to identify vehicles is association
2. Background, reads segmented data for each frame, by amongst current frame and background.
reading and writing to Pre Background Memory, forms
the background image and write the final background
value to Background Memory.
3. Motion, reads data from segment and background,
relate the 2 sets of data together and write a one bit data,
1 for places motion detected and 0 for places the
segment data were close to background to Motion
Memory.
4. Cars read the Motion Memory and calculate the centre
of mass, write the detected values to Cars Memory.
5. Speed, calculate speed of cars and write it to Speed
Background result after 4 frame
Memory.
ISSN: Under Process
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ISAR - International Journal of Electronics and Communication Ethics - Volume 1 Issue 1, 2016
Background result after 98 frame
Motion Block only writes to this memory, and Cars
block Read and write to it.
Cars Block
In last stage, system detects all the motions in a current
frame, but they are bunch of 1s and 0s. Though, for
computing the speed of vehicles we must group the 1s
together so we have each car 1s group together and
compute the centre of mass for every vehicle so we
know the place of cars.
By processing more frames, the background image have
data that are more meaningful and are more alike to real
background, have less noise and are more appropriate
for associating background to each frame data to detect
motions.
Motion: In this block, we want to associate each frame
with background and detect motions. The block going to
read every address of Segment memory and background
memory, if the change among the values for same
location of image were greater than threshold, block
going to write 1 in Motion Memory for that address. If
the alteration is less than threshold, block going to write
0 in Motion Memory for that address. At the finale, what
we get in Motion Memory is 1 for spaces we have
motions and 0 for places the image is similar as memory.
Cars Block result after 6 frame & Cars Block result after
96 frame
Real colour in frame with a car in upper side of picture
Motion result after 3 frame & Motion result after 96
frame
As you can see by processing additional frames,
the result got improved, for the reason that the
background is getting more dependable. Motion memory
is true dual port ram formed with Block Memory
Generator, it has 1 bit read/write write width, and with
depth of 1200, that creates the address 11 bit. True dual
port RAMs could not be created by distributed RAM.
Consequently, there is a necessity to use Block Memory.
ISSN: Under Process
Speed Memory: Speed memory is distributed Memory
with 8 bit data Width and depth of 256, and 8 bit of
addresses. Speed Block writes the location of cars and
their speed to this memory.
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ISAR - International Journal of Electronics and Communication Ethics - Volume 1 Issue 1, 2016
combining and place and routing the timing report,
become accessible. Timing report shows that all
constraints were met and critical path has 8.967 ns delay
that 1.982ns is logic delay and 6.985ns is routing delay.
Consequently, FPGA chip can be clocked up to
110MHZ.
DISADVANTAGES OF USING FPGA FOR
IMAGE PROCESSING:
Speed result after 4 frame
Speed result after 73 frame
Result: The procedure time going to rise at least 25
There are three chief difficulties with FPGA
1. First is that FPGA do not have any memory of
its individual, it is just a hardware with no
storage capacity, once power is off, FPGA
losses its program. One has to constantly use
certain processing unit to program FPGA.
2. Secondly one cannot use acquainted languages
like C, C++, java, etc to program FPGA, for
programming it, Hardware depiction languages
like VHDL or VERILOG, working with
complex algorithm on HDL is pretty hard.
3. Third is that opencv is dynamic library however
FPGA are only hardware with no memory so we
can’t use OPENCV for image processing, we
have to select other tools like OPENCL or
VIVADO, and these tools are not as effectual as
OPENCV.
times, and it still would be ok, and works real time.
Though, the main disadvantage would be upsurge in
resources vital in FPGA. Still, in FPGAs smaller than
Vertex 7, high resolution image and high accuracy is not
possible, even for simulation. Simulation with low
resolutions video, took at least 1 hour at the end of
CONCLUSION
design, and by high resolution video it’s going to
increase at least 40-50 time (logic going to be bigger too)
In this paper, we have presented the
so without very luxurious apparatus it’s not possible to
speeding
vehicles are Spotted with image
get precise data.
processing techniques using FPGA, its procedure
for computing the speed of a vehicle by numerous
For this design to work real time, based on 4 memories to store data, later how could be
frames per second input video rate, handling each frame performance, timing can be met & could be
must not take more than 25ms. Inspect simulation timing improved were discussed. Lastly drawbacks of
that shown in figure 4.7, shows that 3rd frame starts in using FPGA for image processing were also defined.
Performance:
time 36000 micro second simulation time, and it ends in
46000 micro second simulation times. So processing
each frame takes around 12000 micro second, this is 20
time faster than what was wanted for real time treating
for this resolution and this design can handle at least 20
time progress in image size.
Timing:
Timing analysis is one of the most significant stages of
any digital design, it regulates how fast a clock cycle can
run, and faster clock cycles mean better enactment. For
this design, the 100MHZ was intended for clock speed
so system would be capable to work real time. After
ISSN: Under Process
REFERENCES
1.
ROAD
MODELING
FOR
AUTONOMOUS
2.
Fathy M, Siyal K,‖ Real-time image processing
approach to measure traffic queue parameters ―,
Vision, Image and Signal Processing, IEEE
Proceedings ,Volume:142, Issue 5
VEHICLE by AMARTANSH DUBEY Page No 4-7.
www.internationaljournalisar.org
Page 25
ISAR - International Journal of Electronics and Communication Ethics - Volume 1 Issue 1, 2016
3.
Elamaran.V, Rajkumar G., ―FPGA Implementation
Of Point Processes Using Xilinx System Generator‖,
Journal of Theoretical and Applied Information
Technology, 31st July 2012. Vol. 41 No.2
4.
Fukumoto M., ―Digital R/F Latest Image
Processing Technology and Applications Used in XRay TV Systems‖
5.
Santarelli M.F., Positano V., Landini L. , ―Realtime multimodal medical image processing: a
dynamic volume-rendering application‖ , IEEE Trans
Inf Technol Biomed 1997 Sep;1(3):171-8.
6.
Ohbayashi k., ―Developing the world’s first realtime 3D OCT medical imaging system‖
7.
R. Harinarayan, R. Pannerselvam, M. Mubarak Ali,
and D. Kumar Tripathi, “Feature extraction of Digital
Aerial Images by FPGA based implementation of
edge detection algorithms” IEEE International
Conference on Emerging Trends in Electrical and
Computer Technology (ICETECT), pp.631 – 635,
March 2011.
8.
Ailton F, Mohmad A, Sorel Y,‖ Optimized
implementation of real time image processing
Algorithm on field programmable gate arrays‖.
9.
IMAGE PROCESSING USING FPGA by: Bahram
Pourtaherian, Page No 9-43.
10. Mohmad A, Perroton L, ―Special issuses on parllel
computing for real time image processing,‖
11. Caprani C. C. , Obrien E.J.‖The Governing Form Of
Traffic For Highway Bridge Loading‖
12. Koutsia A., Semertzidi T., Dimitropoulos K.,
Grammalidis N. ―Intelligent Traffic Monitoring
And Surveillance With Multiple Cameras‖, ContentBased Multimedia Indexing, 2008. CBMI 2008, 1820 June 2008
13. Fathy M, Siyal K,‖ Real-time image processing
approach to measure traffic queue parameters ―,
Vision, Image and Signal Processing, IEEE
Proceedings ,Volume:142, Issue 5
14. Amina A. Dawood, Balasim A. Hussean‖ Motion
Detection in Real-Time Video Streams Using Moved
Frame Background
ISSN: Under Process
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