HV739DB1 HV739 ±100V 3.0A Ultrasound Pulser Demo Board Introduction Designing a Pulser with the HV739 The HV739 is a monolithic single channel, high-speed, high voltage, ultrasound transmitter pulser. This integrated, high performance circuit is in a single, 5x5mm, 32-lead QFN package. This demo board data sheet describes how to use the HV739DB1 to generate the basic high voltage pulse waveform as an ultrasound transmitting pulser. The HV739 can deliver up to a ±3.0A source and sink current to a capacitive transducer. It is designed for the ultrasound material inspection NDT and medical ultrasound imaging applications. It can also be used as a high voltage driver for other piezoelectric or capacitive MEMS transducers, or for ATE systems and pulse signal generators as a signal source. HV739’s circuitry consists of controller logic circuits, level translators, gate driving buffers and a high current and high voltage MOSFET output stage. The output stages of each channel are designed to provide peak output currents over ±3.0A for pulsing, with up to ±100 volt swings. Two floating 12VDC power supplies referenced to VPP and VNN supply the P- and N-type power FET gate drivers. The upper limit frequency of the pulser waveform is 35MHz depending on the load capacitance. The HV739 can also be used as a damping circuit to generate fast return-to-zero waveforms by working with another HV739 as a pulsing circuit. It also has built-in under-voltage and over-temperature protection functions. The HV739 circuit uses the DC coupling method in all level translators. There are no external coupling capacitors needed. The VPP and VNN rail voltages can be changed rather quickly, compared to a high voltage capacitor gate-coupled driving pulser. This direct coupling topology of the gate drivers not only saves two high voltage capacitors per channel, but also makes the PCB layout easier. The input stage of the HV739 has high-speed level translators that are able to operate with logic signals of 1.8 to 5.0V volts and are optimized at 3.3 to 5.0V. In this demo board, the control logic signals are connected to a high-speed ribbon cable connector. The control signal logic-high voltage should be the same as the VCC voltage of the demo board, and the logic-low should be reference to GND. The HV739DB1 output waveforms can be displayed using an oscilloscope directly by connecting the scope probe to the test point HVOUT and GND. The soldering jumper can select whether or not to connect the on-board equivalent-load, a 330pF, 200V capacitor, parallel with a 2.5kΩ, 1W resistor. A coaxial cable can be used to connect the user’s transducer to easily drive and evaluate the HV739 transmitter pulser. Application Circuit +3.3V +12V VLL +100V (VPP-12V) 0 to +100V VSUB VDD VPP VPF VCC OTP RGND EN Logic Control Level Translator PIN1 P-Driver TXP NIN1 HVOUT HV739 GREF Level Translator TXN N-Driver GND RGND VNF VSS VNN GND (VNN+ 12V) 0 to -100V HV739DB1 The PCB Layout Techniques Testing the Integrated Pulser The large thermal pad at the bottom of the HV739 package is connected to the VSUB pins to ensure that it always has the highest potential of the chip, in any condition. VSUB is the connection of the IC’s substrate. PCB designers need to pay attention to the connecting traces as the output high-voltage and high-speed traces. In particular, low capacitance to the ground plane and more trace spacing need to be applied in this situation. The HV739 pulser demo board should be powered up with multiple lab DC power supplies with current limiting functions. The following power supply voltages and current limits have been used in the testing: VPP= 0 to +100V 10mA, VNN= 0 to -100V 10mA, VDD= +12V 20mA, (VPP-VPF) = +12V 20mA, (VNF-VNN) = +12V 20mA. VCC= +3.3V 5.0mA for HV739 VLL, not including the user’s logic circuits. The power-up or down sequences of the voltage supply ensure that the HV739 chip substrate VSUB is always at the highest potential of all the voltages supplied to the IC. High-speed PCB trace design practices that are compatible with about 50 to 100MHz operating speeds are used for the demo board PCB layout. The internal circuitry of the HV739 can operate at quite a high frequency, with the primary speed limitation being load capacitance. Because of this high speed and the high transient currents that result when driving capacitive loads, the supply voltage bypass capacitors and the driver to the FET’s gate-coupling capacitors should be as close to the pins as possible. The VSS pin pads should have low inductance feed-through connections that are connected directly to a solid ground plane. The VDD, VPP, VPF, VNF and VNN supplies can draw fast transient currents of up to ±3.0A, so they should be provided with a low-impedance bypass capacitor at the chip’s pins. A ceramic capacitor of up to 0.22 to 1.0µF may be used. Minimize the trace length to the ground plane, and insert a ferrite bead in the power supply lead to the capacitor to prevent resonance in the power supply lines. For applications that are sensitive to jitter and noise, and for using multiple HV739 ICs, insert another ferrite bead between VDD and decouple each chip supply separately. The (VPP–VPF) and (VNF–VNN) are the two floating power supplies. They are only 12V, but floating with VPP and VNN. The floating voltages can be trimmed within the range of +8.0~+12V to adjust the rising and falling time of the output pulses for the best HD2. Do not exceed the maximum voltage of +12V. The VPP and VNN are the positive and negative high voltages. They can be varied from 0 to +/-100V maximum. Note when the VPP= VNN= 0, the VPF and VNF in respect to the ground voltage is –12V and +12V. The on-board dummy load 330pF//2.5kΩ should be connected to the high voltage pulser output through the solder jumper when using an oscilloscope’s high impedance probe to meet the typical loading condition. To evaluate different loading conditions, one may change the values of RC within the current and power limit of the device. In order to drive the user’s piezo transducers with a cable, one should match the output load impendence properly to avoid cable and transducer reflections. A 50Ω coaxial cable is recommended. The coaxial cable end should be soldered to the HVOUT and GND directly with very short leads. If a user’s load is being used, the on-board dummy load should be disconnected by cutting the small shorting copper trace in between the zero ohm resistors R7, R8, R9 or R10 pads. They are shorted by factory default. Pay particular attention to minimizing trace lengths and using sufficient trace width to reduce inductance. Surface mount components are highly recommended. Since the output impedance of HV739’s high voltage power stages is very low, in some cases it may be desirable to add a small value resistor in series with the output to obtain better waveform integrity at the load terminals. This will, of course, reduce the output voltage slew rate at the terminals of a capacitive load. Be aware of the parasitic coupling from the outputs to the input signal terminals of HV739. This feedback may cause oscillations or spurious waveform shapes on the edges of signal transitions. Since the input operates with signals down to 1.8V, even small coupling voltages may cause problems. Use of a solid ground plane and good power and signal layout practices will prevent this problem. Also ensure that the circulating ground return current from a capacitive load cannot react with common inductance to create noise voltages in the input logic circuitry. All the on-board test points are designed to work with the high impedance probe of the oscilloscope. Some probes may have limited input voltage. When using the probe on these high voltage test-points, make sure that VPP/VNN voltages do not exceed the probe limit. Using the high impendence oscilloscope probe for the on-board test points, it is important to have short ground leads to the circuit board ground plane. Precautions need to be applied to not overlap the logic-high time periods of the control signals. Otherwise, permanent damage to the device may occur when cross-conduction or shoot-through currents exceed the device’s maximum limits. 2 HV739DB1 HV739DB1 Schematic VCC VDD VSUB VPF VPP TP1 TP2 TP12 TP3 C2 D1 DFLT13A 2 1 C3 0.22 C5 0.22 1.0 4 29 28 27 VP P VP P VP P TXP TXP TXP OTP EN U1 HV739 TP7 5 30 VS UB VS UB VS UB VS UB VLL VP F 1 7 EN NIN PIN OTP 2 4 6 8 J3 TP5 PIN 11 TP13 C7 3 2 1 D3 DFLT13A VNF VNN VPP VNN VNF VPF VPP 2 D7 1 D6 R4 1 R5 10 R6 10 R7 10 R8 10 J2 HEADER 8 HV739DB1 PCB 3 TP11 R9 10 C8 1u 100V VSUB VNN B1 10 0-1 3 2 VDD D5 2 4 3 VPP VNN D9B B1 10 0-1 3 D9A BAT54DW-7 D4 6 D8B 1 3 4 6 1 VCC BAT54DW-7 D8A VPP 1 VSUB B1 10 0-1 3 VSUB 1 VPF 2 VNF B1 10 0-1 3 VCC 1 VDD VDD 1 2 3 4 5 6 7 8 2 R13 50 VCC C6 330p 200V TP9 1.0 1 J5 TX R2 0 VNN VNN VNN GREF 8 3 12 13 14 R14 50 R11 50 17 18 19 NIN VNF 2 TP10 TP6 2 TXN TXN TXN VS S 3 1 J4 D2 BAV99 1 3 TP8 6 22 23 24 R10 10 +100V>VSUB>VPP VCC = +3.3V VDD = +12V (VPP - VPF) = +12V (VNF - VNN) = +12V VPP = 0 to +100V VNN = 0 to -100V 3 1 3 5 7 TP4 1 2 VCC 2 VDD R1 1K R12 200 9 16 25 32 1u 100V HEADER 4 X2 C1 1u 100V C4 R3 2.55K 1W J1 HVOUT HV739DB1 Board Voltage Supply Power-Up Sequence 1 VCC +1.2 to 5.0V positive logic supply voltage for HV739 VLL and user logic circuit. 2 VDD +12V positive drive supply voltage 3 VPF and VNF 4 VSUB 5 VPP / VNN 6 Logic Active Floating supply voltages, (VPP- VPF)= +12V and (VNF- VNN) = +12V +100V>VSUB/VPP positive bias voltages 0 to +/-100V positive and negative high voltages Any logic control active high signals Note: The Power-down sequence should be revising as to the power-up sequence above Connector and Test Pin Description Logic Control Signal Input Connector 1 VCC Logic-high reference voltage input, VLL, +1.2 to 5.0V, normally from control circuit. 2 EN 3 GND Logic signal ground, 0V (2). Pulser output enable logic signal input, active high. 4 NIN1 Logic signal input for CH1 negative pulse output, active high. (1) 5 GND Logic signal ground, 0V. 6 PIN1 Logic signal input for CH1 positive pulse output, active high. (1) 7 GND Logic signal ground, 0V. 8 OTP Open drain output of over-temperature protection logic signal, active low. Power Supply Connector Logic-high reference voltage supply, +1.2 to 5.0V current limit 5.0mA (for VLL only). 1 VCC 2 GND 3 VDD +12V positive driver voltage supply with current limit to 10mA. 4 VNN 0 to -100V negative high voltage supply with current limit to 5.0mA 5 VNF Floating voltage supply (VNF-VNN) = +12V with current limit to 10mA. (3) 6 VPF Floating voltage supply (VPP-VPF) = +12V with current limit to 10mA. (3) 7 VPP 0 to +100V positive high voltage supply with current limit to 2.0mA 8 VSUB Chip substrate bias voltage, must be (+100V>VSUB/VPP) with limit to 5.0mA Low voltage power supply ground, 0V Note: (1). Overlap control signals logic-high periods of PIN and NIN may cause the device permanent damage. (2). Due to the speed of logic control signal, every GND wire in the ribbon cable must connect to signal source ground. (3). (VPP-VPF) and (VNF-VNN) floating voltage can be trimmed from +8V to +12V for tr/tf time matching. Do not exceed the maximum +12V. 4 HV739DB1 HV739DB1 Waveforms Figure 1: NIN, PIN and output waveform of 5.0MHz, VLL= 3.3V, VDD= +12V, (VPP-VPF) = +12V, (VNF-VNN) = +12V, VPP/VNN= +/-48V, VSUB= +100V with load of 330pF//2.5K. Figure 2: NIN, PIN and output waveform of 10MHz, VLL= 3.3V, VDD= +12V, (VPP-VPF) = +12V, (VNF-VNN)= +12V, VPP/VNN= +/-48V, VSUB= +100V with load of 330pF//2.5K. 5 HV739DB1 HV739DB1 Waveforms (cont.) Figure 3: NIN, PIN and output waveform of 20MHz, VLL= 3.3V, VDD= +12V, (VPP-VPF)= +12V, (VNF-VNN)= +12V, VPP/VNN= +/-48V, VSUB= +100V with load of 330pF//2.5K. Figure 4: Input to output propagation delay on falling edge is 16.4ns and the tr/tf time are about 10ns/12ns. VLL= 3.3V, VDD= +12V, (VPP-VPF)= +12V, (VNF-VNN)= +12V, VPP/VNN= +/-48V, VSUB= +100V with load of 330pF//2.5K. 6 HV739DB1 HV739DB1 Waveforms (cont.) Figure 5: Input to output propagation delay on rising edge is 18ns and the tr/tf time are about 10ns/12ns. VLL= 3.3V, VDD= +12V, (VPP-VPF)= +12V, (VNF-VNN)= +12V, VPP/VNN= +/-48V, VSUB= +100V with load of 330pF//2.5K. Figure 6: Input to output waveforms of the tr/tf time are about 13ns/13ns at VLL= 3.3V, VDD= +8.5V, (VPP-VPF)= +8.5V, (VNF-VNN)= +8.5V, VPP/VNN= +/-48V, VSUB= +100V with load of 330pF//2.5K. 7 HV739DB1 HV739DB1 Waveforms (cont.) Figure 7: Input to output waveforms of the tr/tf time are about 10ns/12.3ns at VLL= 3.3V, VDD= +12V, (VPP-VPF)= +12V, (VNF-VNN)= +12V, VPP/VNN= +/-48V, VSUB= +100V with load of 330pF//2.5K. NR072007 8