PROFORMA FOR TEACHING STAFF PROFILE 1. Name : K. Babulu 2. Designation : Associate Professor 3. Department Engineering : Electronics & Communication 4. Date of Birth : 1st July 1971 5. Date of Joining JNTU Service : 7th July 2003 6. Residential Address : 7. Phone No. Mobile: 9440780175 Res: 2356075 8. Mail-id : [email protected] 9. Blood Group : AB +ve 10. Qualification : M.Tech., (Ph.D.) 11. Experience : a) Teaching : 11 years b) R & D : 01 years c) Industrial : 02 years 12. Field of specialization : VLSI & Embedded Systems 13. Subjects of interest (teaching) EDC, : VLSI, DSD, ESD, ECA, DICA, 3-18B-6/2, 4th Road Ayodyanagar, Kakinada – 533 001. LICA, MPI. 14. No. of Scholars a) Awarded with Ph.D. : Not applicable b) Working for Ph.D. : --- 15. No. of M.Tech. Projects guided : 25 16. Awards received : --- Office: 2300861 17. Titles of books authored : Nil 18. Membership of Professional bodies : M.I.S.T.E., 19. Member Curriculum development Bodies (such as BOS) : Nil 20. Any other distinctions : Nil 21. No. of Conferences/Workshops : Organized as Coordinator/Chairman (Enclose the list) 03 22. Publications (enclose the list in the given order) I. Journals a) Nationals : Nil b) International : Nil a) Nationals : 08 b) International : 05 a) Refresher courses : 05 b) Orientation courses : Nil c) Conferences : 05 24. R & D Projects : 25. Countries visited on academic activity II. 23. Conferences Course/Conference attended (enclose the list) Nil : Nil LIST OF PUBLICATIONS International Conferences: 1. K.Babulu, Dr.K.Soundara rajan” Design and Implementation of Microcontroller based Data acquisition system circuits by using Multisim”, PICA 2006 at Priyadarshini College of Engineering & Architecture, Nagpur, India during 11-14 July, 2006. 2. K.Babulu, Dr.K.Soundara rajan ”FPGA Implementation of data compression techniques using statistical coding”,ICACS-2007 at Government College of Technology, Coimbatore, India during 10-12 January,2007. 3. K.Babulu, Dr. K.Soundara rajan, S.Ch.Vijaya Bhaskar ”Enhancement of Power PC Features Using FPGA”, iconADELCO 2007 at National Engineering college, Kovilpatti, India during 1-3 February, 2007. 4. K.Babulu, Dr. K.Soundara rajan, V.Hari Krishna”Design and Implementation of 8b/10b Encoder/Decoder for Gigabit Ethernet on FPGA”, iconADELCO 2007 at National Engineering college, Kovilpatti, India during 1-3 February, 2007. 5. K.Babulu, Dr. K.Soundara rajan, “FPGA Implementation of USB Transceiver Macro cell Interface with USB2.0 Specifications “, ICETET-08 at th th G.H.Raisoni college of Engineering, Nagpur , India during 16 -18 July 2008. National Conferences: 1. K.Babulu” Microcontroller based Signal Conditioning circuits using Multisim”, National Seminar on VLSI Design-Trends and Tools, at Department of Electronics, SKD University, Anantapur, India during 19-20 March ,2006. 2. G.Mamatha ,K.Babulu,”Field Programmable Gate Arrays(FPGA)-An overview and future enhancements”,ATEET’06 at Coimbatore College of Engineering and Technology, Coimbatore, India during 6-7 October,2006. 3. K.Babulu, J.Padma “FPGA implementation of FET based Digital Instantaneous Frequency Measurement (DIFM) technique”, NCe-merge’07 at JNTU, College of engineering, Anantapur, India on 23rd June 2007. 4. K.Babulu, M.Prasanth “FPGA implementation of High Level Data Link Controller”, NCe-merge’07 at JNTU, College of engineering, Anantapur, India on 23rd June 2007. 5. K.Babulu, M.Prasanna “Design of Low Power Embedded Processor Using FPGA”, NCe-merge’07 at JNTU, College of engineering, Anantapur, India on 23rd June 2007. 6. K.Babulu, D.Asmitha “Implementation of ReedSolomon Encoding/Decoding and Viterbi Decoding in Remote Sensing Front End Hardware Chain”,NCPP’07 at G.Narayanamma Institute of Technology & Science, Hyderabad, India during 28-29 November,2007. 7. K.Babulu, K.Sujatha “Implementation of PIC Microcontroller based Miss Distance indicator”,NCPP’07 at G. Narayanamma Institute of Technology & Science, Hyderabad, India during 28-29 November,2007. 8. K.Babulu, K.Soundara Rajan, B.Subbarao “Design and Implementation of Digital Time Slot Interchange Switch on FPGA”,National Seminar on VLSI Technology and Embedded Design,VED-2008 at Dhaneswar Rath Institute of Engineering & Management Studies,Cuttack, India during 14-15 March,2008. STTP/ Workshops/ Refresher Courses etc. Attended: Short Term Training Programs (STTP): 1. Attended for STTP on” Digital IC Design” at National Institute of Warangal, India during 27th February-04th march, 2006. Technology, 2. Attended for STTP on” Development of Embedded systems laboratory” at JNTU, College of Engineering, Anantapur, India during 19th February-02nd March 2007. Workshops: 1. Attended Workshop on “VLSI Design” at Gudlavalleru engineering College, Gudlavalleru, India during 09-10 February, 2007. 2. Attended workshop on “Embedded Systems Design with 89C51 Microcontroller”, Wine Yard technologies, Hyderabad on 28th June 2008. Refresher Courses: 1. Attend for Refresher Course on “Analysis of Electrical Circuits” at JNTU, College of Engineering, and Anantapur, India during 29th August -03rd September 2005. STTP/ Workshops / Refresher Courses etc. Conducted Short Term Training Programs (STTP): 1. Conducted STTP as Coordinator on “Mobile Phone Servicing” at JNTU College of Engineering, Kakinada during 12th - 23rd May 2008. Conferences/Symposiums: 1. Conducted national Conference as Coordinator on “Emerging Trends in Electronics & Communication Engineering” (NCemerge-08) at JNTU College of Engineering, Ananthapur on 23rd June 2007. 2. Conducted National level Technical Symposium as Coordinator on “Emerging Trends in Electronics & Communication Engineering” (emerge-08) at JNTU College of Engineering, Anantapur on 8th April 2007.