5. CMOS Inverter
Institute of
Microelectronic
Systems
Overview
• Logic levels
• Noise Margin
• CMOS Inverter
– static behaviour
– dynamic behaviour
Courtesy Quiller Electronics Limited
5: CMOS Inverter
Institute of
Microelectronic
Systems
2
Inverter as simplest logic gate
V+
V
v
+
R
v
I
v
O
O
vI
VO
V DD
VCC
R
i
R
v
D
vI
M
5: CMOS Inverter
O
i
vI
S
v
C
Q
O
VI
S
Institute of
Microelectronic
Systems
3
Logic Voltage Levels
VOL: Nominal voltage
v
corresponding to a low logic
O
state at the output of a logic
V
+
gate for vI = VOH.
V
Slope = -1
OH
Generally V- ≤ VOL.
VOH: Nominal voltage
corresponding to a high logic
state at the output of a logic
gate for vI = VOL.
Generally VOH ≤ V+.
Slope = -1
VIL: Maximum input voltage that
will be recognised as a low
V
OL
input logic level.
NM
NML
H
VIH: Minimum input voltage that will 0
V
V
V
V
be recognised as a high input
V- 0
OL
IL
IH
OH
logic level.
5: CMOS Inverter
Institute of
Microelectronic
Systems
v
I
V+
4
Noise Margins
vI
vO
V+
"1"
NML: Noise margin associated with
a low input level
"1"
V OH
NMH
VIH
NML = VIL - VOL
Undefined
Logic State
NMH: Noise margin associated with
a high input level
V IL
NM L
NMH = VOH - VIH
"0"
VOL
"0"
V-
Institute of
Microelectronic
Systems
5: CMOS Inverter
5
Dynamic Response of Logic Gates
v
I
• Rise time tr: time required for the
transition from V10% to V90%.
• Fall time tf: time required for the
transition from V90% to V10%.
VOH
• Propagation delay τP: difference
in time between the input and
output signals reaching V50%.
V50% = (VOH + VOL)/2
τP =
5: CMOS Inverter
τ PLH + τ PHL
2
V
50%
+V
OH
OL
2
VOL
V10% = VOL + 0.1(VOH - VOL)
V90% = VOL + 0.9(VOH - VOL)
90%
10%
(a)
tr
vO
VOH
tf
τ PHL
t
τ PLH
90%
V
OH
50%
+V
OL
2
10%
VOL
(b)
t 1 t t2
f
t3 t t4 t
r
Switching waveforms for an idealised inverter
(a) Input voltage signal (b) Output voltage waveform
Institute of
Microelectronic
Systems
6
MOS Inverter with Resistive Load
V
DD
• NMOS switching device MS
designed to force vO to VOL
=5V
R
v
• Resistor load R to pull the output
up toward the power supply VDD
i
• VOH = VDD (driver in cut off
⇒ iD = 0)
• VOL determined by W/L ratio of
MS
v
D
+
M
I
O
v
S
DS
-
Institute of
Microelectronic
Systems
5: CMOS Inverter
7
Example
V = 5V
DD
i
V DD= 5V
DD
R
R
v =V
O
95 k Ω
=5V
OH
v =V
O
50 µA
0
M
M
v =V <V
I
OL
TH
I
=5V
v
2.06
1
= 0.25 V
DS
-
OH
(a)
5: CMOS Inverter
+
S
S
v =V
OL
(b)
Institute of
Microelectronic
Systems
8
On - Resistance
V
V
R
R
DD
DD
VOH
VOL
v =V
v = V OL
I
I
OH
R on
R on
(b)
(a)
Ron =
vDS
=
iD
1
K 'n
W
L
VOL = VDD
v ⎞
⎛
⎜ vGS − VTN − DS ⎟
2 ⎠
⎝
Ron
1
= VDD
R
Ron + R
1+
Ron
Institute of
Microelectronic
Systems
5: CMOS Inverter
9
Transistor Alternatives to the Load Resistor
VDD
VDD
ML
+
ML
vO
vI
vO
vI
MS
(a) NMOS inverter with gate of the load
device connected to its source
MS
(b) NMOS inverter with gate
of the load device grounded
V DD
VGG
ML
V DD
ML
vO
vI
MS
(c) Saturated load inverter
5: CMOS Inverter
vO
VI
MS
(d) Linear load inverter
Institute of
Microelectronic
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10
CMOS Inverter Technology
V
SS
(0 V)
B
p+
v
V
DD
I
S
D
n+
vo
D
n+
(5 V)
S
p+
p+
B
n+
n-well
Ohmic
contact
NMOS transistor
PMOS transistor
Ohmic
contact
p-type substrate
C M O S T ra n sisto r P a ra m e te rs
N M O S D e vice
P M O S D e vice
1 V
-1 V
VTO
γ
2 φF
K'
0 .5 0
0 .7 5
V
0 .6 0 V
25
0 .7 0 V
µA /V 2
1 0 µA /V 2
Institute of
Microelectronic
Systems
5: CMOS Inverter
V
11
Complementary MOS (CMOS) Logic Design
• Inverter with resistive
load ⇒ power
dissipation when the
input is high.
• If an NMOS and
PMOS transistor is v
I
used ⇒ CMOS.
• One transistor is
always off while the
other is on ⇒ no
static power
consumption.
5: CMOS Inverter
S
R onp
M
G
P
v
D
I
v
v
D
G
VDD = 5 V
VDD = 5 V
O
O
M
N
S
Institute of
Microelectronic
Systems
R onn
12
CMOS voltage transfer Characteristic
VIL
1
2
M N off M N saturated
M P linear
4.0V
v o = v I - VTP
vo
M
N
and M P saturated
3
2.0V
M P saturated
M N linear
v o= v I - VTN
0V
VIH
4
0V
1.0V
2.0V v
I
5
M P off
3.0V
4.0V
5.0V
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Microelectronic
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5: CMOS Inverter
13
Regions of Operation of Transistors in a
Symmetrical Inverter
Region
Input Voltage vI
Output
Voltage vO
NMOS
Transistor
PMOS
Transistor
1
vI ≤ VTN
VOH = VDD
Cutoff
Linear
2
VTN < vI ≤ vO + VTP
High
Saturation
Linear
3
vI ≈ VDD/2
VDD/2
Saturation
Saturation
4
vO + VTN < vI ≤ (VDD + VTP)
Low
Linear
Saturation
5
vI ≥ (VDD + VTP)
VOL = 0
Linear
Cutoff
5: CMOS Inverter
Institute of
Microelectronic
Systems
14
What happens, if the inverter is not
symmetrical?
6.0V
6.0V
VDD = 5 V
vO= vI
VDD = 4 V
4.0V
VDD = 3 V
v O= vI
VDD = 2 V
2.0V
KR= 5
4.0V
K R= 1
2.0V
K R = 0.2
0V
0V
0V
1.0V
2.0V
3.0V
vI
4.0V
5.0V 6.0V
Symmetrical inverter (Kn = Kp)
0V
1.0V
2.0V
vI
3.0V
5.0V
Asymmetrical inverter (KR = Kn / Kp)
Institute of
Microelectronic
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5: CMOS Inverter
4.0V
15
Calculation of VIL
Equating currents for saturated nMOS and nonsaturated pMOS device
(Region 2):
[
K
Kn
(Vin − VTn )2 = p 2(VDD − Vin − VTp )(VDD − Vout ) − (VDD − Vout )2
2
2
The derivation condition (dVout / dVin) = -1 has to be evaluated for
IDn(Vin) = IDp(Vin , Vout):
dVout (dI Dn / dVin ) − (∂I Dp / ∂Vin )
=
= −1
dVin
∂I Dp / ∂Vout
Evaluating the derivation gives:
⎛ K ⎞
K
VIL ⎜⎜1 + n ⎟⎟ = 2Vout + n VTn − VDD − VTp
Kp
⎝ Kp ⎠
This equation has to be solved together with the first equation ⇒ VIL
5: CMOS Inverter
Institute of
Microelectronic
Systems
16
]
Calculation of VIH
At the point VIH the NMOS device is nonsaturated and the PMOS
transistor is saturated (region 4):
K
2
Kn
2
[
]
= p (VDD − VIH − VTp )
2(VIH − VTn )Vout − Vout
2
2
The derivation condition (dVout / dVin) = -1 has to be evaluated for
IDn(Vin, Vout) = IDp(Vin):
dVout (dI Dp / dVin ) − (∂I Dn / ∂Vin )
=
= −1
∂I Dn / ∂Vout
dVin
which gives:
K
⎛ K ⎞
VIH ⎜⎜1 + p ⎟⎟ = 2Vout + VTn + p (VDD − VTp )
Kn
⎝ Kn ⎠
This equation forms together with the first equation a quadratic in VIH
which has to be solved.
Institute of
Microelectronic
Systems
5: CMOS Inverter
17
Calculation of Vth
For Vth = Vin = Vout both transistors are
saturated (λ is assumed to be 0):
4.0V
Kp
2
Kn
2
(Vth − VTn ) = (VDD − Vth − VTp )
2
2
vo
Solving for Vth yields:
Vth =
VTn + K p / K n (VDD − VTp )
1+ K p / Kn
V IL
1
Vin=Vout
2
2.0V
M N and M P saturated
3
VIH
0V
4
0V
1.0V
2.0V
5
3.0V
4.0V 5.0V
vI
Vth
5: CMOS Inverter
Institute of
Microelectronic
Systems
18
Design of CMOS inverter (I)
• KR = Kp / Kn
⎛W ⎞
• Remember: K n = K 'n ⎜ ⎟
⎝ L ⎠n
⎛W ⎞
K p = K'p ⎜ ⎟
⎝ L ⎠p
⇒Influence of the symmetry via
W/L of transistors!
4.0
Noise Margin (Volts)
• NMH = VOH - VIH = VDD - VIH
• NML = VIL - VOL = VIL - 0 = VIL
3.5
3.0
NM
2.5
2.0
1.5
NM L
1.0
0.5
0
1
2
3
4
5 6
KR
7
8
Institute of
Microelectronic
Systems
5: CMOS Inverter
H
9 10 11
19
Design of CMOS inverter (II)
The ratio (W/L) in CMOS design is
used to set the level of Vth.
Kp
Kn
=
µ p (W L ) p
µn (W L )n
The ratio required to establish a
given inverter threshold voltage is:
K n VDD − Vth − VTp
=
Kp
Vth − VTn
To get a symmetrical voltage
transfer curve, Vth is set to VDD/2:
K n 12 VDD − VTp
= 1
K p 2 VDD − VTn
If in a process |VTp| = VTn, the
device aspect ratios for a
symmetrical inverter are related by:
(W L ) p µn
=
(W L )n µ p
Since µn / µp ≈ 2.5, a minimum area CMOS inverter will have (W/L)n ≈ 1 and
(W/L)p ≈ 2.5. In this case the voltage transfer function is completely symmetric.
5: CMOS Inverter
Institute of
Microelectronic
Systems
20
Summary
So what did we accomplish until
now?
V IL
1
4.0V
2
vo
2.0V
3
VIH
0V
4
0V
1.0V
2.0V
5
3.0V
4.0V 5.0V
• We know how a CMOS inverter
works.
• VOL, VOH - do you still know it?
• We know how to set the W/L ratios
of the transistors to get optimal
noise margins.
• So we make every inverter the
same, that is to say minimal -or?
vI
Institute of
Microelectronic
Systems
5: CMOS Inverter
21
Dynamic Behavior of the CMOS Inverter
High to Low Output Transition (I)
MN goes from Cutoff over Saturation into Nonsaturation region for the given
input.
The border between Saturation and Nonsaturation is reached at the time tx
and the output voltage Vout = VOH - VTn
v
I
+ 5V
V DD = 5 V
MP
v I = 5V
0V
t
v O (0+) = 5V
MN
C
0
v
O
MN saturated
VOH = 5V
MN nonsaturated
(Vin - VTn)
VOL = 0 V
t
t1
5: CMOS Inverter
Institute of
Microelectronic
Systems
tX
t2
22
High to Low Output Transition (II)
In order to simplify the final expressions, the
integrations on the right for computing tHL are
done with the borders from VDD to V0
(V1 = 0,9 VDD, V0 = 0,1 VDD)
Saturation:
t x − t1 = −COUT
VDD −VTn
∫
VDD
dVOUT
Kn
(VDD − VTn )2
2
=
dV
dQ
= COUT OUT
dt
dt
dV
∫ dt = COUT ∫ iOUT
i=
2CoutVTn
2
K n (VDD − VTn )
Nonsaturation:
V0
t 2 − t x = −COUT
∫
[
dVOUT
Kn
2
2(VDD − VTn )VOUT − VOUT
2
⎛ 2(VDD − VTn ) ⎞
COUT
ln⎜⎜
=
− 1⎟⎟
K n (VDD − VTn ) ⎝
V0
⎠
VDD −VTn
]
⎛
2C
VOUT
1
ln⎜⎜
= − OUT
K n 2(VDD − VTn ) ⎝ 2(VDD − VTh ) − VOUT
Institute of
Microelectronic
Systems
5: CMOS Inverter
23
High to Low Output Transition (III)
We have used the following integral:
In our case:
n = 1, b = −1
dx
1 ⎛ xn ⎞
∫ x a + bx n = an ln⎜⎜⎝ a + bx n ⎟⎟⎠
(
dx
∫ ax − x
2
=
)
1 ⎛ x ⎞
ln⎜
⎟
a ⎝a−x⎠
t HL = (t x − t1 ) + (t 2 − t x )
therefore:
⎡ 2VTn
⎛ 2(VDD − VTn ) ⎞⎤
t HL = τ ⎢
+ ln⎜⎜
− 1⎟⎟⎥
−
V
V
V
0
⎠⎦
⎝
⎣ DD Tn
where
5: CMOS Inverter
τ=
COUT
K n (VDD − VTn )
Institute of
Microelectronic
Systems
V0
⎞
⎟⎟
=
⎠ VDD −VTn
24
Low to high output transition
From symmetry (VTn → VTp; Kn → Kp) follows for the high to low transition
time:
⎡ 2 VTp
⎞⎤
⎛ 2 VDD − VTp
COUT
⎢
⇒ t LH =
+ ln⎜
− 1⎟⎥
⎟⎥
⎜
V0
K p VDD − VTp ⎢VDD − VTp
⎠⎦
⎝
⎣
(
V
DD
(
)
)
=5V
v
I
+ 5V
MP
t
0V
V =0V
I
v
M
O
(0+) = 0V
C
N
0
v
O
+ 5V
0V
t
0
Institute of
Microelectronic
Systems
5: CMOS Inverter
25
Dynamic Behavior of the CMOS Inverter
(cont’d)
• The choice of size of the NMOS and PMOS transistors can be dictated by the
desired average propagation delay τP
• For symmetrical inverter:
τP =
t PHL + t PLH
= t PHL = t PLH
2
Kn' ≈ 2.5 K p'
tr = t f = 2τ P
Example:
VDD= 5 V
V DD= 5 V
M
P
v
5
1
M
P
v
o
I
M
N
2
1
V DD= 5 V
v
32.5
1
M
P
v
I
C
M
N
v
o
v
I
13
1
M
1 pF
(a)
Symmetrical reference inverter
| VTP | = VTN = 1V τP = 6.4 ns
C = 1 pF
tr = tf = 12.8 ns
5: CMOS Inverter
20
1
N
o
8
1
2 pF
(b)
Scaled inverters
a) τP = 1 ns
Institute of
Microelectronic
Systems
b) τP = 3.2 ns
26
Power Dissipation
6.0V
• Two kinds of power
dissipation in digital
electronics:
– static power dissipation
(logic gate output is
stable)
– dynamic power
dissipation (during
switching of logic gate)
Output Voltage
40uA
4.0V
20uA
2.0V
Drain Current
• With CMOS nearly no static
power dissipation!
0V
0A >>
0V
2.0V
4.0V
vI
6.0V
Institute of
Microelectronic
Systems
5: CMOS Inverter
27
Dynamic Power Dissipation (I)
R1
Power dissipation due to charge and
i(t)
discharge of capacitances
+
The total energy ED delivered by the V
DD
source is given by
∞
ED = ∫ P(t )dt
Switch closes at t = 0
Non-linear
Resistor
+
C
vc (t)
(a)
-
vc (0) = 0
0
The power P(t) = VDDi(t), and because
VDD is a constant,
∞
∞
0
0
ED = ∫ VDD i (t )dt = VDD ∫ i (t )dt
The current supplied by source VDD is
also equal to the current in capacitor C,
and so
∞
dv
ED = VDD ∫ C
0
C
dt
VC ( ∞ )
= CVDD ∫
VC ( 0 )
5: CMOS Inverter
Institute of
Microelectronic
Systems
dt
dvC
28
Dynamic Power Dissipation (II)
Integrating from t = 0 to t = ∞, with
VC(0) = 0 and VC (∞) = VDD results in
2
ED = CVDD
We know that the energy Es stored in
capacitor C is given by
2
CVDD
ES =
2
The total energy ETD dissipated in
the process of first charging and
then discharging the capacitor is
equal to
ETD
2
2
⎛ CVDD
⎞
⎛ CVDD
⎞
⎟⎟
⎟⎟
+ ⎜⎜
= ⎜⎜
2
2
⎠ Discharge
⎝
⎠Charge ⎝
2
= CVDD
and thus the energy EL lost in the
resistive element must be
2
CVDD
EL = ED − ES =
2
5: CMOS Inverter
Institute of
Microelectronic
Systems
29
Dynamic Power Dissipation (III)
Thus, every time a logic gate goes through a complete switching cycle, the
transistors within the gate dissipate an energy equal to ETD. Logic gates
normally switch states at some relatively high frequency (switching
events/second), and the dynamic power PD dissipated by the logic gate is
then
2
PD = CVDD
f
In effect, an average current equal to (CVDDf) is supplied from the source
VDD.
5: CMOS Inverter
Institute of
Microelectronic
Systems
30
Dynamic Power Dissipation (IV)
• Power dissipation due to the “short circuit current” (when both transistors
are on during transition)
• The short circuit current reaches a peak for Vin = Vout = VDD/2
Voltage
5.0 V
VDD = 5 V
vO
Vin = Vout = VDD/2
0.0 V
R onp
vI
vout
30uA
Current
i DD
R onn
0 uA
0s
4ns
8ns
12ns
16ns
Time
Institute of
Microelectronic
Systems
5: CMOS Inverter
31
Summary
Let’s repeat:
6.0V
40uA
• What is the dynamic behaviour of
the inverter?
• What do we need it for?
• What kind of power dissipation is
there?
• What kind of power dissipation is
dominant with CMOS logic?
Output Voltage
4.0V
20uA
2.0V
Drain Current
0V 0A >>
0V
2.0V v
I
4.0V
6.0V
2
PD = CVDD
f
5: CMOS Inverter
Institute of
Microelectronic
Systems
32