EECS 141 - S02
Lecture 23
Dealing with
Interconnect
Digital Integrated Circuits
Interconnect
© Prentice Hall 2000
Today’s Lecture
Capacitive parasitic effects
l Resistive interconnect
l
Digital Integrated Circuits
Interconnect
© Prentice Hall 2000
1
COPING WITH
INTERCONNECT
Digital Integrated Circuits
Interconnect
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Impact of Interconnect Parasitics
• Reduce Reliability
• Affect Performance
Classes of Parasitics
• Capacitive
• Resistive
• Inductive
Digital Integrated Circuits
Interconnect
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2
INTERCONNECT
Dealing with Capacitance
Digital Integrated Circuits
Interconnect
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Capacitive Crosstalk
Dynamic Node
V DD
CLK
In1
In2
In3
C XY
Y
CY
X
PDN
2.5 V
0V
CLK
3 x 1 µm overlap: 0.19 V disturbance
Digital Integrated Circuits
Interconnect
© Prentice Hall 2000
3
Capacitive Crosstalk
Driven Node
0.5
0.45
0.4
RY
C XY
VX
Y
CY
τXY = RY(CXY+CY)
0.35
V (Volt)
X
0.3
tr
0.25
0.2
0.15
0.1
0.05
0
0
0.2
0.4
0.6
t(sec)
0.8
1
-9
x 10
Keep time-constant smaller than rise time
Digital Integrated Circuits
Interconnect
© Prentice Hall 2000
Delay Degradation
- Impact of neighboring signal
activity on switching delay
Cc
- When neighboring lines switch
in opposite direction of victim
line, delay increases
Miller Effect
- Both terminals of capacitor are switched in opposite directions
(0 → Vdd, Vdd → 0)
- Effective voltage is doubled and additional charge is needed
(from Q=CV)
Digital Integrated Circuits
Interconnect
© Prentice Hall 2000
4
Interconnect Projections
Low-k dielectrics
l
l
l
Both delay and power are reduced by dropping interconnect
capacitance
Types of low-k materials include: inorganic (SiO2), organic
(Polyimides) and aerogels (ultra low-k)
The numbers below are on the
conservative side of the NRTS roadmap
Generation
Dielectric
Constant
0.25
µm
3.3
Digital Integrated Circuits
0.18
µm
2.7
0.13
µm
2.3
0.1
µm
2.0
Interconnect
0.07
µm
1.8
ε
0.05
µm
1.5
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How to Battle Capacitive
Crosstalk
Shielding
wire
l
GND
l
VDD
Shielding l
layer
l
GND
l
l
Avoid large crosstalk cap’s
Avoid floating nodes
Isolate sensitive nodes
Control rise/fall times
Shield!
Differential signalling
Substrate (GND)
Digital Integrated Circuits
Interconnect
© Prentice Hall 2000
5
Structured and Predictable Interconnect
V
S G S V S
S
G
S
V
S
V
Example: Dense Wire Fabric (DWF) [Khatri, DAC99]
Trade-off:
• Cross-coupling capacitance 40x lower, 2% delay variation
• Increase in area and overall capacitance
Digital Integrated Circuits
Interconnect
© Prentice Hall 2000
Driving Large Capacitances
tpHL = CL Vswing/2
Iav
VD D
Vin
Vout
CL
Digital Integrated Circuits
Interconnect
Transistor
Sizing
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6
Using Cascaded Buffers
In
Out
1
2
0.25 µm process
Cin = 2.5 fF
tp0 = 30 ps
Digital Integrated Circuits
CL = 20 pF
N
F = CL/Cin = 8000
fopt = 3.6 N = 7
tp = 0.76 ns
Interconnect
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Output Driver Design
l
Trade off Performance for Area and Energy
» Given tpmax find N and f
l
Area
(
Adriver = 1 + f + f 2 + ... + f
l
N −1
)A
−1
F −1
Amin =
Amin
f −1
f −1
=
f
2
i DD
=
min
N
Energy
(
E driver = 1 + f + f 2 + ... + f
Digital Integrated Circuits
N −1
)C V
Interconnect
F −1
C
2
2
CiVDD
≈ L VDD
f −1
f −1
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7
Output Driver Design
0.25 µm process, CL = 20 pF
Transistor Sizes for optimally-sized cascaded buffer t = 0.76 ns
Transistor Sizes of redesigned cascaded buffer tp = 1.8 ns
Digital Integrated Circuits
Interconnect
© Prentice Hall 2000
How to Design Large Transistors
D(rain)
S
Multiple
Contacts
D
G
S(ource)
S
G(ate)
(a) small transistors in parallel
Digital Integrated Circuits
Interconnect
(b) circular transistors
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8
Bonding Pad Design
Bonding Pad
GND
100 µm
Out
VDD
In
Digital Integrated Circuits
GND
Out
Interconnect
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Reducing the swing
tpHL = CL Vswing /2
Iav
• Reducing
the swing potentially yields linear
reduction in delay
• Also results in reduction in power dissipation
• Requires use of “sense amplifier” to restore signal level
Digital Integrated Circuits
Interconnect
© Prentice Hall 2000
9
Charge Redistribution Amplifier
5.0
Vref
VA
4.0
VB
M1
M3
3.0
CB
CA
V
M2
VB
Vin
VA
2.0
1.0
(a)
Vref = 3V
0.0
0.0
Digital Integrated Circuits
1.00
2.00
time (nsec)
Interconnect
3.00
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Precharged Bus
VDD
f
In1.f
VD D
M2
M4
Bus
M1
In2.f
Cbus
Out
M3
Cout
f
5.0
Vsym
V
3.0
Vasym
Vbus
1.0
C bus =1pF
-1.0
Digital Integrated Circuits
0
5
t (nsec)
Interconnect
10
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10
Tristate Buffers
VDD
VDD
En
En
Out
Out
In
En
Digital Integrated Circuits
In
Interconnect
En
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11