MD3880DB1
MD3880DB1:
Ultrasound Low Noise Amplifier Demoboard
General Description
The MD3880DB1 demoboard is a platform for testing and
evaluating the MD3880 4-channel low-noise amplifier (LNA)
with a variable gain amplifier (VGA). There are three 2.5V input supplies so that it can test each supply’s performance individually. The input supplies are: LNA power supply (AVDD);
control interface power supply (AVDD_CNTRL); and VGA
power supply (AVDD_AMP).
The MD3880DB1 schematic is shown on the following page.
The input impedance of the LNA is configured for 50Ω, to
match the output impedances of the equipment. This input
impedance can be changed according to the datasheet. Ferrite beads and capacitors are installed at the LNA for filtering the high frequency components for a more stable operation. All channel outputs are connected to resistor dividers
in order to have approximately 250Ω loading to ground and
50Ω impedance matching for measurement purposes. In addition, for measurement simplicity, a transformer with a 1:1
turns ratio is needed to convert the differential outputs to
single-ended output. Note that there is -19.8dB attenuation
from the divider, which needs to be taken into account when
using these outputs. Different loads can also be connected
via the SMA connectors for direct measuring if the two 28Ω
resistors are removed. In this condition, the VGA output is in
series with 237Ω resistors only and the output impedance
becomes higher. Therefore, one needs to compensate for
the attenuation if low impedances are connected to the output SMA when performing direct measurement.
The A0 and A1 pins are reversed and connected to VDD. PG0
and PG1 are used for setting the VGA gain. Each gain step
is approximately 5.5dB. GSC is the reference voltage of the
Voltage Control Attenuator (VCA) for programming the slope
of the linear-in-dB curve. TGC is to vary the VCA gain from
0dB to -47dB. PDC is to power down the MD3880 or to adjust the current consumption. The EBC pin is connected to
a known value resistor or variable resistor for programming
the current consumption.
Connections
Name
Signals
Voltage
AVDD
AVDD
+2.5V
AVDD_AMP
VDD
+2.5V
AVDD_CNTRL
VDD
+2.5V
GND
GND
0V
AGND
AGND
0V
TGC
TGC
0 to +2.0V
EBC
EBC
10k VR to GND
PDC
PDC
Hi / Lo
A0
A0
Reserved, +2.5V
A1
A1
Reserved, +2.5V
PG0
PG0
Hi / Lo
PG1
PG1
Hi / Lo
GSC
GSC
2.5V / External
INPUT_A~D
INPUT
+/-210mVP-P
OUTPUT_A~D
OUTPUT
w/ -19.5dB atten.
Actual Dimensions: 105mm x 113mm
MD3880DB1
Demo Board Schematic
2
MD3880DB1
MD3880 Performance Test Report
1. Electrical Parameters Measurement
All typical values are under the following conditions, unless otherwise noted: TA= + 25°C, VDD = 2.5V, Load resistance =
500Ω across the differential outputs, CLOAD = 1pF, fIN = 10MHz, PG0 = 0V, PG1 = 0V, PDC = 0, VGSC = 2.5V, VCM = 1.25V,
amp gain = 18.5dB, single-ended input: RS = RIN = 50Ω. RIN is formed by active termination with RFB = 237Ω and CFB, differential signal output, VIN is the voltage at the non-inverting node of the amplifier.
1.1. Low Noise Amplifier
Sym
Parameter
Specification
Min
TEST
Max
Units
Notes
GLNA
Pre-amplifier gain
-
18.5
-
dB
---
RIN
Input resistance
-
560
-
kΩ
Without active termination
CIN
Input capacitance
-
17.5
-
pF
Without active termination
IBIAS
Input bias current
-
1
-
nA
From ESD leakage
Com. mode rejection ratio
-
-65
-
dB
PG0 = PG1 = VDD, VTGC = 2.0V, f = 1MHz
Input voltage
-
±210
-
mV
---
VIN-NOISE
Input voltage noise, 5MHz
-
0.74
-
nV/√Hz
Without active termination
IIN-NOISE
Input current noise
-
0.35
-
pA/√Hz
Without active termination
-
2.3
-
dB
f = 5.0MHz, without active termination
RS = RIN = 50Ω, f = 5.0MHz with active
termination
CMRR
VIN
NF
Noise figure
BW
Bandwidth
-
3.7
-
dB
-
105
-
MHz
Small signal bandwidth
Units
Notes
1.2. Overall Channels
Sym
Parameter
Gain
Specification
Min
TEST
Max
Whole channel gain
-
70
-
dB
Without active termination, max. gain
BWVGA
-3dB bandwidth
-
60
-
MHz
Small signal bandwidth at max. gain
SRVGA
Slew rate
-
500
-
V/µs
---
VOVGA
Output signal range
-
4.1
-
VPP
RL > 1.0kΩ differentially
ROUT
Output impedance
IOUTS
Output short-circuit current
VIN-NOISE
IMD
HD3
HD2
-
3.1
-
Ω
-37
-
+45
mA
Input voltage noise
-
0.8
-
nV/√Hz
Intermodulation distortion,
two-tone
-
-76
-
dB
1MHz , VOUT = 1.0VPP, 30dB gain
-
-70
-
dB
10MHz , VOUT = 1.0VPP, 30dB gain
-
-73
-
dB
VOUT = 1.0VPP, 1MHz, 30dB gain
-
-69
-
dB
VOUT = 1.0VPP, 10MHz, 30dB gain
-
-55
-
dB
VOUT = 1.0VPP, 1MHz, 10dB gain
-
-47
-
dB
VOUT = 1.0VPP, 10MHz, 10dB gain
-
-87
-
dB
VOUT = 1.0VPP, 1MHz, 30dB gain
-
-70
-
dB
VOUT = 1.0VPP, 10MHz, 30dB gain
-
-53
-
dB
VOUT = 1.0VPP, 1MHz, 10dB gain
-
-51
-
dB
VOUT = 1.0VPP, 10MHz, 10dB gain
Third harmonic distortion
Second harmonic distortion
3
f = 5.0MHz, single ended
--At Max. gain and 5MHz
MD3880DB1
1.2. Overall Channels (cont.)
Sym
Parameter
Specification
Min
TEST
Max
Units
Notes
AOUT1dB
1dB compression point
-
-1.3
-
dBm
VOUT = 1.0VPP, f = 10MHz, 8dB gain
CSTK
Crosstalk
-
-78
-
dB
PG0 = PG1 = 1, 30dB gain, 1MHz,
1.0VPP at adjacent channel
Δtgd
Group delay variation
-
±2
-
ns
2 MHz < f < 50 MHz, full gain range
tOLR
Overload recovery time
-
5
-
ns
8dB gain, VIN = 50mVPP to 1VPP change,
f = 10MHz
VDC-OUT
DC output Level, VIN = 0
-
1.26
-
V
---
Note: VIN is the voltage at the non-inverting node of the amplifier.
1.3. Accuracy
Sym
Parameter
GSLOPE
Specification
Min
TEST
Max
Units
Notes
Gain slope
-
32.5
-
dB/V
GMAT
Ch. to ch. gain matching
-
±0.1
-
dB
VTGC = 0V or 2.0V
VGSC = 2.5V
EGAIN
Gain error
-
±0.8
-
dB
Referenced to best fit dB-linear curve
VGSC
Slope control voltage
2
-
2.5
V
---
VOS-OUT
Output offset voltage
-
±20
-
mV
Reference to 1.250V
1.4. Gain Control Interface
Sym
Parameter
VTGC
Gain control voltage
VGSC
Gain slope voltage
RGSC
Input resistance of GSC
ITGC
Input current of VTGC
IGSC
tdTGC
Specification
Units
Notes
Min
TEST
Max
0
-
2
V
Linear in dB, see Gain Scaling Diagram
2.0
2.5
2.5
V
About 41dB/V at 2.0V and 33dB/V at
2.5V
-
110
-
kΩ
---
-
1.25
-
µA
VTGC = 2V
Input current of VGSC
-
23
-
µA
VGSC = 2.5V
Response time
-
0.15
-
µs
95% full gain change
1.5. Power Supply
Sym
Parameter
Specification
Min
TEST
Max
Units
Notes
VDD
Power supply
-
2.5
-
V
IDDQ
VDD supply current PDC = 1
-
-
45
mA
Power down status, total of all channels
IDD
VDD supply current
-
75
-
mA
Per channel
PWR
Power dissipation
-
700
-
mW
Total of all channels
-
175
-
mW
Per channel
4
TA = -40 to +85°C
MD3880DB1
tion. The gain control pin draws very small current. 0 to 95%
gain transient response time is about 150ns.
2. Measuring the MD3880
2.1. Low Noise Amplifier
2.5. Power Supply
The amplifier gain is designed at 18.5dB for optimized noise
performance and maximum input voltage.
Current consumption is about 300mA on these engineering
samples. The amplifier PSRR at 100kHz is around -60dB
when PG0 = PG1 = Hi. The PSRR will not vary much no matter what the values of VTGC and the gain setting are.
The 600kΩ input bias resistor is selected to give the user
a higher degree of freedom to program the active termination input impedance for matching the source impedance,
as shown in the LNA input impedance vs. frequency (Figure
12). The input capacitance is about 17.5pF.
3. Typical Characteristic Curves
All measured typical values are under the following conditions unless otherwise noted: TA = + 25°C, VDD = 2.5V, RLOAD
= 500Ω at the differential outputs, CLOAD = 1pF, fIN = 10MHz,
PG0 = 0V, PG1 = 0V, VGSC = 2.5V, VCM = 1.25V, amp gain
= 18.5dB, single-ended input: RS = RIN = 50Ω. (The RIN is
formed by active termination with RFB = 237Ω and CFB) differential signal output.
The LNA input-referred voltage noise is calculated based on
the whole channel output-referred voltage noise. As the gain
of LNA is not high, the output noise of the LNA cannot be
measured directly. Thus, it needs the following stages to amplify the noise such that the spectrum analyzer can read the
output noise spectrum greater than the noise floor.
The input-referred current noise is not measured and is estimated by the fact that the LNA input stage is constructed
by a MOS transistor, of which the input current is assumed
to very small.
3.1. Gain vs. TGC Voltage at Different PG0 &
PG1 settings and GSC = 2.5V
Gain v s. V GAI N
80
70
The noise figure is calculated from the input-referred noise
results.
PG1=Low , PG0=High
60
PG1=High, PG0=Low
GA IN ( dB )
50
The LNA bandwidth is measured at about 104MHz.
The common-mode rejection ratio of the amplifier is -65dB.
40
30
PG1=High, PG0=High
20
2.2. Overall Channel
10
The whole channel’s input voltage referred-input voltage
noise is 0.8nv/√ Hz. The channel crosstalk is measured
to be better than -70dB when the signal frequency is below 10MHz. Group delay variation is ±2ns, from 2MHz to
50MHz. The overload recovery time is about 5ns when the
gain is set at 8dB, VIN = 50mVP-P to 1.0VP-P step-change and
the frequency is 10MHz.
PG1=Low , PG0=Low
0
0 .0
0.2
0.4
0 .6
0.8
1.0
1 .2
1.4
1 .6
1 .8
2.0
V GAIN (V)
Figure 1
Figure 1 shows that the gain vs. TGC control voltage with
slope control voltage GSC equals 2.5V with different PG0
and PG1 settings. The gain spacing between settings is approximately 5.5dB. A 1MHz signal is applied at the input with
50ohm active termination. With settings at PG0 and PG1,
the control voltage is varied with 0.1V step. The differential
output is measured at a no-clipping condition and throughout the whole channel.
2.3. Accuracy
The gain slope of the VCA linear-in-dB control curve is measured to be 33.2dB/V. The channel-to-channel gain matching
is ±0.1dB at voltage control equals 0V or 2V. Other than the
conditions of minimum and maximum VCA gain settings, the
channel-to-channel gain matching of the MD3880 can be up
to ±0.3dB including the VCA interpolating effect. Gain slope
control voltage is tested at the gain slope control voltage
from 2V to 2.5V. The slope of the linear-in-dB curve will be
changed accordingly. The differential output offset is about
±20mV.
3.2. Gain vs. TGC Voltage at Different GSC
Voltages
Figure 2 shows the gain vs. TGC control voltage with different GSC slope control voltages. Only one case where
PG0 and PG1 are both low is charted. Other cases have
the similar effect. The measurement method is the above
measurement. The advantage of having the gain slope control voltage GSC pin is to let the user apply a programmable
2.4. Gain Control Interface
Input resistance of the slope control has less than 10% varia-
5
MD3880DB1
stable reference voltage among all the receiver channels in
order to have the same gain throughout the whole system
and varying the gain together.
Frequency Response for Various Values of VGAIN
PG1 = Low, PG0 = Low
60
Gain v s. V GAI N at D iff er e n t Vslo pe
V GA IN = 2V
50
PG1 = Lo w, PG0 = Low
V G AIN = 1.6V
60
40
V G AIN = 1.2V
30
G AI N ( dB )
Vslope=2.25V
50
40
V G AIN = 0.8V
20
V G AIN = 0.4V
GA IN ( dB )
10
V G AIN = 0.0V
V slope=2V
30
0
Vslope=2.5V
-10
20
-20
1.E+05
1.E+06
10
1.E+07
Fr e q ue n cy (H z)
1.E+08
1.E+09
Figure 4
0
0 .0
0.2
0.4
0 .6
0.8
1 .0
1 .2
1.4
1 .6
1.8
2 .0
V GAIN (V)
Frequency Response for Various Values of VGAIN
PG1 = Low, PG0 = High
Figure 2
70
V GA IN = 2V
60
3.3. Absolute Gain Error vs. TGC at Various
Frequencies
50
V G AIN = 1.6V
V G AIN = 1.2V
40
G AI N ( dB )
Figure 3 shows the absolute gain error vs. TGC at 1MHz,
10MHz and 30MHz.
Absolute Gain Error vs. VGAIN at Various Frequencies
30
V G AIN = 0.8V
20
V G AIN = 0.4V
10
G AI N ERRO R (dB)
V G AIN = 0.0V
2.00
0
1.50
-10
1.00
-20
1.E+05
10MHz
0.50
1.E+06
1.E+07
1 .E+08
1.E+09
F r e qu e n cy (Hz )
0.00
1MHz
Figure 5
-0.50
-1.00
30MHz
-1.50
-2.00
0.30
Frequency Response for Various Values of VGAIN
PG1 = High, PG0 = Low
0.50
0.70
0.90
1.10
1.30
1.50
1.70
1.90
70
V GA IN = 2V
V GAI N (V)
60
Figure 3
V G AIN = 1.6V
50
V G AIN = 1.2V
G AI N ( dB )
40
3.4. Frequency Response Various with TGC
Figures 4 through 7 show the frequency response of the
MD3880. All of the curves are measured with a network analyzer with frequencies up to 200MHz. Note that there is a
high-pass corner frequency existing at 10kHz and it is not
displayed in the figures.
V G AIN = 0.8V
30
V G AIN = 0.4V
20
V G AIN = 0.0V
10
0
-10
-20
1.E+05
1.E+06
1.E+07
F r e qu e n cy (Hz )
Figure 6
6
1 .E+08
1.E+09
MD3880DB1
Channel-to-Channel Crosstalk
PG1 = Low, PG0 = Low
Frequency Response for Various Values of VGAIN
PG1 = High, PG0 = High
0
80
V GA IN = 2V
-10
70
60
V OUT = 1Vpp
-20
V G AIN = 1.6V
V G AIN = 1.2V
-30
40
V G AIN = 0.8V
30
V G AIN = 0.4V
20
Crosstalk (dB)
G AI N ( dB )
50
V G AIN = 0.0V
10
-40
-50
-60
-70
0
-80
-10
V GAIN = 0.7V
V GAIN = 1.2V
1.E+06
1.E+07
1 .E+08
1.E+09
-100
1 .E+05
F r e qu e n cy (Hz )
1.E+06
1 .E+07
1.E+08
Frequency (Hz)
Figure 7
Figure 9
3.5. Frequency Response, Un-terminated
Figure 8 shows the whole channel frequency response without active termination, source resistance is 50Ω and GSC is
at 1.0V.
3.7. Group Delay vs. Frequency
Figure 10 shows the group delay vs. frequency. Due to the
internal 44pF and 1MΩ high-pass filter, the fairly constant
group delay only can be achieved at frequency 2.0 to 20MHz.
The group delay variation is ±2ns up to 60MHz.
Frequency Response, Unterminated, R s = 50ohm
PG1 = Low, PG0 = Low
35
V GAIN = 1V
RFB = ∞
Group Delay vs. Frequency
PG1 = High, PG0 = High, VGAIN = 0V
30
100
25
20
15
G RO UP DEL AY ( ns)
G AI N ( dB )
V GAIN = 2V
-90
-20
1.E+05
10
5
0
1.E+05
1.E+ 06
1.E+07
1.E+08
Frequency (Hz)
Figure 8
10
1.E+05
1.E+06
1.E+0 7
F re q u e ncy ( Hz )
3.6. Channel-to-Channel Crosstalk vs. Frequency for Various Values of TGC
Figure 10
Figure 9 shows the channel-to-channel crosstalk vs. frequency for various voltages of TGC. Although there are four
channels in a single chip, only one adjacent channel crosstalk is charted in this measurement. There is better than
70dB crosstalk when the frequency is below 10MHz.
7
1.E+08
MD3880DB1
3.8. Output Impedance vs. Frequency
Figure 11 shows the single-ended output impedance vs. frequency.
Output Impedance vs. Frequency
100
O UT PU T I MPEDA NC E (o h m)
SINGLE ENDED, RL = ∞
10
Figure 13
3.11. LNA Frequency Response, Single Ended
1
1.E+05
1.E+06
1.E+0 7
Figure 14 shows the LNA frequency response, inverting output, for values of RIN ≈ 50Ω and 100Ω. The RIN is formed
same as in Figure 12 measurement.
1.E+08
F re q u e ncy ( Hz )
Figure 11
LNA Frequency Response, Single Ended
15
3.9. LNA Input Impedance vs. Frequency
Figure 12 shows the LNA active termination input impedance
vs. frequency. The input impedance with RFB = ∞, RFB = 237Ω
and RFB = 470Ω is shown. Based on the active termination
equation, RIN = RFB/(1+A), a smaller RFB will be better for
implementing 50Ω or 100Ω termination in this version. Note
that the parasitic leads inductance and coupling capacitor in
series with the input.
RIN ~ 100Ω
10
GAIN (dB)
RIN ~ 50Ω
5
LNA Input Impedance vs. Frequency
100000
0
1.E+05
1.E+ 06
1.E+0 7
1.E+08
INPU T I MPEDA NCE (o hm )
Frequency (Hz)
10000
Figure 14
RF B = Inf inity, CSH = 0pF
1000
3.12. Frequency Response for Un-terminated
LNA, Single Ended
RFB = 470, CSH = 8.2pF
Figure 15 shows the un-terminated LNA frequency response,
inverting output, for Values of RIN ≈ ∞.
100
RFB = 237, CSH = 22pF
10
1.E+05
1 .E+06
1.E+ 07
1.E+08
Fr e q ue n cy (H z)
LNA Frequency Response, Unterminated, Single-Ended
Figure 12
20
15
3.10. Smith Chart, S11 vs. Frequency
10
Figure 13 shows the Smith chart, S11 vs. frequency with the
same settings as in Figure 12 measurement. (0.1MHz to
80MHz for Values of RFB = 237Ω and 470Ω)
G AI N ( dB )
5
0
-5
-10
-15
-20
-25
-30
1.E+05
1.E+ 06
1.E+07
F r e qu e n cy (Hz )
Figure 15
8
1.E+08
MD3880DB1
3.13. Output-Referred Noise vs.TGC
3.15. Short-Circuit, Input-Referred Noise vs.
TGC
Figure 16 shows the output-referred noise vs. TGC with different PG0 and PG1 settings. The data is measured directly
from the output with a transformer for converting the differential signal to a single ended signal.
Figure 18 shows the input-referred voltage noise vs. TGC
voltage, when PG0 = PG1 = High. The data is obtained by
calculating the output-referred output over the whole channel gain.
Ou tp ut R ef er r e d No ise v s. V GAI N
f = 10MHz
26 00
Short-Circuit, Input-Referred Noise vs. VGAIN
PG1=High, PG0=High
100
24 00
RS = 0, R F B = ∞
PG1=High, PG0=High, f = 10MHz
22 00
PG1=High, PG0=Low
20 00
18 00
PG1=Low , PG0=High
16 00
INPUT NOISE (nV/root Hz)
OU TPU T R EF ER RE D N OISE (n V/ro ot Hz)
28 00
14 00
12 00
PG1=Low , PG0=Low
10 00
8 00
6 00
4 00
2 00
10
1
0
0 .0
0 .5
1.0
V GAIN (V)
1 .5
2.0
Figure 16
0
0.0
0.4
0 .8
3.14. Short-Circuit, Input-Referred Voltage
Noise vs. Frequency
1.6
2 .0
Figure 18
Figure 17 shows the input-referred voltage noise from
100kHz to 60MHz. As the input stage of the amplifier is
formed by MOS transistors, it has 1/f noise and the noise
corner is about 1.5MHz as shown in the figure. At 5MHz, the
input-referred noise is approximately 0.8nV/√Hz.
3.16. Input-Referred Voltage Noise vs. RS
Figure 19 shows the input-referred voltage noise vs. RS the
signal source resistance.
Input-Referred Noise vs. R s
Short-Circuit, input-Referred Noise vs. Frequency
10.0
2.5
f = 5MHz, RFB = ∞ , VGAIN = 2V
INPUT NOISE (nV/root Hz)
PG1=High, PG0=High
2.0
INPUT NOISE (nV/√ Hz)
1.2
V GAIN (V)
1.5
1.0
1.0
RSTHERMAL NOISE ALONE
0.5
1 .E +0 5
1.E +06
1 .E+0 7
0.1
1.E+ 00
1 .E+0 8
FREQUENCY (Hz)
1 .E+0 1
1 .E+0 2
SOURCE RESISTANCE (ohm)
Figure 19
Figure 17
9
1.E+ 03
MD3880DB1
3.17. Noise Figure vs. RS for Various Values
of RIN
3.19. Noise Figure vs. Gain
Noise Figure vs. Gain
40
Noise Figure vs. R s for Various Values of R IN
RS = 50Ω, f = 10MHz
7
35
f = 10MHz
6
NOISE FIGURE (dB)
5
NOISE FIGURE (dB)
PG1 = High, PG0 = High
30
RIN = 50Ω
RIN = 75Ω
4
RIN = 100Ω
3
RIN = 200Ω
2
RIN = ∞
RIN = 50Ω
25
PG1 = High, PG0 = High
RIN = ∞
20
PG1 = Low, PG0 = Low
RIN = 50Ω
15
10
PG1 = Low, PG0 = Low
RIN = ∞
5
1
0
0
0
10
100
SOURCE RESISTANCE (Ohm)
10
20
1000
30
40
GAIN (dB)
50
60
70
Figure 22
Figure 20 is the noise figure vs. source resistance for various values of input resistance.
Figure 22 shows the noise figure vs. gain. Only PG0 = PG1
= High and PG0 = PG1 = Low measurement results are
charted. The data is calculated from the 10MHz input-referred noise measurement result.
3.18. Noise Figure vs. TGC Voltage
3.20. Harmonic Distortion vs. Frequency
Figure 20
Figures 23 through 26 show the harmonic distortion vs. frequency with different PG0 and PG1 settings.
Figure 21 shows the noise figure vs. TGC. It is calculated
by the input-referred noise measurement results and noise
figure equation.
Harmonic Distortion vs. Frequency
PG0 = High, PG1 = High
N oise F ig ur e v s. V G AI N
0
40
HARMONIC DISTORTION (dBc)
RS = 50Ω
PG1=High, PG0=High,f = 10MHz
35
NOISE FIGURE(dB)
30
25
G = 30dB
V O UT = 1Vpp
-10
RIN = 50Ω
20
RIN = ∞
15
-20
-30
-40
-50
-60
HD3
-70
-80
10
-90
5
-100
HD2
1
10
FREQUENCY (MHz)
0
0 .0
0.4
0.8
1 .2
1.6
2 .0
Figure 23
V GAIN (V )
Figure 21
10
100
MD3880DB1
3.21. Harmonic Distortion vs. Differential
Output Voltage
Harmonic Distortion vs. Frequency
PG1 = High, PG0 = Low
0
HARMONIC DIST ORTION (d Bc)
Figures 27 through 30 show the harmonic distortion vs. differential output voltage. Note that the maximum differential
output is 4V.
G = 30dB
V O UT = 1Vpp
-10
-20
-30
-40
Harmonic Distortion vs. Differential Output Voltage
PG1 = High, PG0 = High
-50
-40
G = 30dB
f = 10MHz
-60
HARMONIC DISTORTION (dBc)
HD3
-70
-80
HD2
-90
-100
1
10
100
FREQUENCY (MHz)
Figure 24
-50
HD3
-60
-70
HD2
-80
-90
0
Harmonic Distortion vs. Frequency
PG1 = Low, PG0 = High
1
2
V OUT (V PP)
3
4
0
HARMONIC DISTORTION (dBc)
Figure 27
G = 30dB
V O UT = 1VPP
-10
-20
-30
Harmonic Distortion vs. Differential Output Voltage
PG1 = High, PG0 = Low
-40
-40
G = 30dB
f = 10MHz
-60
HARMONIC DISTORTION (dBc)
-50
HD2
-70
HD3
-80
-90
-100
1
10
FREQUENCY (MHz)
100
-50
HD3
-60
-70
HD2
-80
Figure 25
-90
0
1
Harmonic Distortion vs. Frequency
PG1 = Low, PG0 = Low
G = 30dB
V O UT = 1V PP
-40
-30
G = 30dB
f = 10MHz
-40
HARMONIC DISTORTION (dBc)
HARMONIC DISTORTION (dBc)
4
Harmonic Distortion vs. Differential Output Voltage
PG1 = Low, PG0 = High
-20
-50
HD2
-60
-70
-80
HD3
-90
-100
3
Figure 28
0
-10
2
V OUT (VPP)
1
10
FREQUENCY (MHz)
100
-50
HD3
-60
-70
HD2
-80
-90
Figure 26
0
1
2
V OUT (Vpp)
Figure 29
11
3
4
MD3880DB1
Harmonic Distortion vs. V GAIN , f = 1MHz
PG1 = Low, PG0 = High
Harmonic Distortion vs. Differential Output Voltage
PG1 = Low, PG0 = Low
0
-40
V OUT = 1Vpp
-10
-50
-20
HD3
DISTORTION (dBc)
HARMONIC DISTORTION (dBc)
G = 30dB
f = 10MHz
-60
HD2
-70
-30
-40
-50
-60
-80
HD3
-70
-80
-90
0
1
2
3
HD2
4
V OUT (Vpp)
-90
0.0
0.2
0.4
0.6
0.8
Figure 30
1.0
1.2
V GAIN (V)
1.4
1.6
1.8
2.0
Figure 33
3.22. Harmonic Distortion vs. TGC
Figures 31 through 34 show the harmonic distortion vs. TGC
at 1MHz.
Harmonic Distortion vs. V GAIN , f = 1MHz
PG1 = Low, PG0 = Low
0
V OUT = 1Vpp
Harmonic Distortion vs. V GAIN , f = 1MHz
PG1 = High, PG0 = High
-10
0
-20
DISTORTION (dBc)
V OUT = 1Vpp
-10
DISTORTION (dBc)
-20
-30
-40
-30
-40
-50
-60
HD3
-50
-70
-80
-60
HD2
HD3
-70
-90
0.0
0.2
0.4
0.6
0.8
-80
-90
0.0
0.2
0.4
0.6
0.8
1.0
1.2
V GAIN (V)
1.0
1.2
1.4
1.6
1.8
2.0
V GAIN (V)
HD2
1.4
1.6
1.8
Figure 34
2.0
Figure 31
3.23. Harmonic Distortion vs. TGC
Harmonic Distortion vs. V GAIN , f = 1MHz
PG1 = High, PG0 = Low
Figures 35 through 38 show the harmonic distortion vs. TGC
at 10MHz.
0
V OUT = 1Vpp
-10
Harmonic Distortion vs. VGAIN , f = 10MHz
PG1 = High, PG0 = High
-20
V OUT = 1Vpp
-10
-40
-20
-50
DISTORTION (dBc)
DISTORTION (dBc)
0
-30
-60
HD3
-70
-80
HD2
-30
-40
-50
HD2
-60
-90
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
-70
V GAIN (V)
HD3
-80
Figure 32
-90
0.0
0.2
0.4
0.6
0.8
1.0
1.2
V GAIN (V)
Figure 35
12
1.4
1.6
1.8
2.0
MD3880DB1
Gain Amplifier and Differential Gain Amplifier when TGC is
lower than 0.4V. Otherwise, it is limited by the amplifier at
maximum -1dBm.
Harmonic Distortion vs. V GAIN , f = 10MHz
PG1 = High, PG0 = Low
0
V OUT = 1Vpp
-10
Input 1dB Compression vs. V GAIN
-20
-30
PG1=Low, PG0=Low
-10
-40
PG1=High, PG0=High
INPUT POWER (dBm)
DISTORTION (dBc)
0
-50
HD2
-60
-70
-80
HD3
-20
-30
PG1=High, PG0=Low
-40
PG1=Low, PG0=High
-90
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
-50
2.0
V GAIN (V)
-60
Figure 36
0.0
0.2
0.4
0.6
0.8
1.0
1.2
VGAIN (V)
1.4
1.6
1.8
2.0
Figure 39
Harmonic Distortion vs. V GAIN , f = 10MHz
PG1 = Low, PG0 = High
0
V OUT = 1Vpp
-10
3.25. IMD3 vs. Frequency
DISTORTION (dBc)
-20
Figures 40 through 43 show the IMD3 vs. frequency.
-30
IMD3 vs. Frequency
PG1 = High, PG0 = High
-40
0
-50
-60
G = 30dB
+f 22)
)
V OUT = 1Vpp COMPOSITE (f 11+f
-10
HD2
-20
-80
IMD3 (dBc)
-70
HD3
-90
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
-30
-40
-50
V GAIN (V)
-60
Figure 37
-70
-80
Harmonic Distortion vs. VGAIN , f = 10MHz
PG1 = Low, PG0 = Low
1
10
FREQUENCY (MHz)
100
0
Figure 40
V OUT = 1Vpp
-10
IMD3 vs. Frequency
PG1 = High, PG0 = Low
-30
0
-40
G = 30dB
+f 22)
)
V OUT = 1Vpp COMPOSITE (f 11+f
-10
-50
-20
-60
HD2
IMD3 (dBc)
DISTORTION (dBc)
-20
-70
-80
HD3
-30
-40
-50
-90
0.0
0.2
0.4
0.6
0.8
1.0
1.2
V GAIN (V)
1.4
1.6
1.8
2.0
-60
-70
Figure 38
-80
1
3.24. 1dB Compression vs. TGC
Figure 39 shows the 1dB compression point measurement
vs. TGC at 10MHz with PG0 = PG1 = High. The 1dB compression point is limited by the total gain of the internal Fixed
10
FREQUENCY (MHz)
Figure 41
13
100
MD3880DB1
Output Third-Order Intercept vs. VGAIN
IMD3 vs. Frequency
PG1 = Low, PG0 = High
PG1 = High, PG0 = Low
40
0
G = 30dB
(f1+f2)
+f )
V OUT = 1Vpp COMPOSITE (f
1 2
-10
35
1MHz
30
OU TPU T IP3 (d B m )
IMD3 (dBc)
-20
-30
-40
-50
10MHz
25
20
15
10
V O UT = 1V PP COMPOSITE (f1 +f2 )
-60
5
-70
0
0 .0
-80
1
10
FREQUENCY (MHz)
0 .4
0.8
1 .2
1.6
2.0
V GAIN (V)
100
Figure 45
Figure 42
Output Third-Order Intercept vs. VGAIN
PG1 = Low, PG0 = High
40
IMD3 vs. Frequency
PG1 = Low, PG0 = Low
35
0
G = 30dB
+f 22)
)
VOUT = 1Vpp COMPOSITE (f 11+f
-20
IMD3 (dBc)
1MHz
30
OUTPUT IP3 (dBm)
-10
-30
-40
25
10MHz
20
15
10
-50
V O UT = 1V PP COMPOSITE (f1 +f2 )
5
-60
0
0 .0
-70
-80
0 .4
0.8
1 .2
1 .6
2 .0
1.6
2.0
V GAIN (V)
1
10
FREQUENCY (MHz)
100
Figure 46
Figure 43
Output Third-Order Intercept vs. VGAIN
PG1 = Low, PG0 = Low
40
3.26. Output Third-Order Intercept vs. TGC
35
Figures 44 through 47 show the OIP3 vs. TGC at different
PG0 and PG1 settings.
OUTPUT IP3 (dBm)
30
Output Third-Order Intercept vs. VGAIN
PG1 = High, PG0 = High
40
10MHz
10MHz
25
20
15
10
35
V O UT = 1V PP COMPOSITE (f1 +f2 )
5
30
OU TPU T IP3 (d B m )
1MHz
1MHz
0
25
0 .0
0 .4
0.8
1.2
V GAIN (V)
20
Figure 47
15
10
V O UT = 1V PP COMPOSITE (f1 +f2 )
5
0
0.0
0.4
0.8
1.2
1.6
2.0
V GAIN (V)
Figure 44
14
MD3880DB1
3.27. Small Signal Pulse Response
3.29. Large Signal Pulse Response
Figure 48 shows the small signal pulse response with 1pF
loading.
(gain = 30dB, 1pF load, Top: input, bottom: output voltage
with attenuation of 10)
Figure 50 shows the large signal pulse response with 47pF
loading.
(gain = 30dB, 47pF load, top: the input signal, bottom: the
output voltage with attenuation of 10)
10mV/div
50mV/div
20mV/div
100mV/div
20ns/div
20ns/div
Figure 48
Figure 50
3.28. Large Signal Pulse Response
3.30. TGC Gain Control Transient Response
Time at PG0 = PG1 = Low.
Figure 49 shows the large signal pulse response with 1pF
loading. (gain = 30dB, 1pF load, Top: input, bottom: output
voltage with attenuation of 10)
Figure 51 shows TGC transient response. Top: TGC control
voltage, Bottom: signal output voltage with attenuation of 10.
The result showed that the TGC response time is less than
200ns.
50mV/div
2.0V/div
100mV/div
100mV/div
20ns/div
Figure 49
200ns/div
Figure 51
15
MD3880DB1
3.31. LNA Overload Recovery Time
Figure 52 shows LNA overdrive recovery
(VINPUT = 50mVP-P to 1VP-P burst, gain = 23dB, top: the input
signal, bottom: the channel output with attenuation of 20.)
100mV/div
500mV/div
100mV/div
100mV/div
80ns/div
Figure 54
3.34. PSRR vs. Frequency
80ns/div
Figures 55 and 56 show both the amplifier and VGA PSRR
measurement results. The PSRR is plotted based on the
equation: [–20log(GainOPEN / (VOUT/ ΔVDD))]. The GainOPEN, open loop gain of VGA PG0 = PG1 = Low, VGAIN = 0V,
the measurement result is -26dB. Since the gain of the fixedgain amplifier and PGA is 35dB, the VGA PSRR becomes 26dB -35dB = -61dB and it is irrelevant to VCA and amplifier.
The reason for setting the VGAIN to zero is to make the input
of the VGA as small as possible. The measurement of the
amplifier is as the same as VGA PSRR measurement. The
VOUT is the channel output. For example, at 100kHz, the output is recorded to be -41dB. Since the whole channel gain
is 23dB, the amplifier PSRR becomes -41dB-23dB = -64dB.
The reason for setting PG0 = PG1 = High is to maximize the
gain of the fixed-gain amplifier for simplifying the measurement.
Figure 52
3.32. VGA Overload Recovery Time
Figure 53 shows VGA overdrive recovery
(VINPUT = 2.5mVP-P to 70mVP-P burst, gain = 43dB, top: input,
bottom: channel output with attenuation of 20.)
50mV/div
VGA PSRR vs. Frequency (No Bypass Capacitor)
-30
100mV/div
-40
PG1 = Low , PG0= Low , V G AIN = 0V
PSRR (dB)
-50
80ns/div
Figure 53
PG1 = Low , PG0= High, V G AIN = 0V
-60
-70
PG1 = High, PG0= Low , V G AIN = 0V
-80
3.33. VGA Overload Recovery Time
PG1 = High, PG0= High, V GAIN = 0V
Figure 54 shows VGA overdrive recovery
(VINPUT = 10mVP-P to 280mVP-P burst, gain = 43dB, top: input,
bottom: channel output with attenuation of 20.)
-90
1.E+05
1.E+ 06
1.E+07
Frequency (Hz)
Figure 55
16
1.E+08
MD3880DB1
Preamplifier PSRR vs. Frequency (No Bypass Capacitor)
-30
PG1 = High, PG0= High, V GAI N = 0V
-35
-40
PSRR (dB)
-45
-50
-55
-60
-65
-70
1.E+05
1.E+06
1.E+07
1.E+08
Frequency (Hz)
Figure 56
4. Measurement Considerations and Setups
4.1. Gain and Bandwidth and Group Delay Measurements
A 2.5V, 400mA (minimum) power supply is required, and a low noise voltage reference supply is required for VTGC. Figures
57 through 65 show typical testing configurations and appropriate interface values for measurements with 50Ω conditions.
As the maximum whole channel gain is 70dB, when measuring high gain settings, the output signal power of the network
analyzer should be small enough (i.e. -60dBm) such that the channel output will not be clipped.
LNA
Figure 57
17
MD3880DB1
4.2. Frequency Response for Unterminated Single Ended LNA
Since the output impedance of the LNA is not configured to 50Ω, a high impedance active probe is used in the measurement. The calibration of the frequency response for the whole setup should take the high impedance active probe effect
into account.
LNA
Figure 58
4.3. LNA Input Impedance vs. Frequency in Standard and Smith Chart (S11) formats
The measurement results will include the ferrite bead inductor and filtering capacitor and the parasitic effect from the PCB.
Simply short the ferrite bead inductor and remove the filtering capacitor if needed. Suitable calibrations should be executed
for eliminating the PCB effect.
LNA
Figure 59
18
MD3880DB1
4.4. Shot-Circuit, Input-Referred Noise and Noise Figure
The input-referred noise level is found by dividing the output noise by the channel gain and accounting for the noise floor of
the spectrum analyzer. As the VGA drives the 50Ω load directly, the gain should be measured at each interested frequency
with signal generator. The signal generator is removed when measuring output noise.
LNA
Figure 60
4.5. Harmonic Distortion Measurements
The harmonic distortion can only be accurately measured with a low harmonic distortion signal generator. If the signal
generator cannot provide such a low harmonic distortion signal, a low-pass filter is usually used to ensure the measured
harmonic is absolutely from the device.
LNA
Figure 61
19
MD3880DB1
4.6. IMD3 and OIP3 vs. Frequency Measurements
Two signal generators are used in the IMD3 and OIP3 measurements. Their signal power can be combined by a 50Ω matching power combiner.
LNA
Figure 62
4.7. Pulse Response Measurement
A pulse generator is used in the pulse response measurement. Different pulse magnitudes are applied to the input of LNA
and an oscilloscope is used to capture the output waveform. The whole channel gain is properly set so as not to clip the
output waveform.
LNA
Figure 63
4.8. GAIN Transient Response Measurement
In the transient response measurement, a differential probe is used to measure the output waveform directly without magnitude attenuation. The signal applied to the TGC pin should be properly shielded to avoid any signal coupling to the system.
LNA
Figure 64
20
MD3880DB1
4.9. PSRR vs. Frequency Measurement
The output signal of the network analyzer is applied to either LNA or VGA supply for measuring the individual PSRR. All the
decoupling capacitors mounted to the VDD pins are removed during the measurement. Also, the frequency response of the
whole channel should be taken into account.
LNA
Figure 65
051007
21