CSC501
Operating Systems Principles
Interrupts
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Last Lecture
q Deadlock
Q Necessary Conditions
Q Solutions
q Today
Q Interrupts
Question:
Why do we need
interrupts?
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Introduction
q Interrupts provide an efficient way to handle
unanticipated events and improve processor
utilization
q Interrupts alter a program’s flow of control
Q Interrupt causes transfer of control to an
interrupt service routine (ISR)
v ISR is also called a handler
Q When the ISR is completed, the original
program resumes execution
Q Behavior is similar to a procedure call
v Some significant differences between the two
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Interrupts vs. Procedures
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Interrupts
Initiated by both software
and hardware
Can handle anticipated and
unanticipated internal as well
as external events
ISRs or interrupt handlers
are memory resident
Use numbers to identify an
interrupt service
eflags register is saved
automatically
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Procedures
Can only be initiated by
software
Can handle anticipated
events that are coded into
the program
Typically loaded along with
the program
Use meaningful names to
indicate their function
Do not save the eflags
register
A Taxonomy of Pentium Interrupts
Difference:
q Depending on the way they are reported
q Whether or not the interrupted instruction is
restarted
Interrupt Taxonomy
q Exceptions
Q Faults, Traps, and Aborts
q Software Interrupts
q Hardware Interrupts
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Exceptions: Faults, Traps, and Aborts
q Faults
Q Instruction boundary before the instruction
during which the exception was detected
Q Restarts the instruction
q Examples:
Q Page fault
Q Segment-not-found fault
Exceptions: Faults, Traps, and Aborts
q Traps
Q Instruction boundary immediately after the
instruction during which the exception was
detected
Q No instruction restart
q Examples:
Q Overflow exception (interrupt 4) is a trap
Q User defined interrupts are also examples of
traps
Exceptions: Faults, Traps, and Aborts
q Aborts
Q No precise location of the instruction that
caused the exception
Q No instruction restarting
Q Reporting severe errors such as hardware
errors and inconsistent values in system tables
qExamples:
QMachine check
QDouble fault
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Dedicated Interrupts
q Several Pentium predefined interrupts --called dedicated interrupts
q These include the first five interrupts:
interrupt type Purpose
0
Divide error
1
Single-step
2
Non-maskable interrupt (NMI)
3
Breakpoint
4
Overflow
Dedicated Interrupts (cont’d)
q Single-Step Interrupt
QUseful in debugging
QTo single step, Trap Flag (TF) should be set
QCPU automatically generates a type 1 interrupt
after executing each instruction if TF is set
QType 1 ISR can be used to present the system
state to the user
Dedicated Interrupts (cont’d)
q Breakpoint Interrupt
QUseful in debugging
QCPU generates a type 3 interrupt
QGenerated by executing a special single-byte
version of int 3 instruction (opcode CCH)
Interrupt Taxonomy
q Exceptions
q Software Interrupts
q Hardware Interrupts
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Software Interrupts
q Initiated by executing an int instruction, where
the interrupt number is an integer between 0
and 255
q Each interrupt can be parameterized to provide
several services.
Q For example, Linux interrupt service int 0x80
provides a large number of services (more than
330 system calls!)
v EAX register is used to identify the required
service under int 0x80
Hardware Interrupts
q Software interrupts are synchronous events
Q Caused by executing the int instruction
q Hardware interrupts are asynchronous in
nature
Q Typically caused by applying an electrical signal
to the processor chip
q Hardware interrupts can be
Q Maskable
Q Non-maskable
How Are Hardware Interrupts Triggered?
q Maskable interrupt is triggered by applying an
electrical signal to the INTR (INTerrupt Request)
pin of Pentium
Q Processor recognizes this interrupt only if IF
(interrupt enable flag) is set
Q Interrupts can be masked or disabled by clearing IF
q Non-maskable interrupt is triggered by applying an
electrical signal to the NMI pin of processor
Q Processor always responds to this signal
Q Cannot be disabled under program control
How Does the CPU Know the Interrupt Type?
q Interrupt invocation process is common to all
interrupts
QWhether originated in software or hardware
q For hardware interrupts, processor initiates an
interrupt acknowledge sequence
Qprocessor sends out interrupt acknowledge (INTA)
signal
QIn response, interrupting device places interrupt
vector on the data bus
QProcessor uses this number to invoke the ISR that
should service the device (as in software interrupts)
How Can More Than One Device Interrupt?
q Processor has only one INTR pin to receive
interrupt signal
q Typical system has more than one device that
can interrupt --- keyboard, hard disk, floppy,
etc.
q Use a special chip to prioritize the interrupts
and forward only one interrupt to the CPU
Q 8259 Programmable Interrupt Controller chip
performs this function
Interrupt Processing
q How many interrupts can be supported?
Q Up to 256 interrupts
q Interrupt number is used as an index into the
Interrupt Descriptor Table (IDT)
Q This table stores the addresses of all ISRs
Q Each descriptor entry is 8 bytes long
v Interrupt number is multiplied by 8 to get byte
offset into IDT
Q Location:
v Protected mode: anywhere in memory
IDTR
Detailed Steps in Interrupt Processing
q Step 1: Save the current machine state
q Step 2: Load the machine state for interrupt
handling
q Step 3: Invoke the corresponding ISR
q Step 4: Resume the program execution
Question:
Why do we need to save the current machine states?
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Step 1: Save the Current Machine State
q Push the EFLAGS register onto the stack
q Clear interrupt enable and trap flags
Q This disables further interrupts
Q Use sti to enable interrupts
q Push CS and EIP registers onto the stack
Question:
Where are these states saved?
Step 2: Load the Machine State for
Interrupt Handling
q Load CS with the 16-bit segment selector from the
interrupt gate
q Load EIP with the 32-bit offset value from the
interrupt gate
Question:
How to locate and load the machine states for
interrupt handling?
Protected Mode Interrupt Processing
IDTR
Organization of the IDT
Protected Mode Interrupt Processing
q IDTR contains the memory location of IDT
q IDTR is a 48-bit register
Q 32 bits for IDT base address
Q 16 bits for IDT limit value
v IDT requires only 2048 (11 bits)
v A system may have smaller number of descriptors
n Set the IDT limit to indicate the size in bytes
q Two special instructions to load (lidt) and store
(sidt) IDT
Q Both take the address of a 6-byte memory as the
operand
Protected Mode Interrupt Processing
Interrupt descriptor
Protected Mode Interrupt Processing
Interrupt invocation
Step 3: Invoke the ISR
q ISR: Interrupt-specific service routine
q Examples:
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Single-step
Breakpoint
Timer
Page fault
…
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Step 4: Resume the Program Execution
q What is the last instruction in an ISR:
Q iret
q The actions taken on iret are:
Q pop the 32-bit value on top of the stack into EIP
Q pop the 16-bit value on top of the stack into CS
Q pop the 32-bit value on top of the stack into the
EFLAGS register
q As in procedures, make sure that your ISR does
not leave any data on the stack
Q Match your push and pop operations within the ISR
An Example:
q Timer interrupt handler
Q Related files: sys/clkint.S sys/clkinit.c
Q Interrupt rate – based on clock timer
v ctr1000: 1ms
Q Scheduling rate:
v Interrupt rate * QUANTUM
q You will be familiar with page fault handler in
Lab 3!
q Others: sys/evec.c
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Next Lecture
q Midterm Review
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