MOST PARASITIC CAPACITANCES
gate-bulk overhang
FOX
d2
W
LD
LD
L
drain
source
d1
moat
gate-bulk overhang
gate
TOP VIEW
gate
CGDO
SIDE VIEW
channel
oxide
CGSO
CGC
drain
p
p+
p+
CBD1
TOX
CBC1
CGB
source
CBS1
Bulk (NSUB)
FRONT VIEW
ParasiticCapacitorsinMOStransistors,shownforp-channeldevice
Figure 1. Parasitic capacitances of mos transistor.
1
MOST Oxide Capacitances
COX is the controlling capacitance of the MOST device. It gives rise to three
capacitances:
•
an overlap capacitance between gate and source CGSO
•
a gate to channel capacitance CGC
•
an overlap capacitance between gate and drain CGDO
The overlap capacitances are a result of the gate overlapping source and drain by
an amount LD (see Figure 1 ). The corresponding capacitances CGSO and CGDO are
calculated as follows:
C GSO = CGSO * W
C GDO = CGDO * W
However, the overlap LD is never known precisely and therefore, in the SPICE
parameters list, the parameters CGSO and CGDO are given in Farad per meter with
channel width W, as design parameter.
It is obvious that CGSO is directly added to terminal capacitance CGS and that CGDO
is added to CGD.
The contribution of the gate-to-channel to the terminal capacitances depends on
the operation region of the device. Its total value is
CGC=COX*W*Leff
In the ohmic region, CGC occurs between the gate and the channel, which connects
source and drain and its value is even split between the terminal capacitances CGS and
CGD.
CGS = CGSO + 1/2 CGC
CGD = CGDO + 1/2 CGC
In the saturation region, however, the channel is discontinued at the drain end.
Most of the capacitance 2/3 CGC is added to the source terminal capacitance and nothing
is added to CGD.
2
CGS = CGSO + 2/3 CGC
CGD = CGDO
MOST Junction Capacitances
The source-channel-drain structure is isolated from the substrate by junction space
charge depletion layers. Therefore, three junction capacitances are:
the channel-bulk (or substrate) junction capacitance CBC
the source-bulk junction capacitance CBS
the drain-bulk junction capacitance CBD
The channel-bulk junction capacitance CBC is the controlling capacitance like CGS
in the oxide capacitance. Its total value is
C BCj =
CJ
 VBC 
1
 φB 
mj
CBC =CBCj W Leff
In the calculation, VBC=VBS in order to obtain a worst case value.
The capacitance CBC is divided over the terminal capacitances CBS and CBD in
very much the same way as CGC is divided over CGS and CGD.
The source-bulk and drain-bulk junction capacitances consist of a bottom plate
capacitance and a side wall capacitance. All values depend on the respective junction
voltages.
C BSj =
Cj
 VBS 
1
 φB 
C BSjsw =
mj
C jsw
 VBS 
1
 φB 
mjsw
C BSO = A SC BSj + PSC BSjsw
3
C BDj =
C BDjsw
Cj
mj
 VBD 
1
 φB 
C jsw
=
mjsw
 VBD 
1
 φB 
C BDO = A D C BDj + PD C BDjsw
In the ohmic region
CBS = CBSO + 1/2 CBC
CBD = CBDO + 1/2 CBC
In the saturation region,
CBS = CBSO + 2/3 CBC
CBD = CBDO
4
L=10
6
10
LD
Drain
Source
Gate
W=15
(a)
VD=+5v
D
CGD
VG=0..5v
G
CBD
B
S
CGS
CBS
(b)
Figure 2. NMOS transistor: (a) layout, (b) terminal parasitic capacitances.
5
*SCNA20 Orbit 2u technology Spice Parameters
.MODEL CMOSN NMOS LEVEL=1 PHI=0.600000 TOX=4.1000E-08
XJ=0.200000U TPG=1
+ VTO=0.8630 DELTA=6.6420E+00 LD=2.4780E-07 KP=4.7401E-05
+ UO=562.8 UEXP=1.5270E-01 UCRIT=7.7040E+04 RSH=2.4000E+01
+ GAMMA=0.4374 NSUB=4.0880E+15 NFS=1.980E+11
NEFF=1.0000E+00
+ VMAX=5.8030E+04 LAMBDA=3.1840E-02 CGDO=3.1306E-10
+ CGSO=3.1306E-10 CGBO=4.3449E-10 CJ=9.5711E-05 MJ=0.7817
+ CJSW=5.0429E-10 MJSW=0.346510 PB=0.800000
* Weff = Wdrawn - Delta_W
*The suggested Delta_W is -5.4940E-07
εO = 8.86 x 10-14 F/cm =8.86 x 10-18 F/µm =.00886 fF/µm
LD = .2478 µm ≅ .25 µm
Leff = L - 2LD = 10 - 2 (.25) = 9.5 µm
W = 15 µm
CGSO=CGDO=3.13x10-10 F/m=0.313 fF/µm
Cj = 9.57x10-5 F/m2 =0.0957fF/µm2
mj = .7817
Cjsw = 5.0429x10-10 F/m=0.50429 fF/µm
mjsw = .34651
VBC=VBS=0
VBD=-5v
MOST Oxide Capacitances
C OX =
ε OX
TOX
=
3.9ε O 3.9(8.86x10 -14 F/cm) 3.9(.00886fF/cm)
=
=
= .843fF/µm 2
TOX
4.1x10 -8 m
4.1x10 -2 µm
C GC = C OX W L eff = (.843fF/µm 2 )(15µm)(9.5µm) = 120fF
C GSO = CGSO • W = (3.13x10 -10 F/m)(15µm) = 4.7fF
C GDO = CGDO • W = (3.13x10 -10 F/m)(15µm) = 4.7fF
Ohmic Region
C GS = C GSO +
1
1
C GC = 4.7fF + (120fF) = 64.7fF
2
2
C GD = C GDO +
1
1
C GC = 4.7fF + (120fF) = 64.7fF
2
2
Saturation Region
6
2
2
C GC = 4.7fF + (120fF) = 84.7fF
3
3
C GS = C GSO +
CGD = CGDO = 4.7fF
MOST Junction Capacitances
C BCj =
Cj
 VBC
1  φB



mj
Cj
=
 VBS 
1 
φ
B 

=
mj
9.57 x10 -5 F/m 2
 0
1 - 
 .8 
=
.7817
.0957fF/µm 2
 0
1 - 
 .8 
.7817
= .0957fF/µm 2
C BC = C BCj W L eff = (.0957fF/µm 2 )(15µm)(9.5µm) = 13.64fF
C BSj =
Cj
 VBS 
1 
 φB 
C BSjsw =
=
mj
9.57 x10 -5 F/m 2
 0
1 - 
 .8 
C jsw
 VBS 
1 
 φB 
=
mjsw
.7817
=
.0957fF/µm 2
 0
1 - 
 .8 
5.0429 x10 -10 F/m
 0
1 - 
 .8 
.34651
=
.7817
= .0957fF/µm 2
.50429fF/µm
 0
1 - 
 .8 
.34651
= .50429fF/µm
C BSO = A S C BSj + PS C BSjsw
= (150 µm 2 )(.0957fF/µm 2 ) + (50µm)(.50429fF/µm) = 39.57fF
C BDj =
Cj
 VBD
1  φB
C BDjsw =



mj
=
9.57 x10 -5 F/m 2
C jsw
 VBD
1  φB



mjsw
 -5
1 - 
 .8 
=
.7817
=
0.0957fF/µm 2
 -5
1 - 
 .8 
5.0429x10 -10 F/m
 -5
1 - 
 .8 
.34651
=
.7817
= 0.0203fF/µm 2
0.50429fF/µm
 -5
1 - 
 .8 
.34651
= .2539fF/µm
7
C BDO = A D C BDj + PD C BDjsw
= (90 µm 2 )(0.0203fF/µm 2 ) + (42µm)(0.2539fF/µm) = 12.49fF
Ohmic region:
1
1
C BS = C BSO + C BC = 39.5fF + (13.64fF) = 46.39fF
2
2
1
1
C BD = C BDO + C BC = 12.49fF + (13.64fF) = 19.31fF
2
2
Saturation region:
2
2
C BS = C BSO + C BC = 39.57fF + (13.64fF) = 48.66fF
3
3
C BD = C BDO = 12.49fF
Electrode Capacitor
See Layout of Capacitor
Poly Resistor/HighRes Poly2 Resistor
See Layout of Resistor
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