1
Experiment 4
Phase-Locked Loop
1. Objectives:
• To measure the relavent parameters of an IC phase-locked loop (PLL).
2. Prelab Assignment:
1. Read the spec’s from the IC phase-locked loop LM565C.
2. Consider the circuit diagram in Figure (1). The manufacturers give the following approximatedesign equations:
the VCO free-running frequency, fo
fo ≈ 0.3/(R1 C1 )
(1)
the hold-in, tracking, or lock range, fH
fH ≈ ±8fo /(V + + |V − |)
(2)
the capture, pull-in, or acquisition range, fC
q
fC ≈ ± fH · flpf
(3)
where, flpf is the 3dB frequency of the lowpass filter section.
V+
LPF
10
C2
input
input
3.6k Ω
2
3
5
4
phase
detector
VCO output
Amplifier
VCO
565C
8
R1
9
C1
V+
1
V
Figure (1)
7
6
Demodulated
output
Reference
output
2
Determine:
(a) the value of R1 needed to set fo @ 10kHz, given that C1 = 0.01µF
(b) the values of fH and fC , when V + = V − = 8V and C2 = 0.047µF
(c) the values of fH and fC , when C2 is replaced by a 1.0 µF capacitor
3. Equipment:
• Function generators Tektronix CFG 253
• Oscilloscope Tektronix TDS 340A
• Dual DC-power supply
• LPF module
• Digital voltmeter
4. Procedure:
1. Connect the circuit in Figure (2). Display the signal waveforms @ pins 9 and 4 on the
oscilloscope; the waveform @ pin 4 will be referred to as Vo (t). Use Graph (1) to plot
both displays. Adjust R1 to set the free-running frequency of the VCO @ 10 kHz.
Measure (w.r.t ground) the dc voltages @ pins 6 and 7; leave the EVM @ pin 7. Note
that when the VCO is in the free-running mode, both voltages are equal, and are referred
to as Vref .
Graph (1)
3
8V
2.2k
R1
10k
0.001 µF
7
Demodulated
output
4
VCO output
8
10
input
2
LM565C
3
C3
C2
0.047µ F
5
9
1
C1
0.01 µF
-8V
Figure (2)
2. Apply a 1V (p-p) sinusoid @ 4 kHz to pin 2; this signal will be referred to as Vi (t). Display
Vi (t) and Vo (t) on the oscilloscope, with Vi (t) as the trig. source. Note that the traces
will synchronize only when the PLL is in hold-in (tracking) condition.
Gradually increase the input signal frequency, fi , and determine the frequency fc− which
defines the lower edge of the capture range [fc− is the frequency at which the traces
suddenly synchronize, and remains in synch with freq. changes]. The PLL is now in
hold-in condition. Measure the dc voltage @ pin 7; this voltage will be referred to as VD .
3. Increase further the frequency fi , and for each integer-value (in kHz) setting of fi , measure
the phase angle of Vo (t) w.r.t. Vi (t) and the dc-voltage VD . Find the frequency fH+ which
defines the upper edge of the tracking range. Record in table (1).
Table (1) : C2 = 0.047 uF ; fi ↑
fC−
fi (kHz)
6 Vo /Vi
VD - Vref
fH+
4
4. Gradually decrease the frequency fi , and determine fC+ [the upper edge of the capture
range]. Decrease further fi and measure Vo (t) and VD for each integer-value (in kHz)
setting of fi . Find fH− [the lower edge of the tracking range], and record in table (2).
Table (2) : C2 = 0.047 uF ; fi ↓
fH−
fC+
fi (kHz)
6 Vo /Vi
VD - Vref
5. Use Graph (2) to plot [VD - Vref ] vs fi , and use Graph (3) to plot [VD - Vref ] vs 6 Vo /Vi .
* From the slope of the plot in Graph (2), find the VCO sensitivity, Ko , as:
Ko = 2π/[slope] rad/sec/V
=
* From the slope of the plot in Graph (3), find the phase-detector sensitivity, KD , as:
KD = (180/π)[slope] V/rad
=
5
Graph (2)
Graph (3)
6. Replace C2 by a 1.0 µF capacitor. Find the frequency locations for fC− , fH− , fC+ and
fH− . Record in table (3).
Table (3) : C2 = 1.0 µF
fC−
fH+
fC+
fH−
5. Comments and Conclusions:
1. Explain briefly why Vi (t) and Vo (t) are not synchronized during the time when the PLL
is not in lock condition.
2. In step 2, fi was increased towards fC− . It was noticed that, while fi < fC− , there were
a few isolated narrow-band frequency positions were Vo (t) and Vi (t) did synchronize with
each other. How do you explain this phenomenon?
3. How do the measured values of KD and Ko compare with those in the spec’s? Comment
on any deviation.
4. In step 8, when C2 was replaced by a 1 µF capacitor, the PLL went out of sync. Why?