Q#1
King Saud University
College of Engineering
Electrical Engineering Department
Student name:
Q#2
Total Marks
Student ID:
EE208: Logic Design
2nd Mid Term Exam
Time allowed: 60 Min
2nd Semester 1426H
Question 1:
a) Use only one decoder 2/4 with extra gates to implement the logic function
F = AB + B’C
Write the truth table and draw the circuit diagram (hint: A is the MSB, C is the LSB)
Y= X ;
Where X is a 4-bit signed input binary number and Y is the ROM output code
b) Compute the ROM size to implement the function
Answer to question 1:
Question 2:
a) Design a 8X1 line Multiplexer using 4X1 line Multiplexers having separate enable inputs. Use block
diagram construction.
b) A combinational logic circuit is defined by
F1 = Σ (0,1,3,7) ;
F2 = Σ (2,6)
Write the PLA program table using PLA having 3 inputs and 2 outputs
(hint: use minimal number of product terms)
Answer to question 2: