Application Report
SLUA560C – September 2010 – Revised June 2011
UCC28950 600-W, Phase-Shifted, Full-Bridge
Application Report
Michael O'Loughlin
Introduction
In high-power server applications to meet high-efficiency and green standards some power-supply
designers have found it easier to use a phase-shifted, full-bridge converter. This is because the phaseshifted, full-bridge converter can obtain zero-voltage switching on the primary side of the converter
reducing switching losses, and EMI and increasing overall efficiency. The purpose of this application
report is to review the design of the 600-W, phase-shifted, full-bridge converter for one of these power
systems, using TI’s new UCC28950 Phase-Shifted, Full-Bridge Controller, and was based on typical
values. In a production design the values need to be modified for worst case conditions. Hopefully this
information will aid other power supply designers in their efforts to design an efficient phase-shifted, fullbridge converter. Also note there is a MathCAD Design Tool, (TI Literature Number SLUC210), that goes
along with this application note as well.
Design Specifications
DESCRIPTION
Input Voltage
Output Voltage
MIN
TYP
370 V (VINMIN)
390 V (VIN)
11.4 V
12 V (VOUT)
Allowable Output Voltage Transient
MAX
410 V (VINMAX)
12.6 V
600 mV (VTRAN)
Load Step, 90%
Output Power
600 W (POUT)
Full Load Efficiency
93% (η)
Inductor (LOUT) Switching Frequency
200 kHz (fS)
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Functional Schematic
CT
+
QA
OUTA
V IN
R RE
C IN
QB
DA
OUTC
QD
d
LS
QB
OUTB
QD
d
OUTD
DC
RS
_
QC
DB
T1
CS
L OUT
+
C BP1
VREF
RB
RI
_
RA
UCC28950
CP
RC
RF
C SS
CZ
RD
825k
R DELCD
R DELAB
R TMIN
R DELEF
V OUT
C OUT
OUTF
OUTE
1uF
V OUT
QF
QE
RT
R SUM
C BP2
1uF
24
1
VREF
2
EA+
GND
VDD
3
EA-
OUTA
22
OUTA
12V Bias
COMP
OUTB
21
OUTB
5
SS/EN
OUTC
20
OUTC
6
DELAB
OUTD
19
7
DELCD
OUTE
18
8
DELEF
OUTF
17
9
TMIN
SYNC
16
CS
15
RT
11
RSUM
12
DCM
22 ohm
23
4
10
CS
R LF1
ADEL
14
ADELEF
13
R LF2
1k
OUTD
OUTE
VREF
OUTF
SYNC
R CA1
R DA1
RE
C LF
330pF
R CA2
R DA2
RG
VREF
Figure 1. UCC28950 Phase-Shifted, Full-Bridge Functional Schematic
Power Budget
To meet the efficiency goal a power budget needs to be set.
æ 1- h ö
PBUDGET = POUT ´ ç
÷ » 45.2 W
è h ø
2
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Preliminary Transformer Calculations (T1)
Transformer turns ratio (a1):
a1 =
NP
NS
(2)
Estimated FET voltage drop (VRDSON):
VRDSON = 0.3 V
(3)
Select transformer turns based on 70% duty cycle (DMAX) at minimum specified input voltage. This will give
some room for dropout if a PFC front end is used.
a1 =
a1 =
NP
NS
(4)
(VINMIN - 2 ´ VRDSON )´ DMAX
VOUT + VRDSON
» 21
(5)
Turns ratio rounded to the nearest whole turn.
a1 = 21
(6)
Calculated typical duty cycle (DTYP) based on average input voltage.
DTYP =
(VOUT + VRDSON )´ a » 0.66
(VIN - 2 ´ VRDSON )
(7)
Output inductor ripple current is set to 20% of the output current.
DILOUT =
POUT ´ 0.2
= 10 A
VOUT
(8)
Care needs to be taken in selecting a transformer with the correct amount of magnetizing inductance
(LMAG). The following equations calculate the minimum magnetizing inductance of the primary of the
transformer (T1) to ensure the converter operates in current-mode control. If LMAG is too small the
magnetizing current could cause the converter to operate in voltage mode control instead of peak-current
mode control. This is because the magnetizing current is too large, it will act as a PWM ramp swamping
out the current sense signal across RS.
LMAG ³
VIN ´ (1 - DTYP )
» 2.76mH
DILOUT ´ 0.5
´ fS
a1
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Figure 2 shows T1 primary current (IPRIMARY) and synchronous rectifiers QE (IQE) and QF (IQF) currents with
respect to the synchronous rectifier gate drive currents. Note that IQE and IQF are also T1’s secondary
winding currents as well. Variable D is the converters duty cycle.
IPP
IPRIMAY
IMP2
IMP2 » IPP -DILOUT/ (2 ´a1)
IMP
0A
D
On
QEg
Off
On
QFg
Off
IQE
0A
IQF
IPS
IMS2
IMS
IMS2 » IPS -DILOUT/2
0A
DILOUT/2
Figure 2. T1 Primary and QE and QF FET Currents
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Calculate T1 secondary RMS current (ISRMS):
POUT DILOUT
+
» 55 A
VOUT
2
(10)
P
DI
= OUT - LOUT » 45 A
VOUT
2
(11)
IPS =
IMS
IMS2 = IPS
ΔI
- LOUT » 50 A
2
(12)
Secondary RMS current (ISRMS1) when energy is being delivered to the secondary:
(I - I )
æD
öé
ISRMS1 = ç MAX ÷ êIPS ´ IMS + PS MS
3
è 2 ø êë
2
ù
ú » 29.6 A
úû
(13)
Secondary RMS current (ISRMS2) when current is circulating through the transformer when QE and QF are
both on.
(I - I )
æ 1 - DMAX ö é
êIPS ´ IMS2 + PS MS2
= ç
÷
2
3
è
ø êë
2
ISRMS2
ù
ú » 20.3 A
úû
(14)
Secondary RMS current (ISRMS3) caused by the negative current in the opposing winding during
freewheeling period, please refer to Figure 2.
ISRMS3 =
DILOUT æ 1 - DMAX ö
ç 2 ´ 3 ÷ » 1.1A
2
è
ø
(15)
Total secondary RMS current (ISRMS):
ISRMS = ISRMS12 + ISRMS22 + ISRMS3 2 » 36.0 A
(16)
Calculate T1 Primary RMS Current (IPRMS):
DILMAG =
VINMIN ´ DMAX
» 0.47 A
LMAG ´ fS
æ P
DI
IPP = ç OUT + LOUT
2
è VOUT ´ h
(17)
ö1
÷ + DILMAG » 3.3 A
ø a1
(18)
é
(IPP - IMP )2 ùú
ê
IPRMS1 = (DMAX ) IPP ´ IMP +
» 2.5 A
ê
ú
3
ë
û
(19)
æ DI
ö1
IMP2 = IPP - ç LOUT ÷ » 3.0 A
è 2 ø a1
(20)
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T1 Primary RMS (IPRMS1) current when energy is being delivered to the secondary.
é
IPRMS1 =
(DMAX )êêIPP ´ IMP +
(IPP - IMP )2 ùú
ë
3
ú
û
» 2.5 A
(21)
T1 Primary RMS (IPRMS2) current when the converter is free wheeling.
IPRMS2
2
é
IPP - IMP2 ) ù
(
ú » 1.7 A
= (1 - DMAX )êIPP ´ IMP2 +
3
êë
úû
(22)
Total T1 primary RMS current (IPRMS)
IPRMS = IPRMS12 + IPRMS22 » 3.1A
(23)
For this design a Vitec transformer was selected part number 75PR8107 that had the following
specifications.
a1= 21
LMAG = 2.8mH
(24)
(25)
Measure leakage inductance on the Primary:
LLK = 4 mH
(26)
Transformer Primary DC resistance:
DCRP = 0.215 W
(27)
Transformer Secondary DC resistance:
DCRS = 0.58 W
(28)
Estimated transform losses (PT1) are twice the copper loss.
NOTE:
This is just an estimate and the total losses may vary based on magnetic design.
(
)
PT1 » 2 ´ IPRMS 2 ´ DCRP + 2 ´ ISRMS 2 ´ DCRS » 7.0 W
(29)
Calculate remaining power budget:
PBUDGET = PBUDGET - PT1 » 38.1W
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QA, QB, QC, QD FET Selection
In this design to meet efficiency and voltage requirements 20 A, 650 V, CoolMOS FETs from Infineon
were chosen for QA..QD.
FET drain to source on resistance:
Rds(on)QA = 0.220 W
(31)
FET Specified COSS:
COSS _ QA _ SPEC = 780pF
(32)
Voltage across drain-to-source (VdsQA) where COSS was measured, data sheet parameter:
VdsQA = 25 V
(33)
Calculate average Coss [2]:
COSS _ QA _ AVG = COSS _ QA _ SPEC
VdsQA
» 193pF
VINMAX
(34)
QA FET gate charge:
QA g = 15nC
(35)
Voltage applied to FET gate to activate FET:
Vg = 12 V
(36)
Calculate QA losses (PQA) based on Rds(on)QA and gate charge (QAg):
PQA = IPRMS 2 ´ Rds(on)QA + 2 ´ QA g ´ Vg ´
fs
» 2.1W
2
(37)
Recalculate power budget:
PBUDGET = PBUDGET - 4 ´ PQA » 29.7 W
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Selecting LS
Calculating the shim inductor (LS) is based on the amount of energy required to achieve zero voltage
switching. This inductor needs to able to deplete the energy from the parasitic capacitance at the switch
node. The following equation selects LS to achieve ZVS at 100% load down to 50% load based on the
primary FET’s average total COSS at the switch node.
NOTE: There may be more parasitic capacitance than was estimated at the switch node and LS may
have to be adjusted based on the actual parasitic capacitance in the final design.
VINMAX 2
- LLK » 26 mH
LS ³ (2 ´ COSS _ QA _ AVG )
2
æ IPP DILOUT ö
ç 2 - 2 ´ a1 ÷
è
ø
(39)
For this design a 26-µH Vitec inductor was chosen for LS, part number 60PR964. The shim inductor had
the following specifications.
LS = 26 mH
(40)
LS DC Resistance:
DCRLS = 27mW
(41)
Estimate LS power loss (PLS) and readjust remaining power budget:
8
PLS = 2 ´ IPRMS 2 ´ DCRLS » 0.5 W
(42)
PBUDGET = PBUDGET - PLS » 29.2 W
(43)
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Output Inductor Selection (LOUT)
Inductor LOUT was designed for 20% inductor ripple current (∆ILOUT):
DILOUT =
LOUT =
POUT ´ 0.2 600 W ´ 0.2
=
» 10 A
VOUT
12 V
VOUT ´ (1 - DTYP )
» 2 mH
DILOUT ´ fs
(44)
(45)
Calculate output inductor RMS current (ILOUT_RMS):
2
ILOUT _ RMS
2
æ P ö æ DI
ö
= ç OUT ÷ + ç LOUT ÷ = 50.3 A
è VOUT ø è 3 ø
(46)
A 2-µH inductor from Vitec Electronics Corporation, part number 75PR108, was chosen for this design.
The inductor had the following specifications.
LOUT = 2 mH
(47)
Output inductor DC resistance:
DCRLOUT = 750 mW
(48)
Estimate output inductor losses (PLOUT) and recalculate power budget. Note PLOUT is an estimate of
inductor losses that is twice the copper loss. Note this may vary based on magnetic manufactures. It is
advisable to double check the magnetic loss with the magnetic manufacture.
PLOUT = 2 ´ ILOUT _ RMS 2 ´ DCRLOUT » 3.8 W
(49)
PBUDGET = PBUDGET - PLOUT » 25.4 W
(50)
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Output Capacitance (COUT)
The output capacitor is being selected based on holdup and transient (VTRAN) load requirements.
Time it takes LOUT to change 90% of its full load current:
tHU
LOUT ´ POUT ´ 0.9
VOUT
=
= 7.5 ms
VOUT
(51)
During load transients most of the current will immediately go through the capacitors equivalent series
resistance (ESRCOUT). The following equations are used to select ESRCOUT and COUT based on a 90% load
step in current. The ESR is selected for 90% of the allowable transient voltage (VTRAN), while the output
capacitance (COUT) is selected for 10% of VTRAN.
ESRCOUT £
COUT
VTRAN ´ 0.9
= 12mW
POUT ´ 0.9
VOUT
(52)
POUT ´ 0.9 ´ tHU
VOUT
³
» 5.6mF
VTRAN ´ 0.1
(53)
Before selecting the output capacitance it is also required to calculate the output capacitor RMS current
(ICOUT_RMS).
ICOUT _ RMS =
DILOUT
3
» 5.8 A
(54)
To meet our design requirements five 1500-µF, aluminum electrolytic capacitors were chosen for the
design from United Chemi-Con, part number EKY-160ELL152MJ30S. These capacitors had an ESR of 31
mΩ.
Number of output capacitors:
n=5
(55)
Total output capacitance:
COUT = 1500 mF ´ n » 7500 mF
(56)
Effective output capacitance ESR:
ESRCOUT =
31mW
= 6.2mW
n
(57)
Calculate output capacitor loss (PCOUT):
PCOUT = ICOUT _ RMS 2 ´ ESRCOUT » 0.21W
(58)
Recalculate remaining Power Budget:
PBUDGET = PBUDGET - PCOUT » 25.2 W
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Select FETs QE and QF
Selecting FETs for a design is always trial and error. To meet the power requirements of this design we
selected 75-V, 120-A FETs, from Fairchild, part number FDP032N08. These FETs’ had the following
characteristics.
QEg = 152nC
(60)
Rds(on)QE = 3.2mW
(61)
Calculate average FET COSS (COSS_QE_AVG) based on the data sheet parameters for COSS (COSS_SPEC), and
drain to source voltage where COSS_SPEC was measured (Vds_spec), and the maximum drain to source voltage
in the design (VdsQE) that will be applied to the FET in the application.
Voltage across FET QE and QF when they are off:
VdsQE =
VINMAX
» 19.5 V
a1
(62)
Voltage where FET COSS is specified and tested in the FET data sheet:
Vds _ spec = 25 V
(63)
Specified output capacitance from FET data sheet:
COSS _ SPEC = 1810pF
(64)
Average QE and QF COSS [2]:
COSS _ QE _ AVG = COSS _ SPEC
VdsQE
» 1.6nF
Vds _ spec
(65)
QE and QF RMS current:
IQE _ RMS = ISRMS = 36.0 A
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To estimate FET switching loss the Vg vs. Qg curve from the FET data sheet needs to be studied. First the
gate charge at the beginning of the miller plateau needs to be determined (QEMILLER_MIN) and the gate
charge at the end of the miller plateau (QEMILLER_MAX) for the given VDS.
QE
QE
MILLER
_ MIN
MILLER _ MAX
» 52 nC
» 100 nC
Figure 3. Vg vs. Qg for QE and QF FETs
Maximum gate charge at the end of the miller plateau:
QEMILLER _ MAX » 100nC
(67)
Minimum gate charge at the beginning of the miller plateau:
QEMILLER _ MIN » 52nC
(68)
NOTE: The FETs in this design were driven with UCC27324 setup to drive 4-A (IP) of gate drive
current.
IP » 4 A
(69)
Estimated FET Vds rise and fall time:
tr » t f =
100nC - 52nC 48nC
=
» 24ns
IP
4A
2
2
(70)
Estimate QE and QF FET Losses (PQE):
PQE = IQE _ RMS 2 ´ Rds(on)QE +
POUT
f
f
f
´ VdsQE (tr + t f ) s + 2 ´ COSS _ QE _ AVG ´ VdsQE 2 s + 2 ´ QgQE ´ VgQE s
VOUT
2
2
2
(71)
PQE » 9.3 W
(72)
Recalculate the power budget.
PBUDGET = PBUDGET - 2 ´ PQE » 6.5 W
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Input Capacitance (CIN)
If this converter was designed for a 390-V input, which is generally fed by the output of a PFC boost preregulator. The input capacitance is generally selected based on holdup and ripple requirements.
NOTE: The delay time needed to achieve ZVS can act as a duty cycle clamp (DCLAMP).
Calculate tank frequency:
fR =
1
2p LS ´ (2 ´ COSS _ QA _ AVG )
(74)
Estimated delay time:
tDELAY =
2
» 314ns
f R ´4
(75)
Effective duty cycle clamp (DCLAMP):
æ1
ö
DCLAMP = ç - tDELAY ÷ ´ fs = 94%
è fs
ø
(76)
VDROP is the minimum input voltage where the converter can still maintain output regulation. The
converter’s input voltage would only drop down this low during a brownout or line-drop condition if this
converter was following a PFC pre-regulator.
æ 2 ´ DCLAMP ´ VRDSON + a1´ (VOUT + VRDSON ) ö
VDROP = ç
÷ = 276.2 V
D
CLAMP
è
ø
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CIN was calculated based on one line cycle of holdup:
2 ´ POUT ´
CIN ³
(V
2
IN
1
60Hz
- VDROP 2
)
» 364 mF
(78)
Calculate high frequency input capacitor RMS current (ICINRMS).
2
ICINRMS = I
2
PRMS1
æ POUT ö
-ç
÷ = 1.8 A
è VINMIN ´ a1 ø
(79)
To meet the input capacitance and RMS current requirements for this design we chose a 330-µF capacitor
from Panasonic part number EETHC2W331EA.
CIN = 330 mF
(80)
This capacitor had a high frequency (ESRCIN) of 150 mΩ this was measured with an impedance analyzer
at both 120 and 200 kHz.
ESRCIN = 0.150 W
(81)
Estimate CIN power dissipation (PCIN):
PCIN = ICINRMS 2 ´ ESRCIN = 0.5 W
(82)
Recalculate remaining power budget:
PBUDGET = PBUDGET - PCIN » 6.0 W
(83)
There is roughly 6.0 W left in the power budget left for the current sensing network, and biasing the control
device and all resistors supporting the control device.
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Setting Up the Current Sense Network (CT, RS, RRE, DA)
The CT chosen for this design had a turn’s ratio (a2) of 100:1
a2 =
IP
= 100
IS
(84)
Calculate nominal peak current (IP1) at VINMIN:
Peak primary current:
æ P
DI
IP1 = ç OUT + LOUT
2
è VOUT ´ h
ö 1 VINMAX ´ DMAX
» 3.3 A
÷ +
LMAG ´ fs
ø a1
(85)
The voltage where peak current limit will trip.
VP = 2 V
(86)
Calculate current sense resistor (RS) and leave 200 mV for slope compensation:
RS =
VP - 0.2 V
» 49.9 W
IPEAK
´ 1.1
a2
(87)
Select a standard resistor for RS:
RS = 48.7 W
(88)
Estimate power loss for RS:
2
PRS
æI
ö
= ç PRMS1 ÷ ´ RS » 0.03 W
è a2 ø
(89)
Calculate maximum reverse voltage (VDA) on DA:
VDA = VP
DCLAMP
» 29.8 V
1 - DCLAMP
(90)
Estimate DA power loss (PDA):
PDA =
POUT ´ 0.6 V
» 0.01W
VINMIN ´ h ´ a2
(91)
Calculate RS reset resistor RRE:
Resistor RRE is used to reset the current sense transformer CT.
RRE = 100 ´ RS = 4.87kW
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Resistor RLF and capacitor CLF form a low pass filter for the current sense signal (Pin 15). For this design
we chose the following values. This filter has a low frequency pole (fLFP) at 482 kHz. This should work for
most applications but maybe adjusted to suit individual layouts and EMI present in the design.
RLF = 1kW
(93)
CLF = 330pF
(94)
fLFP =
1
= 482kHz
2pf ´ RLF ´ CLF
(95)
The UCC28950 VREF output (Pin 1) needs a high frequency bypass capacitor to filter out high frequency
noise. This pin needs at least 1 µF of high frequency bypass capacitance (CBP1). Please refer to figure 1
for proper placement.
CBP1 = 1 mF
(96)
The voltage amplifier reference voltage (Pin 2, EA +) can be set with a voltage divider (RA, RB), for this
design example we are going to set the error amplifier reference voltage (V1) to 2.5 V. Select a standard
resistor value for RB and then calculate resistor value RA.
UCC28950 reference voltage:
VREF = 5 V
(97)
Set voltage amplifier reference voltage:
V1 = 2.5 V
RB = 2.37kW
RA =
(98)
(99)
RB ´ (VREF - V1)
V1
= 2.37kW
(100)
Voltage divider formed by resistor RC and RI are chosen to set the DC output voltage (VOUT) at Pin 3 (EA-).
Select a standard resistor for RC:
RC = 2.37kW
(101)
Calculate RI:
RI =
Rc ´ (VOUT - V1)
V1
» 9kW
(102)
Then choose a standard resistor for RI:
RI =
16
Rc ´ (VOUT - V1)
V1
» 9.09kW
(103)
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Compensating the feedback loop can be accomplished by properly selecting the feedback components
(RF, CZ and CP). These components are placed as close to pin 3 and 4 as possible of the UCC28950.
Calculate load impedance at 10% load (RLOAD):
RLOAD
VOUT 2
=
= 2.4 W
POUT ´ 0.1
(104)
Approximation of control to output transfer function (GCO(f)) as a function of frequency:
GCO (f ) »
æ 1 + 2pj ´ f ´ ESRCOUT ´ COUT ö
R
DVOUT
= a1´ a2 ´ LOAD ´ ç
÷´
RS
DVC
è 1 + 2pj ´ f ´ RLOAD ´ COUT ø
1
æ S(f ) ö
S(f )
1+
+ç
÷
2p ´ fPP è 2p ´ fPP ø
2
(105)
Double pole frequency of GCO(f):
fPP »
fs
= 50kHz
4
(106)
Angular velocity:
S(f ) = 2p ´ j ´ f
(107)
Compensate the voltage loop with type 2 feedback network. The following transfer function is the
compensation gain as a function of frequency (GC(f)). Please refer to Figure 1 for component placement.
GC (f ) =
DVC
=
DVOUT
2pj ´ f ´ RF ´ CZ + 1
æ 2pj ´ f ´ CZ ´ CP ´ RF
ö
2pj ´ f ´ (CZ + CP )RI ç
+ 1÷
CZ + CP
è
ø
(108)
th
Calculate voltage loop feedback resistor (RF) based on crossing the voltage (fC) loop over at a 10 of the
double pole frequency (fPP).
fPP
= 5kHz
10
RI
RF =
» 27.9kW
æ fPP ö
GCO ç
÷
è 10 ø
fC =
(109)
(110)
Select a standard resistor for RF.
RF » 27.4kW
(111)
Calculate the feedback capacitor (CZ) to give added phase at crossover.
CZ =
1
f
2 ´ p ´ RF ´ C
5
» 5.8nF
(112)
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Select a standard capacitance value for the design.
CZ = 5.6nF
(113)
Put a pole at two times fC.
CP =
1
» 580pF
2 ´ p ´ RF ´ fC ´ 2
(114)
Select a standard capacitance value for the design.
CP = 560pF
(115)
Loop gain as a function of frequency (TV(f)) in dB.
TV dB(f ) = 20log (GC (f ) ´ GCO (f ) )
(116)
Plot theoretical loop gain and phase to graphically check for loop stability (Figure 4). The theoretical loop
gain crossed over at roughly 3.7 kHz with a phase margin of greater than 90 degrees.
NOTE: It is wise to check your loop stability of your final design with transient testing and/or a
network analyzer and adjust the compensation (GC(f)) feedback as necessary.
180
60
135
40
90
20
45
0
0
-20
-45
-40
-90
-60
TvdB(f)
-135
?Tv(f)
-180
-80
100
Phase in Degrees
Gain in dB
Tv(f) Frequency Response
80
1000
10000
100000
Frequency in Hz
Figure 4. Loop Gain (TVdB(f)), Loop Phase (θTV(f))
To limit over shoot during power up the UCC28950 has a soft-start function (SS, Pin 5) which in this
application was set for a soft start time of 15 ms (tSS).
t ss = 15ms
CSS =
18
(117)
t SS ´ 25 mA
» 123nF
V1 + 0.55
UCC28950 600-W, Phase-Shifted, Full-Bridge Application Report
(118)
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Select a standard capacitor for the design.
CSS = 150nF
(119)
This application note presents a fixed delay approach to achieving ZVS from 100% load down to 50%
load. When the converter is operating below 50% load the converter will be operating in valley switching.
In order to achieve zero voltage switching on switch node of QBd, the turn-on (tABSET) delays of FETs QA
and QB needs to be initially set based on the interaction of LS and the theoretical switch node
capacitance. The following equations are used to set tABSET initially.
Equate shim inductance to two times COSS capacitance:
2p ´ fRLS =
1
2p ´ fR ´ (2 ´ COSS _ QA _ AVG )
(120)
Calculate tank frequency:
fR =
1
2p LS ´ (2 ´ COSS _ QA _ AVG )
(121)
Set initial tABSET delay time and adjust as necessary.
NOTE: The 2.25 factor of the tABSET equation was derived from empirical test data and may vary
based on individual design differences.
t ABSET =
2.25
» 346ns
f R ´4
(122)
The resistor divider formed by RDA1 and RDA2 programs the tABSET, tCDSET delay range of the UCC28950.
Select a standard resistor value for RDA1.
NOTE:
tABSET can be programmed between 30 ns to 1000 ns.
RDA1 = 8.25kW
(123)
The voltage at the ADEL input of the UCC28950 (VADEL) needs to be set with RDA2 based on the following
conditions.
If tABSET > 155 ns set VADEL = 0.2 V, tABSET can be programmed between 155 ns and 1000 ns:
If tABSET ≤ 155 ns set VADEL = 1.8 V, tABSET can be programmed between 29 ns and 155 ns:
Based on VADEL selection, calculate RDA2:
RDA 2 =
RDA1 ´ VADEL
» 344 W
5V - VADEL
(124)
Select the closest standard resistor value for RDA2:
RDA 2 = 348 W
(125)
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Recalculate VADEL based on resistor divider selection:
VADEL =
5 V ´ RDA 2
= 0.202 V
RDA1 + RDA 2
(126)
Resistor RDELAB programs tABSET:
RDELAB =
(t ABSET - 5ns) (0.15 V + VADEL ´ 1.46) ´ 103 1
´
´
» 30.4kW
ns
5
1A
(127)
Select a standard resistor value for the design:
RDELAB = 30.1kW
(128)
NOTE: Once you have a prototype up and running it is recommended you fine tune tABSET at light
load to the peak and valley of the resonance between LS and the switch node capacitance. In
this design the delay was set at 10% load. Please refer to Figure 5.
Set t
ABSET
at resonant tank Peak and Valley
t ABSET = t 1 - t 0
t ABSET = t 4 - t 3
QB d
QA g
Miller Plateau
tMILLER = t
QB
2
- t1
Miller Plateau
g
t MILLER = t 5 - t 4
t0 t1 t2
t3 t4 t5
Figure 5. tABSET to Achieve Valley Switching at Light Loads
20
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The initial starting point for the QC and QD turn on delays (tCDSET) should be initially set for the same delay
as the QA and QB turn on delays (Pin 6). The following equations program the QC and QD turn-on delays
(tCDSET) by properly selecting resistor RDELCD (Pin 7).
t ABSET = t CDSET
(129)
Resistor RDELCD programs tCDSET:
RDELCD =
(t ABSET - 5ns) (0.15 V + VADEL ´ 1.46) ´ 103 1
´
´
» 30.4kW
ns
5
1A
(130)
Select a standard resistor for the design:
RDELCD = 30.1kW
(131)
NOTE: Once you have a prototype up and running it is recommended to fine tune tCDSET at light load.
In this design the CD node was set to valley switch at roughly 10% load. Please refer to
Figure 6. Obtaining ZVS at lighter loads with switch node QDd is easier due to the reflected
output current present in the primary of the transformer at FET QD and QC turnoff/on. This is
because there was more peak current available to energize LS before this transition,
compared to the QA and QB turnoff/on.
Set t
t CDSET
QD
QC
=t
1
CDSET
t CDSET
- t0
=t
4
- t3
d
g
Miller Plateau
t MILLER
QD
at resonant tank Peak and Valley
=t
2
-t1
Miller Plateau
g
t MILLER
t 0 t1 t 2
=t
5
-t4
t 3 t4 t 5
Figure 6. tCDSET to Achieve Valley Switching at Light Loads
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There is a programmable delay for the turnoff of FET QF after FET QA turnoff (tAFSET) and the turnoff of
FET QE after FET QB turnoff (tBESET). A good place to set these delays is 50% of tABSET. This will ensure
that the appropriate synchronous rectifier turns off before the AB ZVS transition. If this delay is too large it
will cause OUTE and OUTF not to overlap correctly and it will create excess body diode conduction on
FETs QE and QF.
t AFSET = tBESET = t ABSET ´ 0.5
(132)
The resistor divider formed by RCA1 and RCA2 programs the tAFSET and tBESET delay range of the UCC28950.
Select a standard resistor value for RCA1.
NOTE:
tEFSET and tBESET can be programmed between 32 ns to 1100 ns.
RCA1 = 8.25kW
(133)
The voltage at the ADELEF pin of the UCC28950 (VADELEF) needs to be set with RCA2 based on the following
conditions.
If tAFSET < 170 ns set VADEL = 0.2 V, tABSET can be programmed between 32 ns and 170 ns:
If tABSET > or = 170 ns set VADEL = 1.7 V, tABSET can be programmed between 170 ns and 1100 ns:
Based on VADELEF selection, calculate RCA2:
RCA 2 =
RCA1 ´ VADELEF
» 4.25kW
5 V - VADELEF
(134)
Select the closest standard resistor value for RCA2:
RCA 2 = 4.22kW
(135)
Recalculate VADELEF based on resistor divider selection:
VADELEF =
5 V ´ RCA 2
= 1.692 V
RCA1 + RCA 2
(136)
The following equation was used to program tAFSET and tBESET by properly selecting resistor RDELEF.
RDELEF =
22
(t AFSET ´ 0.5 - 4ns ) ´ (2.65 V - VADELEF ´ 1.32 )´ 103 ´
ns
5
UCC28950 600-W, Phase-Shifted, Full-Bridge Application Report
1
» 14.1kW
1A
(137)
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A standard resistor was chosen for the design.
RDELEF = 14kW
(138)
Resistor RTMIN programs the minimum duty cycle on time (tMIN) that the UCC28950 (Pin 9) can demand
before entering burst mode. If the UCC28950 controller tries to demand a duty cycle on time of less than
tMIN the power supply will go into burst mode operation. Please see the UCC28950 data sheet for details
regarding burst mode. For this design we set the minimum on time to 100 ns.
tMIN = 100ns
(139)
The minimum on time is set by selecting RTMIN with the following equation.
RTMIN =
(tMIN - 15ns) ´ 103
» 12.9kW
6.6s
(140)
A standard resistor value is then chosen for the design.
RTMIN = 13kW
(141)
There is a pin that is provided for setting up the converter switching frequency (Pin 10). The frequency can
be selected by adjusting timing resistor RT.
æ
ö
6 WHz
ç 2.5 ´ 10 V
W÷
- ÷ ´ (VREF - 2.5 V )´ 2.5 ´ 103 » 60kW
RT = ç
fS
V÷
ç
2
è
ø
(142)
Select a standard resistor for the design.
RT = 61.9kW
(143)
The UCC28950 also provides slope compensation for peak current mode control (Pin 12). This can be set
by setting RSUM with the following equations. The following equations will calculate the required amount of
slope compensation (VSLOPE) that is needed for loop stability.
NOTE: The change in magnetizing current on the primary dILMAG contributes to slope compensation.
DILMAG =
VIN (1 - DTYP )
LMAG ´ fs
= 234mA
(144)
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To help improve noise immunity VSLOPE is set to have a total slope that will equal 10% of the maximum
current sense signal (0.2 V) over one inductor switching period.
VSLOPE1 = 0.2 V ´ fS =
0.04 V
ms
(145)
æ dILOUT
ö
ç a1´ 2 - dILMAG ÷ ´ RS ´ fS
1mV
ø
=
VSLOPE2 = è
ms
a2 ´ (1 - DTYP )
(146)
If VSLOPE2 < VSLOPE1 set VSLOPE = VSLOPE1
If VSLOPE2 ≥ VSLOPE1 set VSLOPE = VSLOPE2
RSUM
2.5 V ´ 103 W
=
» 125.4kW
VSLOPE ´ 0.5 ms
(147)
Select a standard resistor for RSUM.
RSUM = 127kW
(148)
To increase efficiency at lighter loads the UCC28950 is programmed (Pin 12, DCM) under light load
conditions to turn off the synchronous FETs on the secondary side of the converter (QE and QF). This
threshold is programmed with resistor divider formed by RE and RG. This DCM threshold needs to be set
at a level before the inductor current goes discontinues. The following equation sets the synchronous
rectifiers to turnoff at roughly 15% load current.
VRS
æ POUT ´ 0.15 DILOUT
+
ç
VOUT
2
è
=
a1´ a2
ö
÷ ´ RS
ø
= 0.29 V
(149)
Select a standard resistor value for RG.
RG = 1kW
(150)
Calculate resistor value RE.
RE =
RG (VREF - VRS )
VRS
» 16.3kW
(151)
Select a standard resistor value for this design
RE = 16.9kW
24
(152)
UCC28950 600-W, Phase-Shifted, Full-Bridge Application Report
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Figure 7. Daughter Board Schematic
NOTE: Black triangles designate not populated.
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+
+
+
+
+
+
+
www.ti.com
Figure 8. Power Stage Schematic
NOTE: It is recommended to use an RCD clamp to protect the output synchronous FETs from over
voltage due to switch node ringing. This RCD clamp is formed by diodes D4, D6 and resistor
R6, R8 and R9 and capacitor C1 in the power stage schematic, .
26
UCC28950 600-W, Phase-Shifted, Full-Bridge Application Report
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600W UCC28950 Effiency
96%
95%
94%
93%
92%
91%
90%
89%
88%
87%
86%
370V Efficiency
85%
390V Efficiency
84%
410V Efficiency
83%
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
Figure 9. 600-W Phase Shifted Full Bridge Efficiency
Full bridge gate drives and primary switch nodes (QBd and QDd) at VIN = 390 V, IOUT = 5 A.
Valley Switching
QB d/Q4
d
QD d/Q3
Valley Switching
d
Q3
Q4 g
QB/Q4 = off
QB/Q4 = on
g
QD/Q3 = off
QD/Q3 = on
QC/Q2 = on
QC/Q2 = off
0V
QA/Q1 = on
QA/QB = off
t ABSET
t D Slight Delay after t
ABSET
0V
t CDSET
Figure 10. Q4g Q4d, VIN = 390 V, IOUT = 5 A
t D Slight Delay after t
CDSET
before Miller Plateau
before Miller Plateau
Figure 11. Q3g Q3d, VIN = 390 V, IOUT = 5 A
NOTE: The gate drives look slightly different than Figure 5 and Figure 6. This is because they were
driven with 1:2 gate drive transformers instead of 1:1. At 10% load the primary switch nodes
were valley switching
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Full bridge gate drives and switch nodes at VIN = 390 V, IOUT = 10 A
Valley Switching
QB d /Q4 d
QD d /Q3 d
Q4 g
Q3 g
ZVS
QB/Q4 = off
0V
QA/Q1 = on
QA/QB = off
tABSET
tD
Slight Delay after t
before Miller Plateau
0V
QD/Q3 = off
QB/Q4 = on
QD/Q3 = on
0V
QC/Q2 = on
QC/Q2 = off
t CDSET
ABSET
tD
Slight Delay after t
before Miller Plateau
CDSET
Figure 13. Q3g Q3d, VIN = 390 V, IOUT = 10 A
Figure 12. Q4g Q4d, VIN = 390 V, IOUT = 10 A
NOTE: Switch node QBd/Q4d is valley switching and node QDd/Q3d has achieved ZVS. Please refer
to Figure 12 and Figure 13. It is not uncommon for switch node QDd/Q3d to obtain ZVS
before QBd/Q4d. This is because during the QDd/Q3d switch node voltage transition, the
reflected output current provides immediate energy for the LC tanking at the switch node.
Where at the QBd/Q4d switch node transition the primary has been shorted out by the high
side or low side FETs in the H bridge. This transition is dependent on the energy stored in LS
and LLK to provide energy for the LC tanking at switch node QBd/Q4d making it take longer to
achieve ZVS.
Full bridge gate drives and switch nodes at VIN = 390 V, IOUT = 25 A
ZVS Achieved
QB d/Q4 d
QD d/Q3
d
Q3 g
ZVS
Q4 g
QB/Q4 = off
QD/Q3 = off
QB/Q4 = on
QD/Q3 = on
0V
0V
QA/Q1 = on
QA/QB = off
QC/Q2 = on
t ABSET
QC/Q2 = off
t CDSET
Figure 14. Q4g Q4d, VIN = 390 V, IOUT = 25 A
Figure 15. Q3g Q3d, VIN = 390 V, IOUT = 25 A
NOTE: When the converter is running at 25 A both switch nodes are operating into zero voltage
switching (ZVS). It is also worth mentioning that there is no evidence of the gate miller
plateau during gate driver switching. This makes sense because the voltage across the drain
and source of FETs QA through QD has already transition before the gate drives have
transitioned.
28
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Full bridge gate drives and switch nodes at VIN = 390 V, IOUT = 50 A
ZVS
QB d /Q4 d
QD d/Q3 d
Q3 g
ZVS
Q4 g
QB/Q4 = off
QD/Q3 = off
QB/Q4 = on
QD/Q3 = on
0V
0V
QA/Q1 = on
QA/QB = off
QC/Q2 = on
t ABSET
QC/Q2 = off
t CDSET
Figure 16. Q4g Q4d, VIN = 390 V, IOUT = 25 A
Figure 17. Q3g Q3d, VIN = 390 V, IOUT = 25 A
NOTE: ZVS was maintained from 50% to 100% output power.
References
1. Bill Andreycak, “Phase Shifted, Zero Voltage Transition Design Considerations and the UC3875 PWM
Controller” Unitrode Application Note SLUA107, 9/5/1999
2. Lazlo Balogh, “Design and Application Guide for High Speed MOSFET Gate Drive” Unitrode Power
Supply Design Seminar 1400, Topic 2, 2001
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