Voltage Source Converter (VSC)
IEEE PES Winnipeg Tutorial
December 18, 2012
Randy Wachal
Manitoba HVDC Research Centre
rww@hvdc.ca
Acknowledgements:
NSERC Power System Simulation Chair program at
University of Manitoba ..
MHRC Staff
Dr. Farid Mosallat and Juan Carlos Garcia
Cigre DC Grid Working Groups
B4-55, 56 57 58 59 and 60 ..
ABB Siemens and Alstom Grid
VSC Tutorial
VSC Converter Theory Basics
VSC Control and Modelling
VSC system simulations
Start –up; DC Fault
DC Grid Test Case Cigre B4-57/58
Introductory Basics: LCC Single line
VSC:
Single Line Diagram Format
Symmetrical HVDC Monopole
VSC: Unsymmetrical Monopole
VSC: Bipole Configuration
LCC - VSC Comparison
LCC HVDC
Mature Technology
“Requires” strong ac system
Lower losses 0.8% per converter
Requires 60% reactive power
AC-DC system interactions
Harmonics
Commutations failure
Special Transformers
Multi terminal operation possible but hard
Controlled DC Current to zero (Idref=0)
Dc voltage + to - as alpha changes
rectifier to inverter
VSC HVDC
Rapid growth
Helps ac system
Control real and reactive power
independently
Losses reducing 1.1- 1.2% per converter
No Commutation failure
Less Special Transformers
Flexible Dispatch
Harmonics with MMC no issue
DC Grid (multi-terminal) possible
DC voltage is a constant polarity
DC Line faults are problematic
S1
Multi Terminal
For LCC:
Rect α < 90 Vdc +ve
INV α > 90 Vdc -ve
To change Conv 2 from
Rect to Inv you must
flip the thyristor
For VSC:
Power Flow is controlled
by control signals only
S4
S3
f
f
f
S2
VSC Technology is very flexible
VSC technology can control two variables together
real power and reactive power
VSC can generate an AC Waveform….
Black start or island mode possible
Many dispatch options available
•
•
Real Power set point
•
•
Use power to control DC voltage Vdc
In island mode : use power to control frequency
•
Reactive Power Q set point
•
to control Vac magnitude
islanded Mode…
Use Q
Other control targets are possible..
in or out
+ or -
in or out + or –
Grid or
VSC Operation
We tend to think of LCC from AC side to rectifier and generate Dc voltage
For VSC ; think from the DC side.. Assume DC Capacitors are charged
The capacitor voltages are used to piecewise build ac voltage
We the ac voltage waveform and the ac system voltage
now we can transfer energy to charge Dc capacitor(s)
Transfer P & Q across Reactor
Use DC capacitor voltage
(Ud) to build an ac Voltage
waveform Uc
Exchange P based on δ
•↑ δ P into Converter Ud ↑
•↓ δ P from Converter Ud ↓
Exchange Q based on |Uc|
•↑ |Uc| Q flows into system
•↓ |Uc| Q flows from system
History of VSC Development:
ABB, Siemens and Alstom Grid
• VSC Rapid Growth and continue to change
• Many projects but few projects have the same
design
• An MMC type configuration appears to be the
“winner” but many marketplace has variations
• Not unlike LCC technology 25 years ago
• The Final VSC configuration is not decided
• and may never occur.
PWM Based VSC
ABB slide
½ Bridge Multi Module Converter MMC
Siemens Slide
½ Bridge MMC with PWM CTLC
Full Bridge MMC
IET ACDC 2012 Tutorial Gole - Wachal
One possible Hybrid Configuration
IET ACDC 2012 Tutorial Gole - Wachal
VSC Control and Modelling
• Control system organization
• Look at impact of diode in configuration
• High Level Control
D Q controller development
Development of Voltage reference signals based on dispatched
orders
Lower level control
Valve fire pulses (IGBT firing pulses)
Capacitor energy balancing
Models For VSC MMC system
EMT and RMS transient (Dynamic and loadflow) type
models are required
Lots of VSC configurations to consider
• PWM based (all series devices in Valve switch together)
• ½ bridge MMC
• ½ bridge MMC with PWM (cascaded two level converter CTLC)
• Full bridge MMC
• Hybrid mixtures of series valves, ½ and full bridges
Traditional ‘emt’ solution methods not effective
Emt simulation speed is dependent on number of electrical
nodes (size of simulation matrix)
MMC configurations increase electrical nodes
exponentially
•
•
LCC and PWM VSC
• 6 nodes per 3 phase valve
• entire valve arm (xx series devices) switch together
MMC
• Valve may have 400 levels (each switching independent)
• 400*6 = 2400 nodes for 1 converter
Compare 6 to 2400
……
simulation issue is evident …
VSC System Control Model & Levels
•
Dispatch
•
•
•
•
•
Power Set or Dc voltage (grid mode)
Ac voltage reference or MVar set (grid mode)
Frequency reference (P) and Ac Voltage (Q) (island
mode)
Other P& Q strategy
High Level Controls
•
•
•
•
•
What is the target of Converter ?
Based on dispatch set points (Inputs)
Droop setting to allow autonomous control
d-q control will generate Vref a, b and c (outputs)
Voltage and current limits applied
Lower Level Controls
• Inputs Vref signals
• Valve specific configurations
(½ bridge MMC, ½ bridge MMC with PWM, full bridge, etc.)
• Capacitor balancing algorithm(s)
• Circulating current suppression algorithm(s)
• Generates gate pulses and the ac waveforms
Control Hierarchy
Natural separation occurs Higher Lower level
Controls
Regardless of Dispatch Orders Higher Level
controls develop
Vabc Ref
Vref A Vref B and Vref C outputs
Regardless of converter valve implementation
Lower Level controls use the VREF inputs to
generate the gate pulses to produce
Va Vb and Vc
Lower level controls are unique for valve
topology and will have ancillary control
- Capacitor balance
- Circulating current suppression
Impact for VSC System Models
•
•
Dispatch and Higher Levels Controls remain same regardless of
Converter implementation
• Generic or public domain models
• Vendor specific (IP) models
Lower Level Controls unique for different types of converter
• Different Power electronics and control algorithm
• Different Capacitor balance algorithm
• Different Circulation Current suppression algorithm
• Generic or public domain models
• Vendor specific (IP) models
• Different level of details for each lower level models
• Full emt , detailed equivalent, firing pulse RMS
From a Simulation Study Point View
Choose the appropriate Lower Level Model for your study … How ???
New Model Techniques required
Computationally efficient model developed by Simulation Chair University of
Manitoba
Thevenin
equivalent
+
i1l
-
Vc1
Ic1
+
N1
-
FP13
Vc13
Ic13
FP2
Vc2
+
-
Ic2
-
Ic14
+
FP3
+
FP15
-
Vc3
Ic3
-
Vc15
Ic15
+
FP4
Vc4
+
FP14
Vc14
FP16
Vc16
-
Ic4
-
Ic16
+
FP5
Vc5
Ic5
+
-
-
FP17
Vc17
Ic17
+
FP6
+
FP18
-
Vc6
Ic6
-
Vc18
Ic18
+
FP7
Vc7
+
FP19
Vc19
-
Ic7
-
Ic19
+
FP8
+
FP20
-
Vc8
Ic8
-
Vc20
Ic20
+
FP9
+
FP21
-
Vc9
Ic9
-
Vc21
Ic21
+
N1
FP1
+
FP10
Vc10
+
FP22
Vc22
-
Ic10
-
Ic22
+
FP11
Vc11
Ic11
+
-
-
FP23
Vc23
Ic23
+
FP12
+
FP24
-
Vc12
Ic12
-
Vc24
Ic24
100’s of nodes into
2 nodes
Ic(38)
Req
+
Veq
-
Vc(38)
TU(38)
TL(38)
It makes possible the
simulation of Multilevel
converters with only a
PC
n2l
U. N. Gnanarathna, A. M. Gole, and R. P.Jayasinghe, "Efficient Modeling of Modular Multilevel HVDC
Converters (MMC) on Electromagnetic Transient Simulation Programs," IEEE Transactions on Power Delivery,
vol.26, no.1, pp.316-324, Jan. 2011
Start up Concerns
Initial Energization
• Transformer
• MMC Capacitors (Precharge capacitors to 1.41*ELL via diodes)
• DC Line or DC Cable
Use start-up resistor to limit current.
Short resistor with by pass switch
Deblock pulses Conv 1 and then Conv 2
Ramp power to desired setpoints
Session 3: VSC system start up
T1
T2
1000 km
P=900 MW
Z
SCR: 2.5
Z
SCR: 2.5
P control
Vdc control
@ 900 MW
@ 640 kV
P=966 MW
Session 3: VSC system start up
De-block
Terminal 1
Close
AC brk
Bypass
Pre R
De-block
Terminal 2
Ramp up
Start up sequence
(kA)
10.0
Iac T2 (Sending end)
-10.0
Edc2 (+) (Vdc control end)
(kV)
700
-100
Idc 2 -> 1
(kA)
7.0
-1.0
(-) P1
P2
(MW)
1.00k
-0.10k
[s]
0.00
0.50
1.00
1.50
2.00
2.50
Summary Issues VSC Start-up
During start-up energization of both transformers and all
capacitors therefore Larger Inrush
Inrush resistor commonly added with bypass switch
Diodes: with no firing pulse and diodes will conduct
resulting in a Dc voltage
VDC=1.41 peak of Vac L-L
(charge capacitors and line (or Cable)
rww1
DC Line Fault
VSC scheme with overhead line (based on Caprivi)
no Dc Fast (4 msec) breaker installed
Resonant DC Breaker (50-75 msec installed)
On DC fault.. Block firing pulse.. MMC capacitors cannot
discharge into line but diodes will continue to commutate
and feed DC fault (as 6P LCC rectifier)
Open AC breaker .. Remove 6p rectifier diode current
DC line will discharge slowly.. Based on the R/L circuit of the
Dc line will keep the post fault DC current present for seconds up to
a couple of minutes .
A dc switching action is required to allow Dc fault recovery
JCGA1
DC Line Fault - restart
Fault
detection
Valve
blocking
AC Brk
open
Fault
clearing
(MRTB)
MRTB
reclose
AC Brk
close
Valve
deblock
Ramp up
Start up sequence
(kA)
10.0
Iac T2 (Sending end)
-10.0
DC fault current
(kA)
12.0
-2.0
Edc2 (+) (Vdc control end)
(kV)
700
-100
Idc 2 -> 1
(kA)
7.0
-1.0
(MW)
1.0k
(-) P1
P2
-0.2k
[s]
2.60
2.80
3.00
3.20
3.40
3.60
3.80
4.00
Summary for VSC Dc Line Faults
• Pulse Blocking removes discharge of capacitors quickly
• AC breaker is required to open to remove 6P diode
current.
• For a weak ac system .. DC fault draws fault current from
AC bus. dc fault = ac fault
• Post fault residual dc current requires resonant Dc breaker
• For recovery inrush.. MMC capacitors are already charged
• Power ramp rate is determined by ac system strength not
dc controls .
Neutral Return
•
•
•
•
•
Eliminate ground currents
Increased line losses
DC voltage offset at
remote station.. Requires
more dc insulation
Neutral current can be
controlled to zero by
bipole controller
During pole outage, the
pole conductor can be
used to reduce losses.
DC Grid Modelling Test System (B4-58)
B4-57 has developed T-line and
cable parameters for test case
A base PSCAD and EMPT-RV test
cases are available.
Models are changing ..
Test Case alternatives
• Monopole
• Bipole with neutral return
• Bipole with ground/ sea
electrodes.
Thank you…
Questions?