S. Allison, M. Browne, B. Dalesio, J. Dusatko,
R. Fuller, A. Gromme, D. Kotturi, P. Krejcik, S.
Norum, D. Rogind, H. Shoaee, M. Zelazny
Oct 12, 2006
Facility Advisory Committee Meeting
Patrick Krejcik pkr@slac.stanford.edu

Overview – HW Block Diagram and Reqts
Progress since April, 2006
Outstanding Issues
Task List
The Event Definition system - EDEFs
Oct 12, 2006
Facility Advisory Committee Meeting
Patrick Krejcik pkr@slac.stanford.edu

~
Linac main drive line
119 MHz
FIDO
360 Hz
SLC
MPG
P
N
E
T
SLC events m
P
P
N
E
T
S
T
B
Oct 12, 2006
Facility Advisory Committee Meeting
E
V
G
LCLS events
I
O
C
I
O
C
E
V
R
TTL
LCLS Digitizer
LLRF
BPMs
Toroids
Cameras
SLC Trigs
TTL-NIM convert.
GADCs
Old klystrons
Patrick Krejcik pkr@slac.stanford.edu

Modulator
Triggers
Hardware Block Diagram
Early 2007 Commissioning
Existing
Control
System
RF
Timing
Beam Path
Timing
Crate
360Hz
E
Fiducial V
G
119MHz
Clock
F
A
N
1
F
A
N
2
P
N
E
T
I
O
C
Acq and
Calibration
BPM FEE
Triggers
E I
BPM
Crates
V
R
O
C
Acc and
Standby
Triggers
PADs and PACs
LLRF
Crate
E
V
R
1
E
V
R
2
E
V
R
3
I
O
C
Future
MPS
Beam Rate,
Beam Path
Fiber Distribution:
Timing Pattern, Timestamp, Event Codes
Triggers Triggers
Trigger
Laser
Steering
Crate
F
A
N
3
E
V
R
1
C
A
M
I
O
C
1
…
1
...
E
V
R
8
C
A
M
8
I
O
C
8
Oct 12, 2006
Facility Advisory Committee Meeting
Profile
Monitor
Crate
F
A
N
4
E
V
R
1
C
A
M
1
C
A
M
2
…
1
I
O
C
…
E
V
R
4
C
A
M
7
C
A
M
8
I
O
C
4
Patrick Krejcik pkr@slac.stanford.edu

Micro-Research Finland Oy
Event Generator (EVG-200) Event Receiver (EVR-200-RF)
SFP transceiver
• Optical signal to
EVRs (fan-outs)
RF input
• Event clock divided from RF
• EVG-200: /4, /5, ... /12
Line syncronisation input
360 Hz
Oct 12, 2006
Facility Advisory Committee Meeting
SFP transceiver
• Optical signal from
EVG (or fan-out)
Patrick Krejcik pkr@slac.stanford.edu
Recovered RF output
Programmable outputs
• 5 TTL level
• 2 LVPECL level
External trigger input

Event Generator IOC :
Send out proper event codes at 360Hz based on:
PNET pattern input (beam code and bits that define beam path and other conditions)
Add LCLS conditions such as BPM calibration on off-beam pulses , diagnostic pulse etc.
Future – event codes also based on new MPS and user input
Send out system timestamp with encoded pulse ID from PNET
Send out event pattern to be used by SLC-aware IOCs and conditional logic on the EVR IOCs
Manage user-defined beam-synchronous acquisition measurement definitions
Check for match between user meas definitions and input PNET pattern at
360Hz and tag matches in outgoing pattern
MPS Algorithm Processors and Master Pattern Generator (MPG):
Rateliming logic including beam “burst” and “single-shot” modes
Send out PNET pattern to EVG and CAMAC controls (for modulator triggers)
Oct 12, 2006
Facility Advisory Committee Meeting
Patrick Krejcik pkr@slac.stanford.edu

Event Receiver IOC:
Receive event pattern 8.3 msec before corresponding pulse
Set trigger delays, pulse widths, and enable/disable
Set some trigger delays and enable/disables at 120Hz max based on the incoming pattern and local conditions on the IOC – list of conditions under determination
Perform beam-synchronous acquisition based on tags set by EVG in the pattern
Perform beam-synchronous acquisition for the SLC-aware IOC based on the PNET part of the event pattern
Set event code per trigger (triggering done in HW when event code received)
Process pre-defined records when specific event codes are received
Oct 12, 2006
Facility Advisory Committee Meeting
Patrick Krejcik pkr@slac.stanford.edu

# EVRs = 31 (mostly PMC )
# IOCs with EVRs = 28
# EVR Fanouts = 4
# Hardware Triggers = 120 and counting
All TTL except 2 NIM triggers for QDCs
Most require short cables
(except LLRF)
EVR with clock not yet available
All acquisition electronics using either internal clocks, clock output from the RF timing system, or other external clocks
Oct 12, 2006
Facility Advisory Committee Meeting
Patrick Krejcik pkr@slac.stanford.edu

Hardware problems identified by CPE engineers:
119MHz clock input – no divide-by-one available on
EVG, special chip added to board to provide direct clock input
Cannot use EVG AC-line input for 360Hz fiducial without mod to FPGA (or design a special EVG transition module)
Procurement finished
Two test stands equipped and available
Identified EVR IOCs and triggers needed for early commissioning
Added more people of various disciplines (all parttime) to timing team
Oct 12, 2006
Facility Advisory Committee Meeting
Patrick Krejcik pkr@slac.stanford.edu

Way behind in all tasks, significantly:
Interface control document
Hardware testing – jitter, fanout testing, etc
Software testing
Beam-synch-acq implementation just begun
Cabling plans and documentation
Triggering conditions (when to trigger and which event code and delay to use) are pushing more logic from EVG IOC to EVR IOC
Need a full-time timing system engineer
Oct 12, 2006
Facility Advisory Committee Meeting
Patrick Krejcik pkr@slac.stanford.edu

Finish hardware bench testing
Finish PMC-EVR driver
EVG sequence RAM programming at 360Hz
EVR trigger attribute change logic at 120Hz
Event pattern records and timestamp distribution on the EVR IOCs
Finish cabling plans and documentation
Installation in sector 20 and 21
Oct 12, 2006
Facility Advisory Committee Meeting
Patrick Krejcik pkr@slac.stanford.edu

Beam Synchronous Acquisition
Integration with SLC-aware BPM acquisition
Oct 12, 2006
Facility Advisory Committee Meeting
Patrick Krejcik pkr@slac.stanford.edu

EVG Event Definitions (EDEFs) are used for BSA
EDEF includes:
Beam code
SLC PNET bits and LCLS Modifier bits
# to average, # to measure
Client or System name
Permanent System EDEFs are always active
1Hz, 10Hz, Full, Single Shot, Feedback
Available to all clients
Client applications may reserve a Client EDEF
Client receives EDEF # assignment on demand
Client proceeds to fill out definition, then sets “GO”
Oct 12, 2006
Facility Advisory Committee Meeting
Patrick Krejcik pkr@slac.stanford.edu

Slots for
20 possible
Event
Definitions allocated
Oct 12, 2006
Facility Advisory Committee Meeting
Patrick Krejcik pkr@slac.stanford.edu
User
Defs
Fixed
Defs

Synthesizing the EVG Broadcast
MPG PNET bits
0x0
0x0 inclusion mask exclusion mask
0x0
0x0
EDEF
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
Upon match, set
“event bit(s)”
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
MPG PNET bits
0x0 0x0 0x0
0x0 0x0 0x0
LCLS bits
0x0 0x0
0x3 0x0
0x0
0x0
0x0
0x0
EVG to EVR
Broadcast
Oct 12, 2006
Facility Advisory Committee Meeting
EVR IOCs
Patrick Krejcik pkr@slac.stanford.edu

User interface for defining an
Event Def
Oct 12, 2006
Facility Advisory Committee Meeting
Patrick Krejcik pkr@slac.stanford.edu

EVG broadcast at 360Hz checks all active EDEFs against PNET / LCLS
Modifier pattern
For every pattern to EDEF match, EVG sets appropriate “event bit”
EVR IOC BSA device data is fanned out to 20 buffers
Identified by its EDEF # or system name
Enabled/disabled for acquisition by its “event bit”
Oct 12, 2006
Facility Advisory Committee Meeting
Patrick Krejcik pkr@slac.stanford.edu

20 Buffers
One for each EDEF
2800 samples per buffer
Oct 12, 2006
Facility Advisory Committee Meeting
Patrick Krejcik pkr@slac.stanford.edu