An Efficient Test Relaxation
Technique for Synchronous
Sequential Circuits
Aiman El-Maleh and Khaled Al-Utaibi
King Fahd University of Petroleum & Minerals
Dhahran, Saudi Arabia
{aimane, alutaibi}@ccse.kfupm.edu.sa
Outline






2
Motivation
Problem Definition & Test Relaxation Techniques
Proposed Technique
Selection Criteria
Experimental Results
Conclusions
Motivation

With today’s technology, complete systems with
millions of transistors are built on a single chip.

Increasing complexity of systems-on-a-chip and
its test data size increased cost of testing.

Cost of automatic test equipment increases with
increase in speed, channel capacity, and
memory.

Need for test data reduction is imperative
3
• Test compaction
• Test compression
Motivation


Test compression and compaction techniques
significantly improved based on a relaxed test.
Compression techniques:
• LFSR-Reseeding require the test vectors to be partially
•
specified [Koenemann, ETS 91] [Hellebrand, ITS 92]
Run-length coding benefits from partially specified test
sets by specifying don't care values in a way that
reduces number of runs [Jas, ITC 98] [Chandra, VTS 2000,
VTS2001] [El-Maleh, VTS 2001, ICCD 2002]

Compaction:
• In overlapping techniques, increasing the number of
X's in a test set reduces conflicts when merging two
test sequences [Roy,88]
4
Problem Definition & Test Relaxation
Techniques

Given a synchronous sequential circuit and a fully
specified test set, generate a partially specified test set
that maintains the same fault coverage as the fully
specified one while maximizing the number of unspecified
bits.

Dynamic ATPG Compaction

Bitwise-Relaxation
•
•

5
Test for every bit of the test set whether changing it to an X
reduces the fault coverage or not.
O(nm) fault simulation runs, where n is the width of one test
vector, and m is the number of test vectors
Test Relaxation Techniques for Combinational circuits
•
[El-Maleh, VTS 2002][Kajihara, ICCAD 2001]
Proposed Test Relaxation Technique:
General Behavior

At every time frame, t, all logic values necessary to
detect a newly detected fault marked required.

Required logic values are justified backwards
towards primary inputs and/or memory-elements.

Any primary input not marked as required during
the justification process is relaxed.

Required values on the memory-elements are
justified when time frame, t-1, is processed.
6
Proposed Test Relaxation Technique:
Relaxation Process

Fault Simulation: For every test vector t in the given
test set,
• fault simulate the circuit under that test vector
• store faults newly detected in the current time frame
• store faults propagating to the next time frame

Backward Justification: Starting from the last time
frame down to the first one,
• for every fault, f, that could not be justified in the previous
•
7
time frame justify fault-free/faulty values necessary to
propagate f
for every fault f newly detected in the current frame justify
fault-free/faulty values necessary to detect f
Proposed Test Relaxation Technique:
Example

Consider the circuit shown below under two test
vectors: ti = 01 and ti+1 = 00.

Assume that the only newly detected fault is A/1
A/1
A
B
0 /1
G1
0 /1
A
B
1
G2
0
G5
G4
x
x
0
G1
0
0
0
G4
0 /1
x
G3
ti
8
1 /0
G2
G5
G3
ti+1
1 /0
Proposed Test Relaxation Technique:
Example

Justify fault-free/faulty values necessary to detect
A/1 starting from ti+1
A
B
0 /1
G1
0 /1
A
B
1 /1
G2
0 /0
G5
G4
x /x
G1
A/1
x0 //00
x0 //00
x0 //00
ti
x /x
1 /0
G2
G5
G4
0 /1
G3
9
x /x
0 /1
x
/x
G3
ti+1
1 /0
Proposed Test Relaxation Technique:
Example

Since G5 is a memory-element, its fault-free/fault
value can not be justified in ti+1

Thus, the justification process will continue in ti
A
B
0 /1
G1
0 /1
A
B
1x/1
/1
G2
0 /0
G5
G4
x /x
G1
x /0
x /0
x /0
ti
x /x
1 /0
G2
G5
G4
0 /1
G3
10
x /x
x /x
G3
ti+1
1 /0
Selection Criteria in Value Justification

When justifying a controlling value through the
inputs of a given gate, there could be more than
one choice.

Priority is given to inputs already marked required

Otherwise, cost functions are used to guide the
selection.

Cost functions give a relative measure on the
number of primary inputs required to justify a
given value.
11
Selection Criteria

Let g be an AND Gate with i inputs and F(g) fanout
branches [El-Maleh, VTS 2002]

Regular Cost Functions
Creg0 ( g ) = min Creg0 ( i )
i

min C fan0 (i )
C fan1 ( g ) =
i
F ( g)
Weighted-Sum Cost Functions
C (g) = A . C
( g ) + B . C fan 0 ( g )
C (g) = A . C
( g ) + B . C fan1 ( g )
0
1
12
i
Fanout-based Cost Functions
C fan0 ( g ) =

Creg1 ( g ) =  Creg1 ( i )
reg 0
reg 1
C fan1 ( i )
i
F ( g)
Selection Criteria: Example
Creg0(A) = 1
A
Creg0(B) = 1
B
Creg0(C) = 1
G1
0
0
G3
G2
0
C
Cfan0(A) = 1
A
Cfan0(B) = 0.5
B
Cfan0(C) = 1
13
0
C
0
G1
0
0
0
0
G3
G2
0
0
0
Selection Criteria: Sequential Circuits

Controllability values in one time frame depend on
values in the current and previous frames.

Controllability values computed in an iterative
manner starting from the first time frame.

Iterative computation of controllability over several
time frames may cause regular cost function to grow
much faster than fanout-based cost function.

Effect of the second cost function in the weighted
sum may become negligible.
14
Selection Criteria: Sequential Circuits
1
(1, 0.5)
G4
Time Frame 1
Time Frame 2
(2, 1.5)
(5, 2.5)
1
G1
1
(4, 3)
1
1
G3
G1
(4, 1.5)
1
G4
G2
G3
G2
1
(2, 1.5)
(5, 2.5)
Time Frame 10
(1535, 10.5)
1
(1535, 9.5)
G4
G1
1
1
1
G2
1
(1535, 10.5)
15
(3070, 11)
G3
(10, 5)
1
1
1
1
1
1
Selection Criteria: Reconvergent Fanouts

The huge difference between the two costs is due to
the reconverging fanout branches of the flip-flop.

Regular cost of a flip-flop with reconverging fanout
branches should be adjusted to reduce the
difference between the two costs

This can be done as follows.
• Let g be a flip-flop with n fanout branches.
• Assume that m out of the n fanout branches reconverge at
•
16
some gate in the circuit, then
The regular cost of every one of these branches equals to
the regular cost of g divided by m.
Selection Criteria: Reconvergent Fanouts

The three branches of stem B reconverge at gate
G3

Thus, the regular cost of these branches will be
divided by 3
C1 = 1
C1 = v
A
1
B 1
C1 = v/3 +1
C1 = 2v/3 +1
G1
G2
C1 = v+1
1
G3
17
Selection Criteria: Actual vs. General
Values

Assuming general values on the gate inputs when
computing the cost functions is less accurate than
using the actual logical values.
C1=3
1
1
1
1
G1
C1=3
=1
0
G2
1
1
1
G3
C1=2
18
1
G4
1
Experimental Results

Experiments were performed on a number of
ISCAS89 benchmarks.

Test sets generated by HITEC.

Comparison between proposed technique and
bitwise-relaxation technique in terms of percentage
of X’s and CPU time.

Experiments on Cost Functions.
19
Proposed Tech. Vs Bitwise-Relaxation

The difference in the percentage of X’s ranges between
1% and 7%.

Average difference is about 3%.
Proposed Tech. vs Bitwise-Relaxation Tech.
Percentage of X's
Bitwise-Relaxation
Proposed Technique
100
80
60
40
20
0
1
20
2
6
5
4
3
Benchmark Circuits
7
8
Proposed Tech. Vs Bitwise-Relaxation
Circuit
Name
21
CPU Time (sec)
Proposed
Bitwise
Technique
Relaxation
S1423
1.750
943
S1488
2.417
12553
S1494
3.100
13146
S3271
8.033
87726
S3330
5.633
115585
S3384
2.533
16549
S4863
7.800
162894
S5378
20.35
218137
Effect of cost functions on % of X’s
Circuit
Name
A=0
B=1
A=1
B=0
A=1
B=10
A=1
B=30
A=1
B=70
A=1
B=90
s1423
37.882 50.863 57.059 62.431 63.686
64.039 63.020
s1488
44.448 72.457 56.624 66.218 69.968
71.571 72.244
s1494
43.515 72.661 57.410 66.687 70.502
72.098 72.741
s3271
57.361 78.860 82.060 82.017 82.033
81.892 81.908
s3330
66.548 85.251 84.805 85.446 85.407
85.506 85.506
s3384
69.247 71.703 77.755 77.799 77.784
77.755 77.755
s4863
72.114
82.038 81.735
s5378
77.788 85.692 82.130
AVG
22
A=0
B=0
78.934 83.406 82.846 82.582
84.110
85.053
85.094 86.056
58.613 74.553 72.656 75.944 77.127
77.499 77.621
Conclusions

A new test relaxation technique for synchronous
sequential circuits.

Proposed technique is faster than the bitwiserelaxation method by several order of magnitude.

Percentage of X’s obtained close to those obtained
by bitwise-relaxation for most of the circuits.

Does not do any optimization in selecting POs for
fault detection. This will be investigated in future
work.
23