Computing Bounds on Dynamic Power
Using Fast Zero-Delay Logic Simulation
Jins Davis Alexander
Vishwani D. Agrawal
Department of Electrical and Computer Engineering
Auburn University, Auburn, AL 36849
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Objective
• Determine power dissipation in a digital CMOS
circuit.
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Components of Power
• Dynamic
– Signal transitions
• Logic activity
• Glitches
– Short-circuit
• Static
– Leakage
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Ptotal = Pdyn + Pstat
= Ptran + P + Pstat
sc
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Power Per Transition
isc
R
VDD
Dynamic Power
Vo
Vi
= CLVDD2/2 + Psc
CL
R
Ground
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Number of Transitions
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Problem Statement
• Problem - Estimate dynamic power consumed in
a CMOS circuit for:
– A set of input vectors
– Delays subjected to process variation
• Challenge - Existing method, Monte Carlo
simulation, is expensive.
• Find a lower cost solution.
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Bounded (Min-Max) Delay Model
IV
FV
EA
•
•
•
•
LS
FV
EA
LS
EA is the earliest arrival time
LS is the latest stabilization time
IV is the initial signal value
FV is the final signal value
EAsv=-∞
Driving
value
EAdv
LSsv=∞
LSdv
EAdv=-∞
Sensitizing
value
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IV
EAsv
[d, D]
LSdv=∞
LSsv
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Example
d
d
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D
D
8
Finding Number of Transitions
3
14
7
5
8
10
12
10 12
14
2, 2
[mintran,maxtran]
[0,2]
3
EA
5
EA
14
6
LS
[0,4]
1, 3
EA
17
LS
17
LS
where mintran is the minimum number of transitions and
maxtran the maximum number of transitions.
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Estimating maxtran
• Nd: First upper bound is the largest number of transitions that
can be accommodated in the ambiguity interval given by the
gate delay bounds and the (IV, FV) output values.
• N: Second upper bound is the sum of the input transitions as
the output cannot exceed that. Further modify it as
N=N–k
where k = 0, 1, or 2 for a 2-input gate and is determined by
the ambiguity regions and (IV, FV) values of inputs.
• The maximum number of transitions is lower of the two upper
bounds:
maxtran = min (Nd, N)
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First Upper Bound, Nd
Nd = 1 + (LS – EA)/d
└
┘
d
d, D
EA
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LS
11
Examples of maxtran
Nd = 1 + (18 – 3)/0 = ∞
N=4+4=8
maxtran=min (Nd, N) = 8
Nd = 1 + (23 – 6)/3 = 6
N=4+4=8
maxtran=min (Nd, N) = 6
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Example: maxtran With Non-Zero k
[n1 = 6]
EAsv = - ∞
[n1 + n2 – k = 8 ] ,
LSdv = ∞
EAdv
EAsv = - ∞
LS
where k = 2
LSsv
[n2 = 4]
EAdv
EA
LSdv = ∞
LSsv
[6]
[6+4–2=8]
[4]
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Simulation Methodology
• d, D = nominal delay ± Δ%
• Three linear-time passes for each input vector:
 First pass: zero delay simulation to determine initial and
final values, IV and FV, for all signals.
 Second pass: determines earliest arrival (EA) and latest
stabilization (LS) from IV, FV values and bounded gate
delays.
 Third pass: determines upper and lower bounds, maxtran
and mintran, for all gates from the above information.
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Zero-Delay Vs. Event-Driven
Simulation
9000
8000
Execution Time (secs)
7000
6000
5000
Event driven simulation
4000
Min-Max Simulation
3000
2000
1000
0
357
514
880
1161 1667 2290 2416 3466
Number of gates
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Maximum Power
• Monte Carlo Simulation vs. Min-Max analysis for circuit C880.
100 sample circuits with + 20 % variation were simulated for
each vector pair (100 random vectors).
R2 is coefficient of
determination, equals 1.0 for
ideal fit.
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Minimum Power
R2 is coefficient of
determination, equals
1.0 for ideal fit.
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Average Power
10
9
Monte Carlo average power (mW)
R2 = 0.9527
8
7
6
5
4
3
R2 is coefficient of
determination, equals
1.0 for ideal fit.
2
1
0
0
2
4
6
8
10
MIN - MAX m ean pow er (m W)
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C880: Monte Carlo vs. Bounded Delay
Analysis
80000
1000 Random Vectors, 1000 Sample Circuits
70000
Frequency
60000
50000
40000
30000
20000
10000
2.
13
7
2.
74
74
3.
35
79
3.
96
83
4.
57
88
5.
18
92
5.
79
96
6.
41
01
7.
02
05
7.
63
1
8.
24
14
8.
85
19
9.
46
23
10
.0
73
10
.6
83
11
.2
94
1.
52
65
0
Power (mW)
Monte Carlo Simulation
Bounded Delay Analysis
Min Power
(mW)
Max Power
(mW)
CPU Time
(secs)
Min Power
(mW)
Max Power
(mW)
CPU Time
(secs)
1.42
11.59
262.7
1.35
11.89
0.3
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Power Estimation Results
• Circuits implemented using TSMC025 2.5V CMOS library , with standard
size gate delay of 10 ps and a vector period of 1000 ps. Min-Max values
obtained by assuming ± 20 % variation. The simulations were run on a
UNIX operating system using a Intel Duo Core processor with 2 GB RAM.
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Conclusion
• Bounded delay model allows power estimation
method with consideration of uncertainties in
delays.
• Analysis has a linear time complexity in number
of gates and is an efficient alternative to the
Monte Carlo analysis.
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