ELEC 5270/6270 Fall 2007
Low-Power Design of Electronic Circuits
Test Power
Vishwani D. Agrawal
James J. Danaher Professor
Dept. of Electrical and Computer Engineering
Auburn University, Auburn, AL 36849
vagrawal@eng.auburn.edu
http://www.eng.auburn.edu/~vagrawal/COURSE/E6270_Fall07/course.html
Copyright Agrawal, 2007
ELEC6270 Fall 07, Lecture 9
1
Power Considerations in Design
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A circuit is designed for certain function. Its design
must allow the power consumption necessary to
execute that function.
Power buses are laid out to carry the maximum
current necessary for the function.
Heat dissipation of package conforms to the
average power consumption during the intended
function.
Layout design and verification must account for
“hot spots” and “voltage droop” – delay, coupling
noise, weak signals.
Copyright Agrawal, 2007
ELEC6270 Fall 07, Lecture 9
2
Testing Differs from Functional
Operation
Other chips
System
inputs
System
outputs
VLSI chip
system
Functional outputs
Functional inputs
Copyright Agrawal, 2007
ELEC6270 Fall 07, Lecture 9
3
Basic Mode of Testing
Packaged or unpackaged
device under test (DUT)
DUT output for
comparison with
expected response
stored in ATE
VLSI chip
Test vectors:
Pre-generated
and stored in
ATE
Copyright Agrawal, 2007
Clock
Power
Automatic Test Equipment (ATE):
Control processor, vector memory,
timing generators, power module,
response comparator
ELEC6270 Fall 07, Lecture 9
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Functional Inputs vs. Test Vectors
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Functional inputs:
Test vectors:
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Functionally meaningful
signals
Generated by circuitry

Restricted set of inputs
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May have been
optimized to reduce
logic activity and power
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Copyright Agrawal, 2007
ELEC6270 Fall 07, Lecture 9
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Functionally irrelevant
signals
Generated by software
to test modeled faults
Can be random or
pseudorandom
May be optimized to
reduce test time; can
have high logic activity
May use testability logic
for test application
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An Example
VLSI chip in system operation
3-bit random
vectors
Binary to
decimal
converter
8-bit
1-hot
VLSI chip
vectors
system
VLSI chip under test
High activity
8-bit
test vectors
from ATE
Copyright Agrawal, 2007
VLSI chip
ELEC6270 Fall 07, Lecture 9
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Comb. Circuit Power Optimization
Given a set of test vectors
 Reorder vectors to minimize the number of
transitions at primary inputs

01010101
00110011
00001111
11 transitions
Combinational circuit
(tested by exhaustive
vectors)
01111000
Rearranged vector set 00110011
00011110
Copyright Agrawal, 2007
produces 7 transitions
ELEC6270 Fall 07, Lecture 9
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Reducing Comb. Test Power
Original tests:
V1 V2 V3 V4 V5
1 1 0 0 0
1 0 1 0 0
1 0 1 0 1
1 0 1 1 1
10 input transitions
Reordered tests:
V1 V3 V5 V4 V2
1 0 0 0 1
1 1 0 0 0
1 1 1 0 0
1 1 1 1 0
5 input transitions
Copyright Agrawal, 2007
1
V1
3
4
V2
3
3
2
2
V4
1
V3
1
V5
2
Traveling salesperson problem (TSP)
finds the shortest distance closed path
(or cycle) to visit all nodes exactly once.
But, we need an open loop solution.
ELEC6270 Fall 07, Lecture 9
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Open-Loop TSP
1
3
V1
0
V0
0
0
0
2
3
V4
4
V2
2
1
3
V3
1
V5
2
0
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Add a node V0 at distance 0 from all other nodes.
Solve TSP for the new graph.
Delete V0 from the solution.
Copyright Agrawal, 2007
ELEC6270 Fall 07, Lecture 9
9
Traveling Salesperson Problem
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A. V. Aho, J. E. Hopcroft anf J. D. Ullman, Data
Structures and Algorithms, Reading,
Massachusetts: Addison-Wesley, 1983.
E. Horowitz and S. Sahni, Fundamentals of
Computer Algorithms, Computer Science Press,
1984.
B. R. Hunt, R. L. Lipsman, J. M. Rosenberg, K.
R. Coombes, J. E. Osborn and G. J. Stuck, A
Guide to MATLAB for Beginners and
Experienced Users, Cambridge University
Press, 2006.
Copyright Agrawal, 2007
ELEC6270 Fall 07, Lecture 9
10
Scan Testing
Primary
inputs
Primary
outputs
Combinational
logic
Scan-out
SO
Scan enable
SE
Scan-in
SI
Copyright Agrawal, 2007
Scan
flipflops
D
D
SI
1
0
SO
mux
D’
DFF
D’
SE
ELEC6270 Fall 07, Lecture 9
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Example: State Machine
Functional state
transitions
S5
S4
Functional transitions
S1
S2
S3
Reduced power state encoding
S1 = 000
S2 = 011
S3 = 001
S4 = 010
S5 = 100
Copyright Agrawal, 2007
State transition
Comb. State input
changes/clock
000 → 001
1
000 → 100
1
011 → 010
1
001 → 011
1
010 → 000
1
100 → 010
2
ELEC6270 Fall 07, Lecture 9
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Scan Testing of State Machine
Primary
inputs
Combinational
logic
Primary
outputs
Scan transitions
State
transition
Per clock
state
changes
100 → 010
2
FF=0
010 → 101
3
FF=1
101 → 010
3
Scan-out
100
FF=0
Scan-in
010
Copyright Agrawal, 2007
ELEC6270 Fall 07, Lecture 9
13
Low Power Scan Flip-Flop
SO
SI
D
DFF
1
D’
SI
0
mux
D
mux
SO
DFF
D’
SE
SE
Scan FF cell
Copyright Agrawal, 2007
Low power scan FF cell
ELEC6270 Fall 07, Lecture 9
14
Built-In Self-Test (BIST)
Linear feedback shift register (LFSR)
BIST
Controller
Pseudo-random patterns
Circuit under test (CUT)
Circuit responses
Multiple input signature register (MISR)
Clock
C. E. Stroud, A Designer’s Guide to Built-In Self-Test, Boston: Springer,
2002.
Copyright Agrawal, 2007
ELEC6270 Fall 07, Lecture 9
15
Test Scheduling Example
R1
R2
M1
M2
R3
R4
A datapath
Copyright Agrawal, 2007
ELEC6270 Fall 07, Lecture 9
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BIST Configuration 1: Test Time
M1
MISR1
LFSR2
Test power
LFSR1
M2
T2: test for M2
T1: test for M1
MISR2
Test time
Copyright Agrawal, 2007
ELEC6270 Fall 07, Lecture 9
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BIST Configuration 2: Test Power
M1
MISR1
LFSR2
Test power
R1
M2
T1: test for M1
T2: test for M2
MISR2
Test time
Copyright Agrawal, 2007
ELEC6270 Fall 07, Lecture 9
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Testing of MCM and SOC
Test resources: Typically registers and
multiplexers that can be reconfigured as test
pattern generators (e.g., LFSR) or as output
response analyzers (e.g., MISR).
 Test resources (R1, . . .) and tests (T1, . . .)
are identified for the system to be tested.
 Each test is characterized for test time,
power dissipation and resources it requires.

Copyright Agrawal, 2007
ELEC6270 Fall 07, Lecture 9
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Resource Allocation Graph
T1
R1
R2
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T2
R3
T3
R4
T4
R5
T5
R6
ELEC6270 Fall 07, Lecture 9
R7
T6
R8
R9
20
Test Compatibility Graph (TCG)
T1
(2, 100)
T6
(1, 100)
T2
(1,10)
T5
(2, 10)
T3
(1, 10)
Power
Test time
T4
(1, 5)
Pmax = 4
Copyright Agrawal, 2007
ELEC6270 Fall 07, Lecture 9
Tests that form a
clique can be performed
concurrently.
21
Test Scheduling Algorithm

Identify all possible cliques in TCG:
 C1
= {T1, T3, T5}
 C2 = {T1, T3, T4}
 C3 = {T1, T6}
 C4 = {T2, T5}
 C5 = {T2, T6}

Break up clique sets into power
compatible sets (PCS), that satisfy the
power constraint.
Copyright Agrawal, 2007
ELEC6270 Fall 07, Lecture 9
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Test Scheduling Algorithm . . .
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PCS (Pmax = 4), tests within a set are ordered for
decreasing test length:
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C1 = {T1, T3, T5} → (T1, T3), (T1, T5), (T3, T5)
C2 = {T1, T3, T4} → (T1, T3, T4)
C3 = {T1, T6} → (T1, T6)
C4 = {T2, T5} → (T2, T5)
C5 = {T2, T6} → (T2, T6)
Greedy solution:
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Expand PCS into subsets of decreasing test lengths. Each subset is
an independent test session, consisting of tests that can be
concurrently applied.
Select test sessions, starting from the shortest-time PCS, to cover all
tests.
Remove redundant PCS from the selected sessions.
Copyright Agrawal, 2007
ELEC6270 Fall 07, Lecture 9
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TS Algorithm: Cover Table
Test session
T1
(T1, T3, T4)
X
(T1, T5)
X
(T1, T6)
X
(T2, T6)*
T2
(T3, T4)
T4
X
X
T5
T6
X
X
X
X
X
X
100
X
100
10
X
10
10
X
(T4)*
100
X
X
(T5)*
Length
100
X
(T3, T5)
(T2, T5)
T3
10
5
•Dropped as redundant sessions.
•Selected sessions are (T3,T4), (T2, T5) and (T1, T6). Test time = 120.
Copyright Agrawal, 2007
ELEC6270 Fall 07, Lecture 9
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An ILP Solution to Cover Problem
Test session
Integer 0,1 variable T1
(T1, T3, T4)
S1
X
(T1, T5)
S2
X
(T1, T6)
S3
X
(T2, T6)
S4
(T3, T5)
S5
(T2, T5)
S6
(T3, T4)
S7
(T5)
S8
(T4)
S9
Constraints:
Copyright Agrawal, 2007
T2 T3 T4 T5 T6 Length
X
X
100
X
X
X
X
X
100
X
100
X
100
X
10
X
10
X
10
X
X
10
5
S1+S2+S3 ≥ 1
implies T1 is covered
S4+S6 ≥ 1
implies T2 is covered
similar constraints to cover T3, T4, T5 and T6
ELEC6270 Fall 07, Lecture 9
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An ILP Solution (Cont.)
Test session
Si: Integer 0,1 variable
T1
(T1, T3, T4)
S1
X
(T1, T5)
S2
X
(T1, T6)
S3
X
(T2, T6)
S4
(T3, T5)
S5
(T2, T5)
S6
(T3, T4)
S7
(T5)
S8
(T4)
S9
9
Minimize ∑ (Li × Si)
i=1
Copyright Agrawal, 2007
T2
T3
T4
X
X
T5 T6 Length, Li
100
X
X
X
X
X
100
X
100
10
X
10
10
X
ILP solution:
X
X
X
X
100
10
5
S3=S6=S7 = 1
S1=S2=S4=S5=S8=S9 = 0
Test length = 120
ELEC6270 Fall 07, Lecture 9
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A System Example: ASIC Z*
RAM 2
Time=61
Power=241
ROM 1
Time=102
Power=279
RAM 3
Time=38
Power=213
ROM 2
Time=102
Power=279
Random logic 1, time=134, power=295
Random logic 2, time=160, power=352
RAM 4
Time=23
Power=96
RAM 1
Time=69
Power=282
Reg. file
Time = 10
Power=95
*Y. Zorian, “A Distributed Control Scheme for Complex VLSI Devices,”
Proc. VLSI Test Symp., April 1993, pp. 4-9.
Copyright Agrawal, 2007
ELEC6270 Fall 07, Lecture 9
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Test Scheduling for ASIC Z
1200
Reg. file
Power limit = 900
Power
900
600
RAM 2
RAM 3
Random logic 1
ROM 1
300
RAM 1
Random logic 2
ROM 2
RAM 4
0
200
300
400
Test time
331
R. M. Chou, K. K. Saluja and V. D. Agrawal, “Scheduling Tests for VLSI
Systems under Power Constraints,” IEEE Trans. VLSI Systems, vol. 5,
no. 2, pp. 175-185, June 1997.
Copyright Agrawal, 2007
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ELEC6270 Fall 07, Lecture 9
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References
N. Nicolici and B. M. Al-Hashimi, PowerConstrained Testing of VLSI Circuits,
Boston: Springer, 2003.
 E. Larsson, Introduction to Advanced
System-on-Chip Test Design and
Optimization, Springer 2005.

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ELEC6270 Fall 07, Lecture 9
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