Design and Implementation of VLSI Systems
(EN1600)
lecture10
[sources: Weste/Addison Wesley – Rabaey/Pearson]
S. Reda EN160 SP’08
SPICE introduction
• SPICE, a Simulation Program with Integrated Circuit
Emphasis
SPICE card
SPICE deck
• We will use SmartSPICE by SimuCAD (http://www.engin.brown.edu/vpn)
S. Reda EN160 SP’08
SPICE Intro
•
•
•
•
•
SPICE is case insensitive
Cards beginning with a dot (.) are control cards
Cards beginning with a * are comment cards
The last card must be .end
Each card in the netlist must begin with a letter
indicating its type
S. Reda EN160 SP’08
SPICE circuit elements
Letter
R
C
L
K
V
I
M
D
Q
W
X
E
G
H
F
S. Reda EN160 SP’08
Circuit Element
Resistor
Capacitor
Inductor
Mutual Inductor
Independent voltage source
Independent current source
MOSFET
Diode
Bipolar transistor
Lossy transmission line
Subcircuit
Voltage-controlled voltage source
Voltage-controlled current source
Current-controlled voltage source
Current-controlled current source
Units
S. Reda EN160 SP’08
Letter
a
Unit
atto
Magnitude
10-18
f
p
n
femto
pico
nano
10-15
10-12
10-9
u
m
k
x
micro
mili
kilo
mega
10-6
10-3
103
106
g
giga
109
Voltage sources
• DC Source
– Vdd vdd gnd 2.5
• Piecewise Linear Source
(time, voltage) pairs
– Vin in gnd pwl 0ps 0 100ps 0 150ps 1.8 800ps 1.8
• Pulsed Source
– Vck clk gnd PULSE 0 1.8 0ps 100ps 100ps 300ps 800ps
PULSE v1 v2 td tr tf pw per
td
tr
pw
tf
v2
v1
S. Reda EN160 SP’08
per
RC response
*rc.sp
.option post
Vin in gnd pwl 0ps 0 100ps 0 150ps 1.8 800ps 1.8
R1 in out 2k
C1 out gnd 100f
.tran 20ps 800ps
.plot v(in) v(out)
.end
Tutorial movie at http://ic.engin.brown.edu/classes/EN160S07/spice.avi
S. Reda EN160 SP’08
NMOS I-V characteristics
Mname drain gate source body type W=<width> L=<length>
.option post
.include 'tsmc-180.txt'
.temp 70
.option scale=90n
Vgs g gnd 0
Vds d gnd 0
M1 d g gnd gnd NMOS W=2 L=2
.dc Vds 0 1.8 0.05 sweep vgs 0 1.8 0.3
.plot i(m1)
.end
S. Reda EN160 SP’08
NMOS I-V characteristics
S. Reda EN160 SP’08
Inverter transient analysis
.option post
.include 'tsmc-180.txt'
.temp 70
.option scale=90n
for diffusion
capacitance
calculations
Vdd vdd gnd 1.8
M1 d g gnd gnd NMOS W=4 L=2 AS=20 PS=18 AD=20 PD=18
M2 d g vdd vdd PMOS W=8 L=2 AS=40 PS=26 AD=40 PD=26
Vgs g gnd PULSE 0 1.8 0ps 10ps 10ps 100ps 220ps
.tran 20ps 440ps
.end
S. Reda EN160 SP’08
Inverter transient analysis
bootstrapping
S. Reda EN160 SP’08
Measuring propagation delay
* delay measurement
.param SUPPLY=1.8
a
.param H=4
.option scale=90nm
.include 'tsmc-180.txt'
.temp 70
.option post
.global vdd gnd
.subckt inv a y N=4 P=8
Ignoring
M1 y a gnd gnd NMOS W='N' L=2
diffusion
M2 y a vdd vdd PMOS W='P' L=2
capacitance!!
.ends
Vdd vdd gnd 'SUPPLY'
Vin a gnd PULSE 0 'SUPPLY' 0ps 100ps 100ps 500ps 1000ps
X1 a b inv N=4 P=8
X2 b gnd inv N=16 P=32
.tran 1ps 1000ps
.measure tpdr TRIG v(a) VAL='SUPPLY/2' FALL=1 TARG v(b) VAL='SUPPLY/2' rise=1
.end
S. Reda EN160 SP’08
Measuring propagation delay
83.7ps
S. Reda EN160 SP’08
Leakage current/threshold voltage
.option post
.include 'tsmc-180.txt'
.temp 70
.option scale=90n
Vgs g gnd 0
Vds d gnd 1.8
M1 d g gnd gnd NMOS W=2 L=2
.dc Vgs 0 1.8 0.05 s
.plot i(m1)
.end
S. Reda EN160 SP’08
Leakage current/threshold voltage
Vgs
S. Reda EN160 SP’08
Integration with L-Edit
Objective: extract the SPICE circuit
description from Tanner L-Edit and then
simulate it in SPICE to verify that the layout
is indeed performing the required
functionality
S. Reda EN160 SP’08
Extract your design into SPICE to simulate
and verify it
S. Reda EN160 SP’08
Verify your inverter DC characteristics in
SPICE
simulate and plot
Fix your SPICE input file first
S. Reda EN160 SP’08
Summary
 Ideal transistor characteristics
 Non-ideal transistor characteristics
 Inverter DC transfer characteristics
 Simulation with SPICE and integration with L-Edit
S. Reda EN160 SP’08