Methodology for HW/SW
Co-verification in SystemC
Part of
HW/SW Codesign of Embedded
Systems Course (CE 40-226)
Winter-Spring 2001
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Topics
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Introduction
Design Flow
Processor Models
Implementation: 8051
Conclusion
Reference:
L. Semeria & A. Ghosh, “Methodology for Hardware/Software Co-Verification in
C/C++”, in ASP-DAC 2000
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Methodology for HW/SW
Co-verification in SystemC
Introduction
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Introduction
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Shrinking device sizes => all digital
components on a single chip
Software is traditionally fully tested after
hardware is fabricated => long TTM
Integrating HW and SW earlier in the design
cycle => better TTM
Co-simulation involves
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Simulating a processor model along with custom
hw (usually described in HDL)
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Introduction (cont’d)
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Heterogeneous co-simulation
environments (C-VHDL or C-Verilog)
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RPC or another form of inter-process
communication between HW and SW
simulators
High overhead due to high data
transmission between the simulators
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Introduction (cont’d)
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Recently HW synthesis techniques from
C/C++ are more investigated
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Eliminates C to HDL translation for synthesis =>
higher productivity
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Reduces translation time
Eliminated bugs introduced during this translation
Easier verification by
 re-using testbenches developed during system
validation phase
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enabling hw/sw co-verification and performance
estimation at very early stages of design
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Introduction (cont’d)
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In this paper, authors present
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How hw/sw co-verification is performed in
a C/C++ based environment
hw and sw are both described in C++
(SystemC)
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Other C/C++ based approaches: PTOLEMY, and
CoWare N2C,
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Methodology for HW/SW
Co-verification in SystemC
Design Flow
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Design Flow
Functional Specification
of the system
Mapping
Architectural Specification
Refinement of Individual
hw and sw blocks
Synthesis for hw blocks
Compilation for sw blocks
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Methodology for HW/SW
Co-verification in SystemC
Processor Models
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Processor Models
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Bus Functional Model (BFM)
Instruction-Set Simulator (ISS)
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Bus Functional Model (BFM)
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Encapsulates the bus functionality of a
processor
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Can execute bus transactions on the processor bus
(with cycle accuracy)
Cannot execute any instructions
Hence,
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BFM is an abstract model of processor that can be
used to verify how a processor interacts with its
peripherals
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Bus Functional Model (cont’d)
At early stages of the design
C/C++
SW
SW
SW
BFM
HW
HW
HW
In the later stages of the design
Assembly
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ISS
SW
SW
SW
BFM
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HW
HW
HW
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Design of the BFM
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Is a SystemC module
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Ports of the module correspond to the pins of the
processor
Methods of the module provide a PI (programming
interface) to the software/ISS
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They depend on the type of communication between hw
and sw
BFM functionality is modeled as a set of
concurrent FSMs
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Memory-mapped IO
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Peripherals are located on a portion of CPU
address space
BFM provided methods
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void bfm_read_mem(sc_address, sc_data *, int)
void bfm_write_mem(sc_address, sc_data, int)
SW (without ISS) calls these functions to
access hw
When using ISS, SW calls device drivers.
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Device drivers are run in the ISS and at proper
time call these functions
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Interrupt-driven IO
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An interrupt controller is implemented in BFM
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In case of an interrupt, the corresponding ISR
is called
ISRs are registered by these BFM methods
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It is made sensitive to the CPU interrupt lines
void bfm_register_handler(sc_interrupt,
void (*handler)(sc_interrupt))
Interrupts may be masked/change behavior
using configuration ports
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Configuration ports,
Access to internal registers
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CPUs often have configuration ports for
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BFM methods to access these registers
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Multiple modes of operation
Multiple timers/serial modes
Masked interrupts
etc
void bfm_read_reg(sc_register, sc_data*, int nb)
void vfm_write_reg(sc_register, sc_data, int nb)
BFM usually doesn’t model general-purpose
registers of the CPU
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Timers and Serial Ports
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Normally, controllers for these timers and
serial ports are implemented within BFM
They are configured using configuration ports
and registers
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Previously mentioned functions are used
They may issue interrupts to the CPU
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Performance Estimation
Functions
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BFM keeps track of bus transactions
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Can report number of clock cycles spent for each
bus transaction
Reporting can be taken after each transaction or
at the end of simulation
Tracking is enabled using
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void bfm_enable_tracing(int level)
level is used to define multiple levels of tracking
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Even debug information can be produced by the BFM
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HW/SW Synchronization
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Normal BFM methods are blocking
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A flag can be set in the BFM to make SW
execute in parallel with HW
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SW execution is suspended until the bus
transaction is done
This essentially serialized SW and HW execution
i.e. BFM methods return immediately
SW can wait for a specific number of clock
cycles by calling
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void bfm_idel_cycle(int)
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Processor Model
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Bus Functional Model (BFM)
Instruction-Set Simulator (ISS)
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Instruction-Set Simulator
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ISS: a processor model capable of simulating
execution of instructions
Different types of ISS for different purposes
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Usage 1: Verification of applications written in
assembly-code
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For fastest speed: translate target assembly instructions
into host processor instructions
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Is not cycle-accurate. Specially for pipelined and
superscalar architectures
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ISS (cont’d)
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Different types of ISS … (cont’d)
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Usage 2: Verification of timing and interface
between system components
 Used in conjunction with a BFM
 ISS should be timing-accurate in this usage
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ISS often works as an emulator
For performance estimation usage, ISS is to provide
accurate cycle-counting
To have certain speed improvements, ISS should
provide necessary hooks (discussed later)
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Integrating an ISS and a BFM
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ISS + BFM => complete processor model
Cycle-accurate ISS + (already cycle-accurate)
BFM => cycle-accurate processor model
Typical units of an ISS
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Fetch, Decode, Execute
Execute unit performs calls to BFM to access
memory or configuration registers
Fetch unit performs calls to BFM to read
instructions
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Integrating an ISS
and a BFM (cont’d)
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For more complex architectures (pipelined,
superscalar)
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Other units must be modeled
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Cache, prefetch, re-order buffer, issue, …
Many units may need to call BFM functions
ISS may need to provide BFM with certain
memory-access functions (discussed later)
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Techniques to
speedup simulation
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Reduce activity on memory bus
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Most applications: 95% of memory traffic is
attributed to instruction and data fetches
Memory access previously verified? => no need to
simulate it again during co-simulation
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Put instruction memory (and/or data memory) insideISS
What to do for external devices accessing instr/data
memory?
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BFM must be configured to recognize them and call
corresponding ISS method to access instr/data
ISS must provide the above methods
ISS must implement a memory map, where certain addresses
are directly accessed, while others through bus cycles
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Techniques to
speedup simulation (cont’d)
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Turn off clocks on modules
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All clocked components activate by clock edge
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Most of time the component is not addressed =>
activation and simulation (even a limited part of each
process) is wasteful => turn off clocks when not
necessary
How to do it?
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BFM generated bus clock, only when devices on the bus
are addressed
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Methodology for HW/SW
Co-verification in SystemC
Implementation: 8051
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Implementation: 8051
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Implementation of Synopsys dw8051 BFM
and cycle-accurate ISS
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Synopsys dw8051:
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8-bit microcontroller
Configurable, fully synthesizable, reusable macrocell
industry standard for simple embedded application
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smartcard, cars, toys, …
Many IO modes
SFR (Specific Function Register) bus
interrupt ports (expandable to 12)
up to 2 serial ports, in 4 different modes of operation
up to 2 timers, in 3 different modes of operation
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Implementation: 8051 (cont’d)
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dw8051 BFM
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Fully developed in SystemC
BFM supports
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timer 1, mode 0,1,2
serial port 0, mode 0,1,2,3
external interrupts
external memory accesses
SFR accesses
dw8051 cycle-accurate model
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What we learned today
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Ghosh et al co-verification strategy, using
SystemC, was presented
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C/C++ models are very efficiently compiled on
today architectures
No overhead for C-HDL interfacing is introduced
Performance estimates can be obtained from
model
C++ allows use of OO techniques to create BFM
and ISS, which enables re-use of them for
subsequent generations of the processor
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Complementary notes:
Assignments
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Take Assignment 8
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Due Date: Saturday, Khordad 12th
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