inst.eecs.berkeley.edu/~cs61c
CS61C : Machine Structures
Lecture #17 – Combinational Logic
2008-7-21
Albert Chae, Instructor
CS61C L17 Combinational Logic (1)
Chae, Summer 2008 © UCB
Review
• ISA is very important abstraction layer
• Contract between HW and SW
• Clocks control pulse of our circuits
• Voltages are analog, quantized to 0/1
• Circuit delays are fact of life
• Two types of circuits:
• Stateless Combinational Logic (&,|,~)
• State circuits (e.g., registers)
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Review
• State elements are used to:
• Build memories
• Control the flow of information between other state
elements and combinational logic
• D-flip-flops used to build registers
• Clocks tell us when D-flip-flops change
• Setup and Hold times important
• Finite State Machines extremely useful
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Review of Signal vocabulary
• T is the period
• Period is time from one rising edge to next
• Unit is seconds
• 1/T is the frequency
• Unit is hertz (1/s)
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Accumulator with proper timing
• reset signal shown.
• Also, in practice X might
not arrive to the adder at
the same time as Si-1
• Si temporarily is wrong,
but register always
captures correct value.
• In good circuits,
instability never happens
around rising edge of clk.
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Maximum Clock Frequency
Hint…
Frequency = 1/Period
• What is the maximum frequency of
this circuit?
Max Delay =Setup Time + CLK-to-Q Delay
+ CL Delay
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Pipelining to improve performance (1/2)
Extra Register are often added to help
speed up the clock rate.
Timing…
Note: delay of 1 clock cycle from input to output.
Clock period limited by propagation delay of adder/shifter.
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Pipelining to improve performance (2/2)
• Insertion of register allows higher clock
frequency.
• More outputs per second.
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Timing…
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General Model for Synchronous Systems
• Collection of CL blocks separated by registers.
• Registers may be back-to-back and CL blocks may be back-toback.
• Feedback is optional.
• Clock signal(s) connects only to clock input of registers. (NEVER
put it through a gate)
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Hardware Implementation of FSM
… Therefore a register is needed to hold the a representation of which
state the machine is in. Use a unique bit pattern for each state.
+
=
?
Combinational logic circuit is
used to implement a function
maps from present state and
input to next state and output.
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Combinational Logic
• FSMs had states and transitions
• How to we get from one state to the
next?
• Answer: Combinational Logic
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Truth Tables
0
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TT Example #1: 1 iff one (not both) a,b=1
a
0
0
1
1
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b
0
1
0
1
y
0
1
1
0
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TT Example #2: 2-bit adder
How
Many
Rows?
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TT Example #3: 32-bit unsigned adder
How
Many
Rows?
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TT Example #3: 3-input majority circuit
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Administrivia
• Midterm TODAY 2008-07-21@7-10pm, 155
Dwinelle
• Bring pencils and eraser!
• You can bring green sheet and one
handwritten double sided note sheet
• No calculator, laptop, etc.
• No stress… remember you can get it
clobbered
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Logic Gates (1/2)
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And vs. Or review – Dan’s mnemonic
AND Gate
Symbol
A
B
AN
D
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Definition
C
A
0
0
1
1
B
0
1
0
1
C
0
0
0
1
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Logic Gates (2/2)
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2-input gates extend to n-inputs
• N-input XOR is the
only one which isn’t
so obvious
• It’s simple: XOR is a
1 iff the # of 1s at its
input is odd
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Truth Table  Gates (e.g., majority circ.)
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Truth Table  Gates (e.g., FSM circ.)
PS Input NS Output
00
0
00
0
00
1
01
0
01
0
00
0
01
1
10
0
10
0
00
0
10
1
00
1
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or equivalently…
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Boolean Algebra
• George Boole, 19th Century
mathematician
• Developed a mathematical
system (algebra) involving
logic
• later known as “Boolean Algebra”
• Primitive functions: AND, OR and NOT
• The power of BA is there’s a one-to-one
correspondence between circuits made
up of AND, OR and NOT gates and
equations in BA
+ means OR,• means AND, x means NOT
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Boolean Algebra (e.g., for majority fun.)
y=a•b+a•c+b•c
y = ab + ac + bc
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Boolean Algebra (e.g., for FSM)
PS Input NS Output
00
0
00
0
00
1
01
0
01
0
00
0
01
1
10
0
10
0
00
0
10
1
00
1
or equivalently…
y = PS1 • PS0 • INPUT
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BA: Circuit & Algebraic Simplification
BA also great for
circuit verification
Circ X = Circ Y?
use BA to prove!
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Laws of Boolean Algebra
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Boolean Algebraic Simplification Example
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Canonical forms (1/2)
Sum-of-products
(ORs of ANDs)
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Canonical forms (2/2)
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Peer Instruction
A. (a+b)• (a+b) = b
1:
B. N-input gates can be thought of
2:
3:
cascaded 2-input gates. I.e.,
4:
(a ∆ bc ∆ d ∆ e) = a ∆ (bc ∆ (d ∆ e))
where ∆ is one of AND, OR, XOR, NAND 5:
6:
C. You can use NOR(s) with clever wiring 7:
8:
to simulate AND, OR, & NOT
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ABC
FFF
FFT
FTF
FTT
TFF
TFT
TTF
TTT
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A.
Peer Instruction Answer (B)
B.
N-input gates can be thought of cascaded 2-input
gates. I.e.,
(a ∆ bc ∆ d ∆ e) = a ∆ (bc ∆ (d ∆ e))
where ∆ is one of AND, OR, XOR, NAND…FALSE
Let’s confirm!
CORRECT 3-input
XYZ|AND|OR|XOR|NAND
000| 0 |0 | 0 | 1
001| 0 |1 | 1 | 1
010| 0 |1 | 1 | 1
011| 0 |1 | 0 | 1
100| 0 |1 | 1 | 1
101| 0 |1 | 0 | 1
110| 0 |1 | 0 | 1
111| 1 |1 | 1 | 0
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CORRECT 2-input
YZ|AND|OR|XOR|NAND
00| 0 |0 | 0 | 1
01| 0 |1 | 1 | 1
10| 0 |1 | 1 | 1
11| 1 |1 | 0 | 0
Chae, Summer 2008 © UCB
“And In conclusion…”
• Pipeline big-delay CL for faster clock
• Finite State Machines extremely useful
• You’ll see them again in 150, 152 & 164
• Use this table and techniques we
learned to transform from 1 to another
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Chae, Summer 2008 © UCB