Lecture #33: Some example circuits
• Last lecture:
– Edge triggers
– Registers
• This lecture:
– Example circuits
– shift registers
– Counters
– adders
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EE 42 fall 2004 lecture 33
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Examples of useful combinatorial
circuits
• There are several patterns of combinatorial logic
which appear fairly often, here are several
examples
• The examples will be given in terms of gates as
well as logic equations, but not in a minimal
representation, but just a clear example
• In most cases, a computer program such as
Verilog would be responsible for producing
optimal implementations anyway.
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Pattern recognizer
The output of this pattern recognition circuit is 1
only if the input is 10110, and otherwise zero
A
B
C
D
E
Q
Q  ( A  B  C  D  E)
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Decoder
•n inputs, 2n outputs
– one output is 1 for each possible input pattern,
all other outputs are 0
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A
B
O1 O2 O3 O4
0
0
1
1
0
1
0
1
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
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Decoder
•n inputs, 2n outputs
– one output is 1 for each possible input pattern,
all other outputs are 0
1
A
B
2
3
4
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CMOS switch
• A CMOS switch will allow a logic level to
pass if activated, does not allow current
through the gate if not activated
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Multiplexer (MUX)
•n-bit selector and 2n inputs, one output
– output equals one of the inputs, depending on
selector
I1
I2
I3
I4
A
B
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O
2 input decoder
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Buffer
• A buffer passes a logic level while increasing its drive
capability
• A design like the previous slide would likely be
implemented with a buffer at its output
Often, wider
transistors in
the second
stage
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Half Adder
• A half adder takes two bits and produces
their sum, with a carry
• It is called a half adder because it does not
have a carry input
A
B
Sum Output
Carry out
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Half adder
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A
B
O
C
0
0
0
0
0
1
1
0
1
0
1
0
1
1
0
1
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Full Adder
•Add two bits and carry-in,
produce one-bit sum
and carry-out.
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A B Cin S Cout
0 0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 0
0
0
1
1 0 0 1
1 0 1 0
1 1 0 0
0
1
1
1 1 1 1
1
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One bit Full adder
• A single bit full adder can be made from
two half adders and an or gate
A
B
O
Half adder C
Sum out
Carry in
Half adder
C
Carry out
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Full adder as a logic block
• We can use our full adder as a logic block
to make a multi-bit adder by cascading the
carry line
Sum
Cin
Full adder Cout
(one bit)
A
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B
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Three-bit Adder
Sum0
half adder
Sum1
Carry
Full adder
Sum2
Carry
Full adder
(one bit)
(one bit)
(one bit)
A0 B0
A1 B1
A2 B2
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Carry
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Adders
• It is interesting to note that in hardware, it
is typical to dedicate an adder for one
particular use, as contrasted with software
on a CPU, where numbers are moved
around to be added by a central adder.
• This is because the additional selectors
and wires to move around numbers takes
more area than just putting in separate
adders for each purpose.
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Some register based digital blocks
• There are also several common digital
blocks which are based around flip-flop
registers, such as multi-bit data registers,
shift registers, and counters
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Definition:Register
•A register is a collection of flip-flops with
similar controls and logic
•A register stores a multi-bit value.
– Stored values somehow related (e.g., form binary
value)
– Share clock, reset, and set lines
– Similar logic at each stage
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Registers
• Example: a collection of D-flip-flops, all controlled by a
common write enable (WE).
– When WE transitions from 1 to zero (falling edge), a n-bit value
D is written to register.
OUT1
Reset
“0”
OUT2
R S
D Q
OUT3
R S
D Q
R S
D Q
OUT4
R S
D Q
Write enable
IN1
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IN2
IN3
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IN4
18
Shift Register
• Holds samples of past input values and
shifts them in sequence into a string of flipflops
IN
D Q
D Q
D Q
D Q
OUT
shift
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Shift Register
• Holds samples of input
– Store input values in sequence
– 4-bit shift register used as a serial to parallel
converter:
OUT1
OUT2
OUT3
OUT4
IN
D Q
D Q
D Q
D Q
CLK
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Parallel to serial converter
Reset
“0”
R S
D Q
R S
D Q
R S
D Q
R S
D Q
Output
Shift
“0” literal
IN1
MUX
IN2
MUX
IN3
MUX
IN4
MUX
Load/Shift
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Shift Register Application
• Parallel-to-serial conversion for serial
transmission
parallel outputs
parallel inputs
serial transmission
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Pattern Recognizer
• Combinational function of input samples
– In this case, recognizing the pattern 1001 on
the single input signal
OUT
OUT1
IN
D Q
OUT2
D Q
OUT3
D Q
OUT4
D Q
CLK
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Use of counters
• Counters are often used when something
needs to happen a certain number of
times.
• Counters can be designed to be preset to
particular values, to count up or down,
and/or to trigger some action at a
particular count by the use of a pattern
recognizer.
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Binary Counter
• Logic between registers (not just multiplexer)
– XOR decides when bit should be toggled
– Always for low-order bit, only when first bit is true for
second bit, and so on
OUT1
D Q
OUT2
D Q
OUT3
D Q
OUT4
D Q
CLK
"1"
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Sequential Logic Summary
• Fundamental building block of circuits with state
– R-S latch, R-S master/slave, D master/slave, edge-triggered D FF
– Latch and flip-flop
• Timing methodologies
– Use of clocks
– Cascaded FFs work because prop delays exceed hold times
– Beware of clock skew
• Asynchronous inputs and their dangers
– Synchronizer failure: what it is and how to minimize its impact
• Basic registers
– Shift registers
– Pattern detectors
– Counters
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